On Fri, Dec 11, 2020 at 12:16:39PM +1100, David Gibson wrote:
> On Thu, Dec 10, 2020 at 09:54:18AM +0530, Bharata B Rao wrote:
> > On Wed, Dec 09, 2020 at 03:15:42PM +1100, Paul Mackerras wrote:
> > > On Mon, Oct 19, 2020 at 04:56:41PM +0530, Bharata B Rao wrote:
> > > > Implements H_RPT_INVALIDATE
Sometimes we can't read an error log from OPAL, and we print an error
message accordingly. But the OPAL userspace tools seem to like retrying a
lot, in which case we flood the kernel log with a lot of messages.
Change pr_err() to pr_err_ratelimited() to help with this.
Signed-off-by: Andrew Donne
-20201209
i386 randconfig-a002-20201209
i386 randconfig-a006-20201209
i386 randconfig-a003-20201209
i386 randconfig-a001-20201210
i386 randconfig-a004-20201210
i386 randconfig-a003-20201210
i386
01209
i386 randconfig-a003-20201209
i386 randconfig-a001-20201210
i386 randconfig-a004-20201210
i386 randconfig-a003-20201210
i386 randconfig-a002-20201210
i386 randconfig-a005-20201210
i386 randc
On Thu, Dec 10, 2020 at 09:54:18AM +0530, Bharata B Rao wrote:
> On Wed, Dec 09, 2020 at 03:15:42PM +1100, Paul Mackerras wrote:
> > On Mon, Oct 19, 2020 at 04:56:41PM +0530, Bharata B Rao wrote:
> > > Implements H_RPT_INVALIDATE hcall and supports only nested case
> > > currently.
> > >
> > > A K
The pull request you sent on Fri, 11 Dec 2020 11:25:43 +1100:
> https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
> tags/powerpc-5.10-6
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/47003b9971cc7c38737f21e07034502ca35ab7af
Thank you!
--
Deet-doot-d
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi Linus,
Please pull one final powerpc fix for 5.10:
The following changes since commit a1ee28117077c3bf24e5ab6324c835eaab629c45:
powerpc/64s/powernv: Fix memory corruption when saving SLB entries on MCE
(2020-12-02 23:16:40 +1100)
are availa
> On Dec 5, 2020, at 7:59 PM, Nicholas Piggin wrote:
>
> I'm still going to persue shoot-lazies for the merge window. As you
> see it's about a dozen lines and a if (IS_ENABLED(... in core code.
> Your change is common code, but a significant complexity (which
> affects all archs) so needs a lot
Cédric Le Goater writes:
> PowerNV systems can handle up to 4K guests and 1M interrupt numbers
> per chip. Increase the range of allowed interrupts to support a larger
> number of guests.
>
> Reviewed-by: Greg Kurz
> Signed-off-by: Cédric Le Goater
> ---
> arch/powerpc/Kconfig | 2 +-
> 1 file
Hi Michael,
On Thu, 10 Dec 2020 11:19:45 +1100 Michael Ellerman wrote:
>
> Stephen Rothwell writes:
> >
> > On Wed, 09 Dec 2020 15:44:35 +1100 Michael Ellerman
> > wrote:
> >>
> >> They should really be in DATA_DATA or similar shouldn't they?
> >
> > No other architecture appears t need th
Am 2020-12-10 18:38, schrieb Bjorn Helgaas:
On Wed, Dec 09, 2020 at 10:29:04PM +0200, Vladimir Oltean wrote:
On Wed, Dec 09, 2020 at 04:40:52PM +0100, Michael Walle wrote:
> Hopefully my mail client won't mess up the output that much.
I can reproduce on my LS1028A as well. The following fixes t
On Wed, Dec 09, 2020 at 10:29:04PM +0200, Vladimir Oltean wrote:
> On Wed, Dec 09, 2020 at 04:40:52PM +0100, Michael Walle wrote:
> > Hopefully my mail client won't mess up the output that much.
>
> I can reproduce on my LS1028A as well. The following fixes the bug for
> me. I did not follow the d
This is a simple cleanup to identify easily all flags of the XIVE
interrupt structure. The interrupts flagged with XIVE_IRQ_FLAG_NO_EOI
are the escalations used to wake up vCPUs in KVM. They are handled
very differently from the rest.
Reviewed-by: Greg Kurz
Signed-off-by: Cédric Le Goater
---
a
PowerNV systems can handle up to 4K guests and 1M interrupt numbers
per chip. Increase the range of allowed interrupts to support a larger
number of guests.
Reviewed-by: Greg Kurz
Signed-off-by: Cédric Le Goater
---
arch/powerpc/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
This flag was used to support the PHB4 LSIs on P9 DD1 and we have
stopped supporting this CPU when DD2 came out. See skiboot commit:
https://github.com/open-power/skiboot/commit/0b0d15e3c170
Reviewed-by: Greg Kurz
Signed-off-by: Cédric Le Goater
---
arch/powerpc/include/asm/opal-api.h |
When the XIVE resources are allocated at the HW level, the VP
structures describing the vCPUs of a guest are distributed among
the chips to optimize the PowerBUS usage. For best performance, the
guest vCPUs can be pinned to match the VP structure distribution.
Currently, the VP identifiers are ded
This flag was used to support the PHB4 LSIs on P9 DD1 and we have
stopped supporting this CPU when DD2 came out. See skiboot commit:
https://github.com/open-power/skiboot/commit/0b0d15e3c170
Reviewed-by: Greg Kurz
Signed-off-by: Cédric Le Goater
---
arch/powerpc/include/asm/opal-api.h | 2 +
Full state of the Linux interrupt descriptors can be dumped under
debugfs when compiled with CONFIG_GENERIC_IRQ_DEBUGFS. Add support for
the XIVE interrupt controller.
Signed-off-by: Cédric Le Goater
---
arch/powerpc/sysdev/xive/common.c | 58 +++
1 file changed, 58 i
This flag was used to support the P9 DD1 and we have stopped
supporting this CPU when DD2 came out. See skiboot commit:
https://github.com/open-power/skiboot/commit/0b0d15e3c170
Also, remove eoi handler which is now unused.
Reviewed-by: Greg Kurz
Signed-off-by: Cédric Le Goater
---
arch/pow
Hello,
The most important change is the removal of support of OPAL flags
required for P9 DD1. It provides a good cleanup of some complex
routines.
Thanks,
C.
Changes since v1:
- dropped the change on the allocation of the pages donated to the
XIVE IC. Needs a retest on a specific system.
The XIVE driver deals with CPU IPIs in a peculiar way. Each CPU has
its own XIVE IPI interrupt allocated at the HW level, for PowerNV, or
at the hypervisor level for pSeries. In practice, these interrupts are
not always used. pSeries/PowerVM prefers local doorbells for local
threads since they are
Introduce a vp_err() macro to standardize error reporting.
Reviewed-by: Greg Kurz
Signed-off-by: Cédric Le Goater
---
arch/powerpc/sysdev/xive/native.c | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/sysdev/xive/native.c
b/arch/po
This is useful to track allocation of the HW resources on per guest
basis. Making sure IPIs are local to the chip of the vCPUs reduces
rerouting between interrupt controllers and gives better performance
in case of pinning. Checking the distribution of VP structures on the
chips also helps in reduc
Previous patches removed the need of the first argument which was a
hack for Firwmware EOI. Remove it and flatten the routine which has
became simpler.
Reviewed-by: Greg Kurz
Signed-off-by: Cédric Le Goater
---
arch/powerpc/sysdev/xive/common.c | 72 ++-
1 file chang
The 'chip_id' field of the XIVE CPU structure is used to choose a
target for a source located on the same chip when possible. This field
is assigned on the PowerNV platform using the "ibm,chip-id" property
on pSeries under KVM when NUMA nodes are defined but it is undefined
under PowerVM. The XIVE
We hope one day to handle multiple irq_domain in the XIVE driver.
Start simple by setting the name using the DT node.
Signed-off-by: Cédric Le Goater
---
arch/powerpc/sysdev/xive/xive-internal.h | 4 ++--
arch/powerpc/sysdev/xive/common.c| 10 +-
arch/powerpc/sysdev/xive/native.
>> A local variable was used only within an if branch.
>> Thus move the definition for the variable “mm” into the corresponding
>> code block.
>
> You did nothing here except add a checkpatch warning :(
elfring@Sonne:~/Projekte/Linux/next-patched> scripts/checkpatch.pl
/home/elfring/Projekte/Bau/
From: Markus Elfring
Date: Thu, 10 Dec 2020 14:14:07 +0100
A local variable was used only within an if branch.
Thus move the definition for the variable “mm” into the corresponding
code block.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
drivers/
On Thu, Dec 10, 2020 at 03:35:38PM +0100, Markus Elfring wrote:
> From: Markus Elfring
> Date: Thu, 10 Dec 2020 14:14:07 +0100
>
> A local variable was used only within an if branch.
> Thus move the definition for the variable “mm” into the corresponding
> code block.
You did nothing here except
On 12/8/20 6:39 PM, Greg Kurz wrote:
> On Tue, 8 Dec 2020 16:11:20 +0100
> Cédric Le Goater wrote:
>
>> This flag was used to support the PHB4 LSIs on P9 DD1 and we have
>> stopped supporting this CPU when DD2 came out. See skiboot commit:
>>
>> https://github.com/open-power/skiboot/commit/0b0d
On 9/12/20 6:54 am, Tyrel Datwyler wrote:
Commit bd59380c5ba4 ("powerpc/rtas: Restrict RTAS requests from userspace")
introduced the following error when invoking the errinjct userspace
tool.
[root@ltcalpine2-lp5 librtas]# errinjct open
[327884.071171] sys_rtas: RTAS call blocked - exploit attem
On 24/11/20 1:41 am, Andrew Donnellan wrote:
On 9/10/20 12:20 pm, Andrew Donnellan wrote:
The Linux kernel for powerpc has an issue with the Run-Time
Abstraction Services (RTAS) interface, allowing root (or CAP_SYS_ADMIN
users) in a VM to overwrite some parts of memory, including kernel
memory
On Thu, 26 Nov 2020 17:59:49 +0100, Uwe Kleine-König wrote:
> The remove callback is only called for devices that were probed
> successfully before. As the matching probe function cannot complete
> without error if dev->match_id != PS3_MATCH_ID_SOUND, we don't have to
> check this here.
Applied t
On Fri, 27 Nov 2020 15:07:37 +0800, Youling Tang wrote:
> Use the common STABS_DEBUG and DWARF_DEBUG and ELF_DETAILS macro rule for
> the linker script in an effort.
Applied to powerpc/next.
[1/1] powerpc: Use common STABS_DEBUG and DWARF_DEBUG and ELF_DETAILS macro
https://git.kernel.org/p
On Wed, 2 Dec 2020 10:34:52 +0530, Srikar Dronamraju wrote:
> Currently, vcpu_is_preempted will return the yield_count for
> shared_processor. On a PowerVM LPAR, Phyp schedules at SMT8 core boundary
> i.e all CPUs belonging to a core are either group scheduled in or group
> scheduled out. This can
On Mon, 30 Nov 2020 09:14:06 +0530, Ravi Bangoria wrote:
> With CONFIG_PPC_8xx and CONFIG_XMON set, kernel build fails with
>
> arch/powerpc/xmon/xmon.c:1379:12: error: 'find_free_data_bpt' defined
> but not used [-Werror=unused-function]
>
> Fix it by enclosing find_free_data_bpt() inside #i
On Thu, 9 Apr 2020 16:13:37 +1000, Oliver O'Halloran wrote:
> If the platform decides to block enabling the device nothing is printed
> currently. This can lead to some confusion since the dmesg output will
> usually print an error with no context e.g.
>
> e1000e: probe of 0022:01:00.0 faile
On Thu, 19 Nov 2020 17:01:54 +0100, Oleg Nesterov wrote:
> Can we finally fix this problem? ;)
>
> My previous attempt was ignored, see
>
> https://lore.kernel.org/lkml/20190917121256.ga8...@redhat.com/
>
> Now that gpr_get() was changed to use membuf API we can make a simpler fix.
>
> [.
On Sat, 7 Nov 2020 12:33:05 +1000, Nicholas Piggin wrote:
> It's often useful to know the register state for interrupts in
> the stack frame. In the below example (with this patch applied),
> the important information is the state of the page fault.
>
> A blatant case like this probably rather sho
On Sat, 28 Nov 2020 17:07:20 +1000, Nicholas Piggin wrote:
> First patch is a nasty memory scribble introduced by me :( That
> should go into fixes.
>
> The next ones could wait for next merge window. They get things to the
> point where misbehaving or buggy guest isn't so painful for the host,
>
On Fri, 27 Nov 2020 00:09:58 +1100, Michael Ellerman wrote:
> In order to build VDSO32 for PPC64, we need to have CPU_FTRS_POSSIBLE
> and CPU_FTRS_ALWAYS independant of whether we are building the
> 32 bits VDSO or the 64 bits VDSO.
>
> Use #ifdef CONFIG_PPC64 instead of #ifdef __powerpc64__
Appl
On Tue, 24 Nov 2020 23:05:45 +1100, Michael Ellerman wrote:
> Our Kconfig allows NUMA to be enabled without SMP, but none of
> our defconfigs use that combination. This means it can easily be
> broken inadvertently by code changes, which has happened recently.
>
> Although it's theoretically possi
On Wed, 18 Nov 2020 14:39:10 -0800, Bill Wendling wrote:
> Normally all read-only sections precede SHF_WRITE sections. .dynamic and
> .got have the SHF_WRITE flag; .dynamic probably because of DT_DEBUG. LLD
> emits an error when this happens, so use "-z rodynamic" to mark .dynamic
> as read-only.
On Fri, 16 Oct 2020 17:01:51 -0700, Bill Wendling wrote:
> Both .dynamic and .got are RELRO sections and should be placed together,
> and LLD emits an error:
>
> ld.lld: error: section: .got is not contiguous with other relro sections
>
> Place them together to avoid this.
Applied to powerpc/n
On Mon, 30 Nov 2020 11:44:04 +1100, Jordan Niethe wrote:
> Commit 63ce271b5e37 ("powerpc/prom: convert PROM_BUG() to standard
> trap") added an EMIT_BUG_ENTRY for the trap after the branch to
> start_kernel(). The EMIT_BUG_ENTRY was for the address "0b", however the
> trap was not labeled with "0".
On Tue, 1 Dec 2020 11:52:03 +1100, Jordan Niethe wrote:
> This enables GENERIC_BUG_RELATIVE_POINTERS on Power so that 32-bit
> offsets are stored in the bug entries rather than 64-bit pointers.
> While this doesn't save space for 32-bit machines, use it anyway so
> there is only one code path.
App
On Mon, 7 Dec 2020 12:05:18 +1100, Jordan Niethe wrote:
> The value in CIABR persists across kexec which can lead to unintended
> results when the new kernel hits the old kernel's breakpoint. For
> example:
>
> 0:mon> bi $loadavg_proc_show
> 0:mon> b
>typeaddress
> 1 inst c00
On Tue, 1 Dec 2020 14:54:03 +0530, Harish wrote:
> Patch fixes uninitialized variable warning in bad_accesses test
> which causes the selftests build to fail in older distibutions
>
> bad_accesses.c: In function âbad_accessâ:
> bad_accesses.c:52:9: error: âxâ may be used uninitialized in t
On Mon, 30 Nov 2020 14:00:57 +0530, Ganesh Goudar wrote:
> To check machine check handling, add support to inject slb
> multihit errors.
Applied to powerpc/next.
[1/1] lkdtm/powerpc: Add SLB multihit test
https://git.kernel.org/powerpc/c/3ba150fb21207e4a7f4b600eb2dbbe83f94571fe
cheers
On Mon, 30 Nov 2020 16:29:49 +0100, Frederic Barrat wrote:
> Update bus speed definition for PCI Gen4 and 5.
Applied to powerpc/next.
[1/1] powerpc/pseries: Define PCI bus speed for Gen4 and Gen5
https://git.kernel.org/powerpc/c/c8754c517e37270a01b0561ad46ee647a721a09b
cheers
On Wed, 2 Dec 2020 01:44:27 +1100, Daniel Axtens wrote:
> I did an in-place build of the self-tests and found that it left
> the tree dirty.
>
> Add missed test binaries to .gitignore
Applied to powerpc/next.
[1/1] selftests/powerpc: update .gitignore
https://git.kernel.org/powerpc/c/f0812
On Wed, 2 Dec 2020 01:43:44 +1100, Daniel Axtens wrote:
> In a bunch of our security flushes, we use a comma rather than
> a semicolon to 'terminate' an assignment. Nothing breaks, but
> checkpatch picks it up if you copy it into another flush.
>
> Switch to semicolons for ending statements.
Appl
On Thu, 3 Dec 2020 15:28:07 +1100, Daniel Axtens wrote:
> It's sometimes handy to have a config that boots a bit like a system
> under secure boot (forcing lockdown=integrity, without needing any
> extra stuff like a command line option).
>
> This config file allows that, and also turns on a few a
On Wed, 25 Nov 2020 16:50:08 +0100, Christophe Lombard wrote:
> OpenCAPI 4.0/5.0 with TLBI/SLBI Snooping, is not used due to performance
> problems caused by the PAU having to process all incoming TLBI/SLBI
> commands which will cause them to back up on the PowerBus.
>
> When the Address Translati
On Thu, 22 Oct 2020 09:29:19 + (UTC), Christophe Leroy wrote:
> GCC 4.9 sometimes fails to build with "m<>" constraint in
> inline assembly.
>
> CC lib/iov_iter.o
> In file included from ./arch/powerpc/include/asm/cmpxchg.h:6:0,
> from ./arch/powerpc/include/asm/atomic.
On Tue, 13 Oct 2020 11:11:20 + (UTC), Christophe Leroy wrote:
> On 8xx, we get the following features:
>
> [0.00] cpu_features = 0x0100
> [0.00] possible= 0x0120
> [0.00] always = 0x
>
> This is not corr
On Sun, 18 Oct 2020 17:25:17 + (UTC), Christophe Leroy wrote:
> As stated in platform/44x/Kconfig, CONFIG_PPC_47x is not
> compatible with 440 and 460 variants.
>
> This is confirmed in asm/cache.h as L1_CACHE_SHIFT is different
> for 47x, meaning a kernel built for 47x will not run correctly
On Tue, 18 Aug 2020 17:19:11 + (UTC), Christophe Leroy wrote:
> This series leads to a reduction from 2.55s to 1.73s of
> the system CPU time with the following microbench app
> on an mpc832x with KUAP (approx 32%)
>
> This series replaces copies to users by unsafe_put_user() and friends
> wit
On Wed, 25 Nov 2020 07:10:46 + (UTC), Christophe Leroy wrote:
> Since commit 2b279c0348af ("powerpc/32s: Allow mapping with BATs with
> DEBUG_PAGEALLOC"), there is no real situation where mapping without
> BATs is required.
>
> In order to simplify memory handling, always map kernel text
> and
On Sun, 27 Sep 2020 09:16:16 + (UTC), Christophe Leroy wrote:
> This series modernises the setup of VDSO:
> - Switch to using _install_special_mapping() which has replaced
> install_special_mapping()
> - Move datapage in front of text like most other architectures to simplify
> its localisati
On Fri, 4 Dec 2020 10:35:38 + (UTC), Christophe Leroy wrote:
> Since some time now, printk() adds carriage return, leading to
> unusable xmon output:
>
> [ 54.288722] sysrq: Entering xmon
> [ 54.292209] Vector: 0 at [cace3d2c]
> [ 54.292274] pc:
> [ 54.292331] c0023650
> [ 54.29
On Thu, 1 Oct 2020 10:59:20 + (UTC), Christophe Leroy wrote:
> SPRN_VTB and CPU_FTR_ARCH_207S are always defined,
> no need of an ifdef.
Applied to powerpc/next.
[1/1] powerpc/time: Remove ifdef in get_vtb()
https://git.kernel.org/powerpc/c/c3cb5dbd85dbd9ae51fadf867782dc34806f04d8
chee
On Mon, 12 Oct 2020 08:02:30 + (UTC), Christophe Leroy wrote:
> Since commit 10b35d9978ac ("[PATCH] powerpc: merged asm/cputable.h"),
> CPU_FTR_COHERENT_ICACHE has always been defined.
>
> Remove the #ifndef CPU_FTR_COHERENT_ICACHE block.
Applied to powerpc/next.
[1/1] powerpc/mm: Remove use
On Mon, 12 Oct 2020 08:05:49 + (UTC), Christophe Leroy wrote:
> Only mpc83xx will set MMU_FTR_NEED_DTLB_SW_LRU and its
> definition is enclosed in #ifdef CONFIG_PPC_83xx.
>
> Make MMU_FTR_NEED_DTLB_SW_LRU possible only when
> CONFIG_PPC_83xx is set.
Applied to powerpc/next.
[1/1] powerpc/mm:
On Sat, 10 Oct 2020 17:30:59 + (UTC), Christophe Leroy wrote:
> MMU_FTR_TYPE_44x cannot be checked by cpu_has_feature()
>
> Use mmu_has_feature() instead
Applied to powerpc/next.
[1/1] powerpc/mm: Fix verification of MMU_FTR_TYPE_44x
https://git.kernel.org/powerpc/c/17179aeb9d34cc81e1a
On Mon, 12 Oct 2020 08:04:24 + (UTC), Christophe Leroy wrote:
> MMU_FTR_PPCAS_ARCH_V2 is defined in cpu_table.h
> as MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE.
>
> MMU_FTR_TLBIEL and MMU_FTR_16M_PAGE are defined in mmu.h
>
> MMU_FTR_PPCAS_ARCH_V2 is used only in mmu.h and it is used only once.
>
> [
On Sat, 21 Nov 2020 17:59:19 + (UTC), Christophe Leroy wrote:
> ioreadXX()/ioreadXXbe() accessors are equivalent to ppc
> in_leXX()/in_be16() accessors but they are not inlined.
>
> Since commit 0eb573682872 ("powerpc/kerenl: Enable EEH for IO
> accessors"), the 'le' versions are equivalent to
On Tue, 17 Nov 2020 05:07:58 + (UTC), Christophe Leroy wrote:
> There is no defconfig selecting CONFIG_E200, and no platform.
>
> e200 is an earlier version of booke, a predecessor of e500,
> with some particularities like an unified cache instead of both an
> instruction cache and a data cach
On Mon, 12 Oct 2020 08:02:13 + (UTC), Christophe Leroy wrote:
> G2_LE has a 603 core, add CPU_FTR_NOEXECUTE.
Applied to powerpc/next.
[1/1] powerpc/feature: Add CPU_FTR_NOEXECUTE to G2_LE
https://git.kernel.org/powerpc/c/197493af414ee22427be3343637ac290a791925a
cheers
On Mon, 23 Nov 2020 21:40:40 -0500, Athira Rajeev wrote:
> On systems without any specific PMU driver support registered, running
> 'perf record' with âintr-regs will crash ( perf record -I ).
>
> The relevant portion from crash logs and Call Trace:
>
> Unable to handle kernel paging request
On Thu, 26 Nov 2020 11:54:37 -0500, Athira Rajeev wrote:
> Patchset contains PMU fixes for power10.
>
> This patchset contains 7 patches.
> Patch1 includes fix to update event code with radix_scope_qual
> bit in power10.
> Patch2 and Patch3 updates the event group constraints for L2/L3
> and thres
On Tue, 1 Dec 2020 04:28:00 -0500, Athira Rajeev wrote:
> The power_pmu_event_init() callback access per-cpu variable
> (cpu_hw_events) to check for event constraints and Branch Stack
> (BHRB). Current usage is to disable preemption when accessing the
> per-cpu variable, but this does not prevent t
On Fri, 27 Nov 2020 10:14:02 +0530, Aneesh Kumar K.V wrote:
> This patch series implements KUAP and KUEP with hash translation mode using
> memory keys. The kernel now uses memory protection key 3 to control access
> to the kernel. Kernel page table entries are now configured with key 3.
> Access t
On Tue, 8 Dec 2020 08:45:39 +0530, Aneesh Kumar K.V wrote:
> This partially reverts commit eb232b162446 ("powerpc/book3s64/kuap: Improve
> error reporting with KUAP") and update the fault handler to print
>
> [ 55.022514] Kernel attempted to access user page (7e6725b7) - exploit
> attempt?
On Wed, 2 Dec 2020 11:52:22 +1100, Alexey Kardashevskiy wrote:
> When a passthrough IO adapter is removed from a pseries machine using hash
> MMU and the XIVE interrupt mode, the POWER hypervisor expects the guest OS
> to clear all page table entries related to the adapter. If some are still
> pres
On Sun, 22 Nov 2020 18:38:28 +1100, Alexey Kardashevskiy wrote:
> We execute certain NPU2 setup code (such as mapping an LPID to a device
> in NPU2) unconditionally if an Nvlink bridge is detected. However this
> cannot succeed on POWER8NVL machines and errors appear in dmesg. This is
> harmless as
From: "Gautham R. Shenoy"
Hi,
This is the v2 of the patchset to extend parsing of "ibm,thread-groups" property
to discover the Shared-L2 cache information.
The previous versions can be found here :
v2 :
https://lore.kernel.org/linuxppc-dev/1607533700-5546-1-git-send-email-...@linux.vnet.ibm.c
From: "Gautham R. Shenoy"
On platforms which have the "ibm,thread-groups" property, the per-cpu
variable cpu_l1_cache_map keeps a track of which group of threads
within the same core share the L1 cache, Instruction and Data flow.
This patch renames the variable to "thread_group_l1_cache_map" to
From: "Gautham R. Shenoy"
init_thread_group_l1_cache_map() initializes the per-cpu cpumask
thread_group_l1_cache_map with the core-siblings which share L1 cache
with the CPU. Make this function generic to the cache-property (L1 or
L2) and update a suitable mask. This is a preparatory patch for th
From: "Gautham R. Shenoy"
On POWER systems, groups of threads within a core sharing the L2-cache
can be indicated by the "ibm,thread-groups" property array with the
identifier "2".
This patch adds support for detecting this, and when present, populate
the populating the cpu_l2_cache_mask of ever
From: "Gautham R. Shenoy"
On POWER platforms where only some groups of threads within a core
share the L2-cache (indicated by the ibm,thread-groups device-tree
property), we currently print the incorrect shared_cpu_map/list for
L2-cache in the sysfs.
This patch reports the correct shared_cpu_map
From: "Gautham R. Shenoy"
The "ibm,thread-groups" device-tree property is an array that is used
to indicate if groups of threads within a core share certain
properties. It provides details of which property is being shared by
which groups of threads. This array can encode information about
multip
On 09.12.20 12:27, Laurent Pinchart wrote:
Hi,
>>> I wonder if this shouldn't be dropped instead, commented-out code isn't
>>> very useful.
>>
>> Indeed. Shall I send a separate patch for that ?
>
> Yes, that would make sense.
Okay, I'm currently doing a more in-depth rework. I'll send another
On 12/8/20 4:11 PM, Cédric Le Goater wrote:
> Hello,
>
> The most important change is the removal of support of OPAL flags
> required for P9 DD1. It provides a good cleanup of some complex
> routines.
>
> The series also includes a change on how the pages donated to the XIVE
> IC are allocated in
In accordance with the Generic EHCI/OHCI bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible
nodes are correctl
As the subject states this series is an attempt to harmonize the xHCI,
EHCI, OHCI and DWC USB3 DT nodes with the DT schema introduced in the
framework of the patchset [1].
Firstly as Krzysztof suggested we've deprecated a support of DWC USB3
controllers with "synopsys,"-vendor prefix compatible st
Intel Keem Bay DWC3 compatible DT nodes are supposed to have a DWC USB3
compatible sub-node to describe a fully functioning USB interface. Let's
use the available DWC USB3 DT schema to validate the Intel Keem Bay DWC3
sub-nodes.
Note since the generic DWC USB3 DT node is supposed to be named as ge
Qualcomm msm8996/sc7180/sdm845 DWC3 compatible DT nodes are supposed to
have a DWC USB3 compatible sub-node to describe a fully functioning USB
interface. Let's use the available DWC USB3 DT schema to validate the
Qualcomm DWC3 sub-nodes.
Note since the generic DWC USB3 DT node is supposed to be n
TI Keystone DWC3 compatible DT node is supposed to have a DWC USB3
compatible sub-node to describe a fully functioning USB interface.
Since DWC USB3 has now got a DT schema describing its DT node, let's make
sure the TI Keystone DWC3 sub-node passes validation against it.
Signed-off-by: Serge Semi
Amlogic G12A USB DT sub-nodes are supposed to be compatible with the
generic DWC USB2 and USB3 devices. Since now we've got DT schemas for
both of the later IP cores let's make sure that the Amlogic G12A USB
DT nodes are fully evaluated including the DWC sub-nodes.
Signed-off-by: Serge Semin
Revi
An empty snps,quirk-frame-length-adjustment won't cause any change
performed by the driver. Moreover the DT schema validation will fail,
since it expects the property being assigned with some value. So set
fix the example by setting a valid FL-adj value in accordance with
Neil Armstrong comment.
L
In accordance with the IP core databook the
snps,quirk-frame-length-adjustment property can be set within [0, 0x3F].
Let's make sure the DT schema applies a correct constraints on the
property.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/usb/snps,dw
In accordance with the driver comments the PIPE3 de-emphasis can be tuned
to be either -6dB, -2.5dB or disabled. Let's add the de-emphasis
property constraints so the DT schema would make sure the controller DT
node is equipped with correct value.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herri
The controller driver supports two types of DWC USB3 devices: with a
common interrupt lane and with individual interrupts for each mode. Add
support for both these cases to the DWC USB3 DT schema.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
---
Changelog v2:
- Grammar fix: "s/both of t
DWC USB3 DT node is supposed to be compliant with the Generic xHCI
Controller schema, but with additional vendor-specific properties, the
controller-specific reference clocks and PHYs. So let's convert the
currently available legacy text-based DWC USB3 bindings to the DT schema
and make sure the DW
The DWC USB3 driver and some DTS files like Exynos 5250, Keystone k2e, etc
expects the DWC USB3 DT node to have the compatible string with the
"synopsys" vendor prefix. Let's add the corresponding compatible string to
the controller DT schema, but mark it as deprecated seeing the Synopsys,
Inc. is
For some reason the "brcm,xhci-brcm-v2" compatible string has been missing
in the original bindings file. Add it to the Generic xHCI Controllers DT
schema since the controller driver expects it to be supported.
Signed-off-by: Serge Semin
Acked-by: Florian Fainelli
Reviewed-by: Rob Herring
---
Currently the DT bindings of Generic xHCI Controllers are described by
means of the legacy text file. Since such format is deprecated in favor of
the DT schema, let's convert the Generic xHCI Controllers bindings file to
the corresponding yaml files. There will be two of them: a DT schema for
the x
The host controller device might be designed to work for the particular
products or applications. In that case its DT node is supposed to be
equipped with the tpl-support property.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
---
Changelog v2:
- Grammar fix: "s/it'/its"
- Discard '|' fr
With minor peculiarities (like uploading some vendor-specific firmware)
these are just Generic xHCI controllers fully compatible with its
properties. Make sure the Renesas USB xHCI DT nodes are also validated
against the Generic xHCI DT schema.
Signed-off-by: Serge Semin
Reviewed-by: Rob Herring
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