As 601 is gone, CONFIG_PPC_BOO3S_6xx and CONFIG_PPC_BOOK3S_32
are dedundant.
Remove CONFIG_PPC_BOOK3S_6xx.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/cputable.c | 4 ++--
arch/powerpc/platforms/Kconfig.cputype | 6 +-
2 files changed, 3 insertions(+), 7 deletions(-)
di
early_mmu_init() is independent of MMU type and not
directly linked to tlb handling.
In a following patch, tlb.c will be restricted to HASH mmu.
Move early_mmu_init() into mmu.c which is common.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/book3s32/mmu.c | 4
arch/powerpc/mm/book3s
flush_hash_entry() is a simple function calling
flush_hash_pages() if it's a hash MMU or doing nothing otherwise.
Inline it.
And use it also in __ptep_test_and_clear_young().
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 17 +++--
arch/powerpc/i
On book3s/32, tlb_flush() does nothing when the CPU has a hash table,
it calls _tlbia() otherwise.
Inline it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/tlbflush.h | 11 +++
arch/powerpc/mm/book3s32/tlb.c| 15 ---
2 files changed,
flush_range() handle both the MMU_FTR_HPTE_TABLE case and
the other case.
The non MMU_FTR_HPTE_TABLE case is trivial as it is only a call
to _tlbie()/_tlbia() which is not worth a dedicated function.
Make flush_range() a hash specific and call it from tlbflush.h based
on mmu_has_feature(MMU_FTR_H
flush_tlb_range() and flush_tlb_kernel_range() are trivial calls to
flush_range().
Make flush_range() global and inline flush_tlb_range()
and flush_tlb_kernel_range().
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/tlbflush.h | 15 --
arch/powerpc/mm/book3s32/tlb
flush_tlb_mm() and flush_tlb_page() handle both the MMU_FTR_HPTE_TABLE
case and the other case.
The non MMU_FTR_HPTE_TABLE case is trivial as it is only a call
to _tlbie()/_tlbia() which is not worth a dedicated function.
Make flush_tlb_mm() and flush_tlb_page() hash specific and call
them from t
_tlbie() and _tlbia() are used only on 603 cores while the
other functions are used only on cores having a hash table.
Move them into a new file named nohash_low.S
Add mmu_hash_lock var is used by both, it needs to go
in a common file.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/book3s
Hash var is used only locally in mmu.c now.
No need to set it in head_32.S anymore.
Make it static and initialises it to the early hash table.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_book3s_32.S | 5 -
arch/powerpc/mm/book3s32/mmu.c | 2 +-
arch/powerpc/mm/mmu_de
In order to use _tlbie() and _tlbia() directly
from asm/book3s/32/tlbflush.h, move their prototypes
from mm/mm_decl.h to there.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/tlbflush.h | 4
arch/powerpc/mm/mmu_decl.h| 3 ---
2 files changed, 4 in
Hash related vars are used at init only.
Declare them in __initdata.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/book3s32/mmu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c
index c0c0f2a50f86.
On non SMP, _tlbie() is just a tlbie plus a sync instruction.
Make it static inline.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/tlbflush.h | 7 +++
arch/powerpc/mm/book3s32/hash_low.S | 7 ++-
2 files changed, 9 insertions(+), 5 deletions(-)
diff -
flush_tlb_page_nohash() was removed by
commit 703b41ad1a87 ("powerpc/mm: remove flush_tlb_page_nohash")
Remove stale prototype and comment.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/tlbflush.h | 1 -
arch/powerpc/include/asm/nohash/tlbflush.h| 1 -
2 files chang
We now have an early hash table on hash MMU, so no need to check
Hash var to know if the Hash table is set of not.
Use mmu_has_feature(MMU_FTR_HPTE_TABLE) instead. This will allow
optimisation via jump_label.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/book3s32/mmu.c | 2 +-
arch/power
On 8xx, we get the following features:
[0.00] cpu_features = 0x0100
[0.00] possible= 0x0120
[0.00] always = 0x
This is not correct. As CONFIG_PPC_8xx is mutually exclusive with all
other configurations, the
This table is used only locally. Declare it static.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/book3s32/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c
index a59e7ec98180..eceb55c12fe9 100644
--- a
On the same principle as commit 773edeadf672 ("powerpc/mm: Add mask
of possible MMU features"), add mask for MMU features that are
always there in order to optimise out dead branches.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/mmu.h | 25 +
1 file change
On Thu, Oct 22, 2020 at 4:33 PM Ravi Bangoria
wrote:
>
>
>
> On 10/22/20 10:41 AM, Jordan Niethe wrote:
> > On Thu, Oct 22, 2020 at 2:40 PM Ravi Bangoria
> > wrote:
> >>
> >> POWER10_DD1 feature flag will be needed while adding
> >> conditional code that applies only for Power10 DD1.
> >>
> >> Si
On 10/22/20 10:41 AM, Jordan Niethe wrote:
On Thu, Oct 22, 2020 at 2:40 PM Ravi Bangoria
wrote:
POWER10_DD1 feature flag will be needed while adding
conditional code that applies only for Power10 DD1.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/cputable.h | 8 ++--
ar
On Thu, Oct 22, 2020 at 2:40 PM Ravi Bangoria
wrote:
>
> POWER10_DD1 feature flag will be needed while adding
> conditional code that applies only for Power10 DD1.
>
> Signed-off-by: Ravi Bangoria
> ---
> arch/powerpc/include/asm/cputable.h | 8 ++--
> arch/powerpc/kernel/dt_cpu_ftrs.c | 3
Ganesh writes:
> On 7/24/20 12:09 PM, Ganesh Goudar wrote:
>
>> When an UE or memory error exception is encountered the MCE handler
>> tries to find the pfn using addr_to_pfn() which takes effective
>> address as an argument, later pfn is used to poison the page where
>> memory error occurred, rec
POWER10 DD1 has an issue where it generates watchpoint exceptions when it
shouldn't. The conditions where this occur are:
- octword op
- ending address of DAWR range is less than starting address of op
- those addresses need to be in the same or in two consecutive 512B
blocks
- 'op address
POWER10_DD1 feature flag will be needed while adding
conditional code that applies only for Power10 DD1.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/cputable.h | 8 ++--
arch/powerpc/kernel/dt_cpu_ftrs.c | 3 +++
arch/powerpc/kernel/prom.c | 9 +
3 files chan
On Wed, 21 Oct 2020, Laurent Vivier wrote:
> Le 21/10/2020 à 01:43, Finn Thain a écrit :
>
> > Laurent, can we avoid the irq == 0 warning splat like this?
> >
> > diff --git a/drivers/tty/serial/pmac_zilog.c
> > b/drivers/tty/serial/pmac_zilog.c
> > index 96e7aa479961..7db600cd8cc7 100644
> > -
Laurent Vivier writes:
> Le 20/10/2020 à 20:32, Greg KH a écrit :
>> On Tue, Oct 20, 2020 at 08:19:26PM +0200, Laurent Vivier wrote:
>>> Le 20/10/2020 à 19:37, Greg KH a écrit :
On Tue, Oct 20, 2020 at 06:37:41PM +0200, Laurent Vivier wrote:
> Le 20/10/2020 à 18:28, Greg KH a écrit :
Use a more generic form for __section that requires quotes to avoid
complications with clang and gcc differences.
Remove the quote operator # from compiler_attributes.h __section macro.
Convert all unquoted __section(foo) uses to quoted __section("foo").
Also convert __attribute__((section("foo")
Christophe Leroy writes:
> Le 21/10/2020 à 10:53, Madhavan Srinivasan a écrit :
>> In power10 DD1, there is an issue where the
>> Sampled Instruction Address Register (SIAR)
>> not latching to the sampled address during
>> random sampling. This results in value of 0s
>> in the SIAR. Patch adds a c
On Wed, Oct 21, 2020 at 06:13:01PM +0200, Greg KH wrote:
> On Fri, Sep 25, 2020 at 06:51:39AM +0200, Christoph Hellwig wrote:
> > From: David Laight
> >
> > This lets the compiler inline it into import_iovec() generating
> > much better code.
> >
> > Signed-off-by: David Laight
> > Signed-off-b
In commit 269e583357df ("powerpc/eeh: Delete eeh_pe->config_addr") the
following simplification was made:
- if (!pe->addr && !pe->config_addr) {
+ if (!pe->addr) {
eeh_stats.no_cfg_addr++;
return 0;
}
This introduced a bug which causes EEH check
From: Greg KH
> Sent: 21 October 2020 17:13
>
> On Fri, Sep 25, 2020 at 06:51:39AM +0200, Christoph Hellwig wrote:
> > From: David Laight
> >
> > This lets the compiler inline it into import_iovec() generating
> > much better code.
> >
> > Signed-off-by: David Laight
> > Signed-off-by: Christoph
Hello,
apparently this has not received any (public) comments.
Maybe resend without the RFC status?
Clearly the kernel interface must be defined first, and then ndctl can
follow and make use of it.
Thanks
Michal
On Mon, May 18, 2020 at 04:38:10PM +0530, Vaibhav Jain wrote:
> The patch-set pro
Le 21/10/2020 à 16:25, Aneesh Kumar K.V a écrit :
Christophe Leroy writes:
Le 12/10/2020 à 17:39, Christophe Leroy a écrit :
On the same principle as commit 773edeadf672 ("powerpc/mm: Add mask
of possible MMU features"), add mask for MMU features that are
always there in order to optimise
On Fri, Sep 25, 2020 at 06:51:39AM +0200, Christoph Hellwig wrote:
> From: David Laight
>
> This lets the compiler inline it into import_iovec() generating
> much better code.
>
> Signed-off-by: David Laight
> Signed-off-by: Christoph Hellwig
> ---
> fs/read_write.c | 179
On Wed, Oct 21, 2020 at 11:00:36AM +0800, Chunfeng Yun wrote:
> On Tue, 2020-10-20 at 14:20 +0300, Serge Semin wrote:
> > The generic USB HCD properties have been described in the legacy bindings
> > text file: Documentation/devicetree/bindings/usb/generic.txt . Let's
> > convert it' content into t
Christophe Leroy writes:
> Le 12/10/2020 à 17:39, Christophe Leroy a écrit :
>> On the same principle as commit 773edeadf672 ("powerpc/mm: Add mask
>> of possible MMU features"), add mask for MMU features that are
>> always there in order to optimise out dead branches.
>>
>> Signed-off-by: Chris
Le 12/10/2020 à 17:39, Christophe Leroy a écrit :
On the same principle as commit 773edeadf672 ("powerpc/mm: Add mask
of possible MMU features"), add mask for MMU features that are
always there in order to optimise out dead branches.
Signed-off-by: Christophe Leroy
---
v2: Features must be a
Le 21/10/2020 à 10:53, Madhavan Srinivasan a écrit :
In power10 DD1, there is an issue where the
Sampled Instruction Address Register (SIAR)
not latching to the sampled address during
random sampling. This results in value of 0s
in the SIAR. Patch adds a check to use regs->nip
when SIAR is zer
In power10 DD1, there is an issue where the
Sampled Instruction Address Register (SIAR)
not latching to the sampled address during
random sampling. This results in value of 0s
in the SIAR. Patch adds a check to use regs->nip
when SIAR is zero.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/
From: Athira Rajeev
While setting the processor mode for any sample, `perf_get_misc_flags`
expects the privilege level to differentiate the userspace and kernel
address. On power10 DD1, there is an issue that causes [MSR_HV MSR_PR] bits
of Sampled Instruction Event Register (SIER) not to be set f
From: Athira Rajeev
By setting exclude_kernel for user space profiling, we set the
freeze bits in Monitor Mode Control Register. Due to hardware
limitation, sometimes, Sampled Instruction Address register (SIAR)
captures kernel address even when counter freeze bits are set in
Monitor Mode Control
From: Athira Rajeev
In power10 DD1, there is an issue that causes the SIAR_VALID
bit of Sampled Instruction Event Register(SIER) not to be
set. But the SIAR_VALID bit is used for fetching the instruction
address from Sampled Instruction Address Register(SIAR), and
marked events are sampled only i
From: Athira Rajeev
Add a new power PMU flag "PPMU_P10_DD1" which can be
used to conditionally add any code path for power10 DD1 processor
version. Also modify power10 PMU driver code to set this
flag only for DD1, based on the Processor Version Register (PVR)
value.
Signed-off-by: Athira Rajeev
Le 21/10/2020 à 01:43, Finn Thain a écrit :
> On Tue, 20 Oct 2020, Brad Boyer wrote:
>
>>
>> Wouldn't it be better to rearrange this code to only run if the devices
>> are present? This is a macio driver on pmac and a platform driver on
>> mac, so shouldn't it be possible to only run this code w
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