On Sun, Feb 03, 2019 at 05:49:02PM +0100, Christian Zigotzky wrote:
> OK, next step: b50f42f0fe12965ead395c76bcb6a14f00cdf65b (powerpc/dma: use
> the dma_direct mapping routines)
>
> git clone git://git.infradead.org/users/hch/misc.git -b powerpc-dma.6 a
>
> git checkout b50f42f0fe12965ead395c76bc
On 25-01-19, 05:54, Peng Ma wrote:
> Hi Vinod,
>
> Sorry to replay late.
> 1:This patch has already send to the patchwork.
> Please see the patch link: https://patchwork.kernel.org/patch/10741521/
> 2:I have already compile the fsl patches on arm and powerpc after patched
> https://patchwor
On Sat, Jan 26, 2019 at 09:25:04AM +0100, Cédric Le Goater wrote:
> Was there a crashing.org shutdown ?
>
> Received: from gate.crashing.org (gate.crashing.org [63.228.1.57])
> by in5.mail.ovh.net (Postfix) with ESMTPS id 43mYnj0nrlz1N7KC
> for ; Fri, 25 Jan 2019 22:38:00 + (UTC
On Mon, Jan 07, 2019 at 07:43:26PM +0100, Cédric Le Goater wrote:
> When the VM is stopped in a migration sequence, the sources are masked
> and the XIVE IC is synced to stabilize the EQs. When done, the KVM
> ioctl KVM_DEV_XIVE_SAVE_EQ_PAGES is called to mark dirty the EQ pages.
>
> The migration
On Mon, Jan 07, 2019 at 08:10:04PM +0100, Cédric Le Goater wrote:
> At a VCPU level, the state of the thread context interrupt management
> registers needs to be collected. These registers are cached under the
> 'xive_saved_state.w01' field of the VCPU when the VPCU context is
> pulled from the HW
On Mon, Jan 07, 2019 at 07:43:27PM +0100, Cédric Le Goater wrote:
> Theses are use to capure the XIVE EAS table of the KVM device, the
> configuration of the source targets.
>
> Signed-off-by: Cédric Le Goater
> ---
> arch/powerpc/include/uapi/asm/kvm.h | 11
> arch/powerpc/kvm/book3s_xiv
On Mon, Jan 07, 2019 at 07:43:25PM +0100, Cédric Le Goater wrote:
> When migration of a VM is initiated, a first copy of the RAM is
> transferred to the destination before the VM is stopped. At that time,
> QEMU needs to perform a XIVE quiesce sequence to stop the flow of
> event notifications and
On Mon, Jan 07, 2019 at 07:43:28PM +0100, Cédric Le Goater wrote:
> These are used to capture the XIVE END table of the KVM device. It
> relies on an OPAL call to retrieve from the XIVE IC the EQ toggle bit
> and index which are updated by the HW when events are enqueued in the
> guest RAM.
>
> Si
On Wed, Jan 23, 2019 at 05:56:26PM +0100, Cédric Le Goater wrote:
> On 1/22/19 6:14 AM, Paul Mackerras wrote:
> > On Mon, Jan 07, 2019 at 07:43:20PM +0100, Cédric Le Goater wrote:
> >> The ESB MMIO region controls the interrupt sources of the guest. QEMU
> >> will query an fd (GET_ESB_FD ioctl) and
On Mon, Jan 07, 2019 at 07:43:24PM +0100, Cédric Le Goater wrote:
> The guest physical address of the event queue will be part of the
> state to transfer in the migration. Cache its value when the queue is
> configured, it will save us an OPAL call.
That doesn't sound like a very compelling case -
On Mon, Jan 07, 2019 at 07:43:21PM +0100, Cédric Le Goater wrote:
> Interrupt sources are simply created at the OPAL level and then
> MASKED. KVM only needs to know about their type: LSI or MSI.
This commit message isn't very illuminating.
>
> Signed-off-by: Cédric Le Goater
> ---
> arch/power
On Mon, Jan 07, 2019 at 07:43:18PM +0100, Cédric Le Goater wrote:
> This will let the guest create a memory mapping to expose the ESB MMIO
> regions used to control the interrupt sources, to trigger events, to
> EOI or to turn off the sources.
>
> Signed-off-by: Cédric Le Goater
> ---
> arch/pow
On Mon, Jan 07, 2019 at 07:43:17PM +0100, Cédric Le Goater wrote:
> This is the basic framework for the new KVM device supporting the XIVE
> native exploitation mode. The user interface exposes a new capability
> and a new KVM device to be used by QEMU.
>
> Internally, the interface to the new KVM
On Mon, Feb 4, 2019 at 3:45 PM Alexey Kardashevskiy wrote:
>
>
>
> On 01/02/2019 11:42, Oliver O'Halloran wrote:
> > The IODA reset is used to flush out any OS controlled state from the PHB.
> > This reset can fail if a PHB fatal error has occurred in early boot,
> > probably due to a because of a
On 01/02/2019 11:42, Oliver O'Halloran wrote:
> The IODA reset is used to flush out any OS controlled state from the PHB.
> This reset can fail if a PHB fatal error has occurred in early boot,
> probably due to a because of a bad device. We already do a fundemental
> reset of the device in some
This adds test cases for the addc[.] instruction.
Signed-off-by: Sandipan Das
---
arch/powerpc/include/asm/ppc-opcode.h | 1 +
arch/powerpc/lib/sstep_tests.c| 212 ++
2 files changed, 213 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/
This adds test cases for the add[.] instruction.
Signed-off-by: Sandipan Das
---
arch/powerpc/lib/sstep_tests.c | 194 +
1 file changed, 194 insertions(+)
diff --git a/arch/powerpc/lib/sstep_tests.c b/arch/powerpc/lib/sstep_tests.c
index a610c778044d..fe6201a2add
This adds a selftest framework for the in-kernel instruction
emulation infrastructure. This currently does not support the
load/store and branch instructions and is limited to integer
ALU instructions. Support for SPRs is also limited to LR, CR
and XER for now.
Tests run at boot time if CONFIG_DEB
This adds the bitmask definitions of D, SI and UI fields
found in D-form instructions.
Signed-off-by: Sandipan Das
---
arch/powerpc/include/asm/ppc-opcode.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
index
This adds the bitmask definition for the Record bit that
is available at the end (bit 31) of some instructions.
Signed-off-by: Sandipan Das
---
arch/powerpc/include/asm/ppc-opcode.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/
This aims to add a test infrastructure for the in-kernel instruction
emulation code. This is currently limited to testing only the basic
integer operations and supports verification of the GPRs, LR, XER and
CR.
There can be multiple test cases for each instruction. Each test case
has to be provide
On Friday, February 1, 2019 4:43:52 PM IST Michael Ellerman wrote:
> Michael Ellerman writes:
>
> > Adding Simon who wrote the code.
> >
> > Chandan Rajendra writes:
> >> When executing fstests' generic/026 test, I hit the following call trace,
> >>
> >> [ 417.061038] BUG: Unable to handle kern
On Wed, Jan 23, 2019 at 05:24:13PM +0100, Cédric Le Goater wrote:
> On 1/22/19 5:56 AM, Paul Mackerras wrote:
> > On Mon, Jan 07, 2019 at 07:43:15PM +0100, Cédric Le Goater wrote:
> >> We will have different KVM devices for interrupts, one for the
> >> XICS-over-XIVE mode and one for the XIVE nativ
On 1/17/19 1:39 PM, Alexandre Ghiti wrote:
From: Alexandre Ghiti
On systems without CMA or (MEMORY_ISOLATION && COMPACTION) activated but
that support gigantic pages, boottime reserved gigantic pages can not be
freed at all. This patchs simply enables the possibility to hand back
those pages to
OK, next step: b50f42f0fe12965ead395c76bcb6a14f00cdf65b (powerpc/dma:
use the dma_direct mapping routines)
git clone git://git.infradead.org/users/hch/misc.git -b powerpc-dma.6 a
git checkout b50f42f0fe12965ead395c76bcb6a14f00cdf65b
Results: The X1000 and X5000 boot but unfortunately the P.A.
(dropped most of 'CC)
On Sun, Feb 03, 2019 at 08:39:20PM +1100, Michael Ellerman wrote:
> Mike Rapoport writes:
>
> > Currently, memblock has several internal functions with overlapping
> > functionality. They all call memblock_find_in_range_node() to find free
> > memory and then reserve the al
On Sun, Feb 03, 2019 at 08:39:20PM +1100, Michael Ellerman wrote:
> Mike Rapoport writes:
>
> > Currently, memblock has several internal functions with overlapping
> > functionality. They all call memblock_find_in_range_node() to find free
> > memory and then reserve the allocated range and mark
Mike Rapoport writes:
> Currently, memblock has several internal functions with overlapping
> functionality. They all call memblock_find_in_range_node() to find free
> memory and then reserve the allocated range and mark it with kmemleak.
> However, there is difference in the allocation constrain
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