This adds test cases for the addc[.] instruction.

Signed-off-by: Sandipan Das <sandi...@linux.ibm.com>
---
 arch/powerpc/include/asm/ppc-opcode.h |   1 +
 arch/powerpc/lib/sstep_tests.c        | 212 ++++++++++++++++++++++++++
 2 files changed, 213 insertions(+)

diff --git a/arch/powerpc/include/asm/ppc-opcode.h 
b/arch/powerpc/include/asm/ppc-opcode.h
index 07bdb404571c..c0fe90173977 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -326,6 +326,7 @@
 #define PPC_INST_ADDI                  0x38000000
 #define PPC_INST_ADDIS                 0x3c000000
 #define PPC_INST_ADD                   0x7c000214
+#define PPC_INST_ADDC                  0x7c000014
 #define PPC_INST_SUB                   0x7c000050
 #define PPC_INST_BLR                   0x4e800020
 #define PPC_INST_BLRL                  0x4e800021
diff --git a/arch/powerpc/lib/sstep_tests.c b/arch/powerpc/lib/sstep_tests.c
index fe6201a2add7..d2f4bb66f66f 100644
--- a/arch/powerpc/lib/sstep_tests.c
+++ b/arch/powerpc/lib/sstep_tests.c
@@ -243,6 +243,218 @@ static struct sstep_test tests[] = {
                        }
                }
        },
+       {
+               .mnemonic = "addc",
+               .subtests =
+               {
+                       {
+                               .descr = "RA = LONG_MIN, RB = LONG_MIN",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22),
+                               .regs =
+                               {
+                                       .gpr[21] = LONG_MIN,
+                                       .gpr[22] = LONG_MIN,
+                               }
+                       },
+                       {
+                               .descr = "RA = LONG_MIN, RB = LONG_MAX",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22),
+                               .regs =
+                               {
+                                       .gpr[21] = LONG_MIN,
+                                       .gpr[22] = LONG_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = LONG_MAX, RB = LONG_MAX",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22),
+                               .regs =
+                               {
+                                       .gpr[21] = LONG_MAX,
+                                       .gpr[22] = LONG_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = ULONG_MAX, RB = ULONG_MAX",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22),
+                               .regs =
+                               {
+                                       .gpr[21] = ULONG_MAX,
+                                       .gpr[22] = ULONG_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = ULONG_MAX, RB = 0x1",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22),
+                               .regs =
+                               {
+                                       .gpr[21] = ULONG_MAX,
+                                       .gpr[22] = 0x1,
+                               }
+                       },
+                       {
+                               .descr = "RA = INT_MIN, RB = INT_MIN",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22),
+                               .regs =
+                               {
+                                       .gpr[21] = INT_MIN,
+                                       .gpr[22] = INT_MIN,
+                               }
+                       },
+                       {
+                               .descr = "RA = INT_MIN, RB = INT_MAX",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22),
+                               .regs =
+                               {
+                                       .gpr[21] = INT_MIN,
+                                       .gpr[22] = INT_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = INT_MAX, RB = INT_MAX",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22),
+                               .regs =
+                               {
+                                       .gpr[21] = INT_MAX,
+                                       .gpr[22] = INT_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = UINT_MAX, RB = UINT_MAX",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22),
+                               .regs =
+                               {
+                                       .gpr[21] = UINT_MAX,
+                                       .gpr[22] = UINT_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = UINT_MAX, RB = 0x1",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22),
+                               .regs =
+                               {
+                                       .gpr[21] = UINT_MAX,
+                                       .gpr[22] = 0x1,
+                               }
+                       },
+                       {
+                               .descr = "RA = LONG_MIN | INT_MIN, RB = 
LONG_MIN | INT_MIN",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22),
+                               .regs =
+                               {
+                                       .gpr[21] = LONG_MIN | (uint) INT_MIN,
+                                       .gpr[22] = LONG_MIN | (uint) INT_MIN,
+                               }
+                       }
+               }
+       },
+       {
+               .mnemonic = "addc.",
+               .subtests =
+               {
+                       {
+                               .descr = "RA = LONG_MIN, RB = LONG_MIN",
+                               .flags = IGNORE_CCR,
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22) | __PPC_RC31,
+                               .regs =
+                               {
+                                       .gpr[21] = LONG_MIN,
+                                       .gpr[22] = LONG_MIN,
+                               }
+                       },
+                       {
+                               .descr = "RA = LONG_MIN, RB = LONG_MAX",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22) | __PPC_RC31,
+                               .regs =
+                               {
+                                       .gpr[21] = LONG_MIN,
+                                       .gpr[22] = LONG_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = LONG_MAX, RB = LONG_MAX",
+                               .flags = IGNORE_CCR,
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22) | __PPC_RC31,
+                               .regs =
+                               {
+                                       .gpr[21] = LONG_MAX,
+                                       .gpr[22] = LONG_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = ULONG_MAX, RB = ULONG_MAX",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22) | __PPC_RC31,
+                               .regs =
+                               {
+                                       .gpr[21] = ULONG_MAX,
+                                       .gpr[22] = ULONG_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = ULONG_MAX, RB = 0x1",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22) | __PPC_RC31,
+                               .regs =
+                               {
+                                       .gpr[21] = ULONG_MAX,
+                                       .gpr[22] = 0x1,
+                               }
+                       },
+                       {
+                               .descr = "RA = INT_MIN, RB = INT_MIN",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22) | __PPC_RC31,
+                               .regs =
+                               {
+                                       .gpr[21] = INT_MIN,
+                                       .gpr[22] = INT_MIN,
+                               }
+                       },
+                       {
+                               .descr = "RA = INT_MIN, RB = INT_MAX",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22) | __PPC_RC31,
+                               .regs =
+                               {
+                                       .gpr[21] = INT_MIN,
+                                       .gpr[22] = INT_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = INT_MAX, RB = INT_MAX",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22) | __PPC_RC31,
+                               .regs =
+                               {
+                                       .gpr[21] = INT_MAX,
+                                       .gpr[22] = INT_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = UINT_MAX, RB = UINT_MAX",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22) | __PPC_RC31,
+                               .regs =
+                               {
+                                       .gpr[21] = UINT_MAX,
+                                       .gpr[22] = UINT_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = UINT_MAX, RB = 0x1",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22) | __PPC_RC31,
+                               .regs =
+                               {
+                                       .gpr[21] = UINT_MAX,
+                                       .gpr[22] = 0x1,
+                               }
+                       },
+                       {
+                               .descr = "RA = LONG_MIN | INT_MIN, RB = 
LONG_MIN | INT_MIN",
+                               .instr = PPC_INST_ADDC | ___PPC_RT(20) | 
___PPC_RA(21) | ___PPC_RB(22) | __PPC_RC31,
+                               .regs =
+                               {
+                                       .gpr[21] = LONG_MIN | (uint) INT_MIN,
+                                       .gpr[22] = LONG_MIN | (uint) INT_MIN,
+                               }
+                       }
+               }
+       },
 };
 
 int emulate_instr(struct pt_regs *regs, unsigned int instr)
-- 
2.19.2

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