On Tue, Dec 4, 2018 at 10:28 PM Christophe LEROY
wrote:
>
>
>
> Le 04/12/2018 à 21:53, Mathieu Malaterre a écrit :
> > The code:
> >
> >ifdef CONFIG_6xx
> >KBUILD_CFLAGS += -mcpu=powerpc
> >endif
> >
> > was added in 2006 in commit f48b8296b315 ("[PATCH] powerpc32: Set cpu
> >
On 05/12/2018 16:47, Alexey Kardashevskiy wrote:
>
>
> On 05/12/2018 16:14, David Gibson wrote:
>> On Fri, Nov 23, 2018 at 04:52:49PM +1100, Alexey Kardashevskiy wrote:
>>> The powernv PCI code stores NPU data in the pnv_phb struct. The latter
>>> is referenced by pci_controller::private_data.
Hi Florian,
Florian Fainelli writes:
> +PPC folks
>
> On 11/23/18 10:20 AM, Guenter Roeck wrote:
>> On Mon, Nov 19, 2018 at 12:50:50PM -0800, Guenter Roeck wrote:
>>> On Mon, Nov 19, 2018 at 10:44:30AM -0800, Florian Fainelli wrote:
On 11/15/18 5:16 PM, Guenter Roeck wrote:
> On Thu, Nov
On 05/12/2018 16:14, David Gibson wrote:
> On Fri, Nov 23, 2018 at 04:52:49PM +1100, Alexey Kardashevskiy wrote:
>> The powernv PCI code stores NPU data in the pnv_phb struct. The latter
>> is referenced by pci_controller::private_data. We are going to have NPU2
>> support in the pseries platfor
On Fri, Nov 23, 2018 at 04:52:49PM +1100, Alexey Kardashevskiy wrote:
> The powernv PCI code stores NPU data in the pnv_phb struct. The latter
> is referenced by pci_controller::private_data. We are going to have NPU2
> support in the pseries platform as well but it does not store any
> private_dat
Le 05/12/2018 à 05:06, Aneesh Kumar K.V a écrit :
On 12/5/18 9:32 AM, Christophe LEROY wrote:
Le 05/12/2018 à 04:09, Aneesh Kumar K.V a écrit :
Architectures like ppc64 requires to do a conditional tlb flush based
on the old
and new value of pte. Enable that by passing old pte value as th
On Mon, Nov 5, 2018 at 7:52 AM Sabyasachi Gupta
wrote:
>
> Replaced dma_alloc_coherent + memset with dma_zalloc_coherent
>
> Signed-off-by: Sabyasachi Gupta
Any comment on this patch?
> ---
> arch/powerpc/sysdev/fsl_rmu.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --gi
checkpatch.pl reports the following:
WARNING: struct kgdb_arch should normally be const
#28: FILE: arch/mips/kernel/kgdb.c:397:
+struct kgdb_arch arch_kgdb_ops = {
This report makes sense, as all other ops struct, this
one should also be const. This patch does the change.
Signed-off-by: Ch
MIPS is the only architecture modifying arch_kgdb_ops during init.
This patch makes the init static, so that it can be changed to
const in following patch, as recommended by checkpatch.pl
Suggested-by: Paul Burton
Signed-off-by: Christophe Leroy
---
arch/mips/kernel/kgdb.c | 16 +++-
On Fri, Nov 23, 2018 at 04:52:46PM +1100, Alexey Kardashevskiy wrote:
> The skiboot firmware has a hot reset handler which fences the NVIDIA V100
> GPU RAM on Witherspoons and makes accesses no-op instead of throwing HMIs:
> https://github.com/open-power/skiboot/commit/fca2b2b839a67
>
> Now we are
On Fri, Nov 23, 2018 at 04:52:48PM +1100, Alexey Kardashevskiy wrote:
> This new memory does not have page structs as it is not plugged to
> the host so gup() will fail anyway.
>
> This adds 2 helpers:
> - mm_iommu_newdev() to preregister the "memory device" memory so
> the rest of API can still b
On Fri, Nov 23, 2018 at 04:52:47PM +1100, Alexey Kardashevskiy wrote:
> Normally mm_iommu_get() is supposed to add a reference and
> mm_iommu_put() to remove it. However historically mm_iommu_find() does
> the referencing and mm_iommu_get() is doing allocation and referencing.
>
> We are going to
On Tue, Dec 4, 2018 at 7:01 PM Kevin Hilman wrote:
>
> Rob Herring writes:
>
> > It is best practice to have 1 binding per file, so board level bindings
> > should be separate for various misc SoC bindings.
> >
> > Cc: Mark Rutland
> > Cc: Carlo Caione
> > Cc: Kevin Hilman
> > Cc: devicet...@v
NestMMU requires us to mark the pte invalid and flush the tlb when we do a
RW upgrade of pte. We fixed a variant of this in the fault path in commit
Fixes: bd5050e38aec ("powerpc/mm/radix: Change pte relax sequence to handle
nest MMU hang")
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/inclu
Christophe LEROY writes:
> diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
>> index 8cf035e68378..39d33a3d0dc6 100644
>> --- a/arch/powerpc/mm/hugetlbpage.c
>> +++ b/arch/powerpc/mm/hugetlbpage.c
>> @@ -912,3 +912,32 @@ int gup_hugepte(pte_t *ptep, unsigned long sz, unsi
On 12/5/18 9:32 AM, Christophe LEROY wrote:
Le 05/12/2018 à 04:09, Aneesh Kumar K.V a écrit :
Architectures like ppc64 requires to do a conditional tlb flush based
on the old
and new value of pte. Enable that by passing old pte value as the arg.
Signed-off-by: Aneesh Kumar K.V
---
arch/s3
Le 05/12/2018 à 04:09, Aneesh Kumar K.V a écrit :
Architectures like ppc64 requires to do a conditional tlb flush based on the old
and new value of pte. Enable that by passing old pte value as the arg.
Signed-off-by: Aneesh Kumar K.V
---
arch/s390/include/asm/pgtable.h | 3 ++-
arch/s390/
Le 05/12/2018 à 04:09, Aneesh Kumar K.V a écrit :
NestMMU requires us to mark the pte invalid and flush the tlb when we do a
RW upgrade of pte. We fixed a variant of this in the fault path in commit
Fixes: bd5050e38aec ("powerpc/mm/radix: Change pte relax sequence to handle nest MMU
hang")
S
Hi,
On Mon, Dec 3, 2018 at 7:57 AM Daniel Thompson
wrote:
>
> On Tue, Nov 27, 2018 at 09:38:37AM -0800, Douglas Anderson wrote:
> > When I had lockdep turned on and dropped into kgdb I got a nice splat
> > on my system. Specifically it hit:
> > DEBUG_LOCKS_WARN_ON(current->hardirq_context)
> >
When I had lockdep turned on and dropped into kgdb I got a nice splat
on my system. Specifically it hit:
DEBUG_LOCKS_WARN_ON(current->hardirq_context)
Specifically it looked like this:
sysrq: SysRq : DEBUG
[ cut here ]
DEBUG_LOCKS_WARN_ON(current->hardirq_context)
The function kgdb_roundup_cpus() was passed a parameter that was
documented as:
> the flags that will be used when restoring the interrupts. There is
> local_irq_save() call before kgdb_roundup_cpus().
Nobody used those flags. Anyone who wanted to temporarily turn on
interrupts just did local_ir
This series was originally part of the series ("serial: Finish kgdb on
qcom_geni; fix many lockdep splats w/ kgdb") but it made sense to
split it up.
It's believed that dropping into kgdb should be more robust once these
patches are applied.
Repost of v6 adds CC's and also tags already received.
Christophe LEROY writes:
> Le 16/11/2018 à 11:20, Michael Ellerman a écrit :
>> Christophe LEROY writes:
>>
>>> Le 15/11/2018 à 12:46, Michael Ellerman a écrit :
Christophe Leroy writes:
> This patch adds a debugfs file to dump block address translation:
>
> ~# cat /sys/k
Hi Dan,
Thanks for the patch.
Dan Carpenter writes:
> The ipic_info[] array only has 95 elements so I have made the bounds
> check smaller to prevent a read overflow. It was Smatch that found
> this issue:
>
> arch/powerpc/sysdev/ipic.c:784 ipic_set_priority()
> error: buffer overflow '
NestMMU requires us to mark the pte invalid and flush the tlb when we do a
RW upgrade of pte. We fixed a variant of this in the fault path in commit
Fixes: bd5050e38aec ("powerpc/mm/radix: Change pte relax sequence to handle
nest MMU hang")
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/inclu
Architectures like ppc64 requires to do a conditional tlb flush based on the old
and new value of pte. Follow the regular pte change protection sequence for
hugetlb too. This allow the architectures to override the update sequence.
Signed-off-by: Aneesh Kumar K.V
---
include/linux/hugetlb.h | 20
NestMMU requires us to mark the pte invalid and flush the tlb when we do a
RW upgrade of pte. We fixed a variant of this in the fault path in commit
Fixes: bd5050e38aec ("powerpc/mm/radix: Change pte relax sequence to handle
nest MMU hang")
Do the same for mprotect upgrades.
Hugetlb is handled i
Architectures like ppc64 requires to do a conditional tlb flush based on the old
and new value of pte. Enable that by passing old pte value as the arg.
Signed-off-by: Aneesh Kumar K.V
---
arch/s390/include/asm/pgtable.h | 3 ++-
arch/s390/mm/pgtable.c | 2 +-
arch/x86/include/asm/paravi
Some architecture may want to call flush_tlb_range from these helpers.
Signed-off-by: Aneesh Kumar K.V
---
arch/s390/include/asm/pgtable.h | 4 ++--
arch/s390/mm/pgtable.c | 6 --
arch/x86/include/asm/paravirt.h | 7 +--
fs/proc/task_mmu.c | 4 ++--
include/asm-gene
We can upgrade pte access (R -> RW transition) via mprotect. We need
to make sure we follow the recommended pte update sequence as outlined in
commit bd5050e38aec ("powerpc/mm/radix: Change pte relax sequence to handle
nest MMU hang")
for such updates. This patch series do that.
Changes from V2
Rob Herring writes:
> It is best practice to have 1 binding per file, so board level bindings
> should be separate for various misc SoC bindings.
>
> Cc: Mark Rutland
> Cc: Carlo Caione
> Cc: Kevin Hilman
> Cc: devicet...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-a
Hello James,
Thanks for you interest in these patches.
James Morris writes:
> On Fri, 16 Nov 2018, Thiago Jung Bauermann wrote:
>
>> On the OpenPOWER platform, secure boot and trusted boot are being
>> implemented using IMA for taking measurements and verifying signatures.
>> Since the kernel
Commit-ID: 04229110adfba984950fc0209632640a76eb1de4
Gitweb: https://git.kernel.org/tip/04229110adfba984950fc0209632640a76eb1de4
Author: Paul E. McKenney
AuthorDate: Mon, 5 Nov 2018 16:53:13 -0800
Committer: Paul E. McKenney
CommitDate: Thu, 8 Nov 2018 21:43:20 -0800
powerpc: Convert hu
On Tue, Dec 4, 2018 at 2:12 AM wrote:
>
> On 03/12/2018 at 22:32, Rob Herring wrote:
> > Convert Atmel SoC bindings to DT schema format using json-schema.
> >
> > Cc: Mark Rutland
> > Cc: Nicolas Ferre
>
> I'm listed here...
>
> > Cc: Alexandre Belloni
>
> Proper email address here...
>
>
> > C
On Fri, 16 Nov 2018, Thiago Jung Bauermann wrote:
> On the OpenPOWER platform, secure boot and trusted boot are being
> implemented using IMA for taking measurements and verifying signatures.
> Since the kernel image on Power servers is an ELF binary, kernels are
> signed using the scripts/sign-fi
On Mon, 2018-11-26 at 17:56 +0530, Anshuman Khandual wrote:
> At present there are multiple places where invalid node number is encoded
> as -1. Even though implicitly understood it is always better to have macros
> in there. Replace these open encodings for an invalid node number with the
> global
On Tue, Dec 4, 2018 at 10:17 PM Arnd Bergmann wrote:
>
> > diff --git a/arch/powerpc/kernel/systbl.S b/arch/powerpc/kernel/systbl.S
> > index 9ff1913..d756348 100644
> > --- a/arch/powerpc/kernel/systbl.S
> > +++ b/arch/powerpc/kernel/systbl.S
>
> > #ifdef CONFIG_PPC64
> > @@ -47,5 +25,17 @@
> >
PowerPC uses a syscall table with native and compat calls interleaved,
which is a slightly simpler way to define two matching tables.
As we move to having the tables generated, that advantage is no longer
important, but the interleaved table gets in the way of using the
same scripts as on the othe
Le 04/12/2018 à 21:53, Mathieu Malaterre a écrit :
The code:
ifdef CONFIG_6xx
KBUILD_CFLAGS += -mcpu=powerpc
endif
was added in 2006 in commit f48b8296b315 ("[PATCH] powerpc32: Set cpu
explicitly in kernel compiles"). This change was acceptable since the
TARGET_CPU logic wa
> diff --git a/arch/powerpc/kernel/systbl.S b/arch/powerpc/kernel/systbl.S
> index 9ff1913..d756348 100644
> --- a/arch/powerpc/kernel/systbl.S
> +++ b/arch/powerpc/kernel/systbl.S
> #ifdef CONFIG_PPC64
> @@ -47,5 +25,17 @@
> .globl sys_call_table
> sys_call_table:
>
> +#if defined CONFIG_PPC64
The code:
ifdef CONFIG_6xx
KBUILD_CFLAGS += -mcpu=powerpc
endif
was added in 2006 in commit f48b8296b315 ("[PATCH] powerpc32: Set cpu
explicitly in kernel compiles"). This change was acceptable since the
TARGET_CPU logic was 64-bit only.
Since commit 0e00a8c9fd92 ("powerpc: Allow
On Mon, Dec 03, 2018 at 03:32:15PM -0600, Rob Herring wrote:
> Convert Renesas SoC bindings to DT schema format using json-schema.
>
> Cc: Simon Horman
> Cc: Magnus Damm
> Cc: Mark Rutland
> Cc: linux-renesas-...@vger.kernel.org
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Rob Herring
> -
On Mon, Dec 03, 2018 at 03:32:14PM -0600, Rob Herring wrote:
> In preparation to convert board-level bindings to json-schema, move
> various misc SoC bindings out to their own file.
>
> Cc: Mark Rutland
> Cc: Simon Horman
> Cc: Magnus Damm
> Cc: devicet...@vger.kernel.org
> Cc: linux-renesas-..
commit f21f49ea639a ("[POWERPC] Remove the dregs of APUS support from
arch/powerpc") removed CONFIG_APUS, but forgot to remove the logic
which adapts tophys() and tovirt() for it.
This patch removes the last stale pieces.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/ppc_asm.h |
Hi Mikey,
On 11/29/18 12:11 AM, Michael Neuling wrote:
> On Wed, 2018-11-28 at 11:23 -0200, Breno Leitao wrote:
>> A new self test that forces MSR[TS] to be set without calling any TM
>> instruction. This test also tries to cause a page fault at a signal
>> handler, exactly between MSR[TS] set and
On Tue, Dec 04, 2018 at 11:24:28AM +1030, Joel Stanley wrote:
> Alan Modra explains:
>
> > Likely you could discard .interp > and .dynstr too, and .dynsym when
> > !CONFIG_PPC32.
>
> Discarding of interp and dynstr happened in a previous patch. The dynsym
> cleanup was a bit less straightforwa
On Tue, Dec 04, 2018 at 08:59:41PM +1100, Michael Ellerman wrote:
> Hi Mike,
>
> Thanks for trying to clean these up.
>
> I think a few could be improved though ...
>
> Mike Rapoport writes:
> > diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
> > index 913bfca..fa884ad 1006
On Tue, Dec 4, 2018 at 8:57 AM Geert Uytterhoeven wrote:
>
> Hi Simon,
>
> On Tue, Dec 4, 2018 at 3:48 PM Simon Horman wrote:
> > On Mon, Dec 03, 2018 at 03:32:15PM -0600, Rob Herring wrote:
> > > Convert Renesas SoC bindings to DT schema format using json-schema.
> > >
> > > Cc: Simon Horman
>
On Tue, Dec 4, 2018 at 8:16 AM Heiko Stuebner wrote:
>
> Am Montag, 3. Dezember 2018, 22:32:13 CET schrieb Rob Herring:
> > Convert Rockchip SoC bindings to DT schema format using json-schema.
> >
> > Cc: Mark Rutland
> > Cc: Heiko Stuebner
> > Cc: devicet...@vger.kernel.org
> > Cc: linux-arm-ke
Hi Simon,
On Tue, Dec 4, 2018 at 3:48 PM Simon Horman wrote:
> On Mon, Dec 03, 2018 at 03:32:15PM -0600, Rob Herring wrote:
> > Convert Renesas SoC bindings to DT schema format using json-schema.
> >
> > Cc: Simon Horman
> > Cc: Magnus Damm
> > Cc: Mark Rutland
> > Cc: linux-renesas-...@vger.k
On Mon, Dec 3, 2018 at 10:35 PM Rob Herring wrote:
> In preparation to convert board-level bindings to json-schema, move
> various misc SoC bindings out to their own file.
>
> Cc: Mark Rutland
> Cc: Simon Horman
> Cc: Magnus Damm
> Cc: devicet...@vger.kernel.org
> Cc: linux-renesas-...@vger.ker
On Tue, Dec 4, 2018 at 2:39 AM Neil Armstrong wrote:
>
> Hi Rob,
>
> You forgot linux-amlogic in CC...
>
> On 03/12/2018 22:32, Rob Herring wrote:
> > Convert Amlogic SoC bindings to DT schema format using json-schema.
> >
> > Cc: Carlo Caione
> > Cc: Kevin Hilman
> > Cc: Mark Rutland
> > Cc: d
Am Montag, 3. Dezember 2018, 22:32:13 CET schrieb Rob Herring:
> Convert Rockchip SoC bindings to DT schema format using json-schema.
>
> Cc: Mark Rutland
> Cc: Heiko Stuebner
> Cc: devicet...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-rockc...@lists.infradead.org
> S
On Tue, Dec 04, 2018 at 10:53:39AM +0100, Christian Zigotzky wrote:
> I don't know why this kernel doesn't recognize the hard disks connected to
> my physical P5020 board and why the onboard ethernet on my PASEMI board
> doesn't work. (dma_direct_map_page: overflow)
Do you know if this actually
On Tue, Dec 4, 2018 at 2:43 AM Neil Armstrong wrote:
>
> On 03/12/2018 22:32, Rob Herring wrote:
> > Convert Oxford Semi SoC bindings to DT schema format using json-schema.
> >
> > Cc: Mark Rutland
> > Cc: Neil Armstrong
> > Cc: devicet...@vger.kernel.org
> > Cc: linux-arm-ker...@lists.infradead
"Aneesh Kumar K.V" writes:
> On 11/29/18 3:40 AM, Andrew Morton wrote:
>> On Wed, 28 Nov 2018 20:04:37 +0530 "Aneesh Kumar K.V"
>> wrote:
>>
>>> Signed-off-by: Aneesh Kumar K.V
>>
>> Some explanation of the motivation would be useful.
>
> I will update the commit message.
>
Is this good?
* Ram Pai:
> +void arch_dup_pkeys(struct mm_struct *oldmm, struct mm_struct *mm)
> +{
> + /* Duplicate the oldmm pkey state in mm: */
> + mm_pkey_allocation_map(mm) = mm_pkey_allocation_map(oldmm);
> + mm->context.execute_only_pkey = oldmm->context.execute_only_pkey;
> +}
Looks reason
Hi Rob,
On Mon, Dec 03, 2018 at 03:32:00PM -0600, Rob Herring wrote:
> diff --git a/Documentation/devicetree/bindings/arm/al,alpine.yaml
> b/Documentation/devicetree/bindings/arm/al,alpine.yaml
> new file mode 100644
> index ..82e2fafdfece
> --- /dev/null
> +++ b/Documentation/devicet
On Tue, 2018-12-04 at 12:19 +0100, Mathieu Malaterre wrote:
> On Tue, Dec 4, 2018 at 12:09 PM Benjamin Herrenschmidt
> wrote:
> > Hi folks !
> >
> > Does anybody still has the manual or schematics (or both!) of the old
> > "ebony" ppc440gp eval board around by any chance ?
>
> A google search fo
On Tue, Dec 4, 2018 at 12:09 PM Benjamin Herrenschmidt
wrote:
>
> Hi folks !
>
> Does anybody still has the manual or schematics (or both!) of the old
> "ebony" ppc440gp eval board around by any chance ?
A google search for:
IBM/AMCC "PPC440GP" Evaluation Board datasheet
leads to:
https://4don
Hi folks !
Does anybody still has the manual or schematics (or both!) of the old
"ebony" ppc440gp eval board around by any chance ?
Cheers
Ben.
4.19-stable review patch. If anyone has any objections, please let me know.
--
From: Steven Rostedt (VMware)
commit fe60522ec60082a1dd735691b82c64f65d4ad15e upstream.
The function_graph_enter() function does the work of calling the function
graph hook function and the manageme
Hi Mike,
Thanks for trying to clean these up.
I think a few could be improved though ...
Mike Rapoport writes:
> diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
> index 913bfca..fa884ad 100644
> --- a/arch/powerpc/kernel/paca.c
> +++ b/arch/powerpc/kernel/paca.c
> @@ -42,17
On 04 December 2018 at 08:31AM, Christian Zigotzky wrote:
Hi All,
Could you please test Christoph's kernel on your PASEMI and NXP
boards? Download:
'git clone git://git.infradead.org/users/hch/misc.git -b powerpc-dma.5 a'
Thanks,
Christian
I successfully tested this kernel on a virtual e55
On 04.12.18 10:44, Michal Suchánek wrote:
> On Fri, 30 Nov 2018 18:59:21 +0100
> David Hildenbrand wrote:
>
>> Let's introduce new types for different kinds of memory blocks and use
>> them in existing code. As I don't see an easy way to split this up,
>> do it in one hunk for now.
>>
>> acpi:
>>
On Fri, 30 Nov 2018 18:59:21 +0100
David Hildenbrand wrote:
> Let's introduce new types for different kinds of memory blocks and use
> them in existing code. As I don't see an easy way to split this up,
> do it in one hunk for now.
>
> acpi:
> Use DIMM or DIMM_UNREMOVABLE depending on hotremove
Christophe LEROY writes:
> Le 16/11/2018 à 11:20, Michael Ellerman a écrit :
>> Christophe LEROY writes:
>>
>>> Le 15/11/2018 à 12:46, Michael Ellerman a écrit :
Christophe Leroy writes:
> This patch adds a debugfs file to dump block address translation:
>
> ~# cat /sys/k
On Mon, Dec 03, 2018 at 03:32:19PM -0600, Rob Herring wrote:
> Convert Tegra SoC bindings to DT schema format using json-schema.
>
> Cc: Mark Rutland
> Cc: Thierry Reding
> Cc: Jonathan Hunter
> Cc: devicet...@vger.kernel.org
> Cc: linux-te...@vger.kernel.org
> Signed-off-by: Rob Herring
> ---
On 03/12/2018 22:32, Rob Herring wrote:
> Convert Oxford Semi SoC bindings to DT schema format using json-schema.
>
> Cc: Mark Rutland
> Cc: Neil Armstrong
> Cc: devicet...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-ox...@groups.io
> Signed-off-by: Rob Herring
> ---
Christophe Leroy writes:
> In the powerpc, there are several places implementing safe
^
code ?
> access to user data. This is sometimes implemented using
> probe_kernel_address() with additional access_ok() verification,
> sometimes with get_user() enclosed in a p
Hi Rob,
You forgot linux-amlogic in CC...
On 03/12/2018 22:32, Rob Herring wrote:
> Convert Amlogic SoC bindings to DT schema format using json-schema.
>
> Cc: Carlo Caione
> Cc: Kevin Hilman
> Cc: Mark Rutland
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Rob Herring
> ---
> .../device
Hi Rob
On 12/3/18 10:32 PM, Rob Herring wrote:
> Convert ST STi SoC bindings to DT schema format using json-schema.
>
> Cc: Patrice Chotard
> Cc: Mark Rutland
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Rob Herring
> ---
> Documentation/devicetree/bindings/arm/sti.txt | 23 -
On 03/12/2018 22:32, Rob Herring wrote:
> It is best practice to have 1 binding per file, so board level bindings
> should be separate for various misc SoC bindings.
>
> Cc: Mark Rutland
> Cc: Carlo Caione
> Cc: Kevin Hilman
> Cc: devicet...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradea
On 03/12/2018 at 22:32, Rob Herring wrote:
> Convert Atmel SoC bindings to DT schema format using json-schema.
>
> Cc: Mark Rutland
> Cc: Nicolas Ferre
I'm listed here...
> Cc: Alexandre Belloni
Proper email address here...
> Cc: devicet...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infr
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