On Tue, 2018-05-29 at 22:57 +1000, Michael Ellerman wrote:
> From: Al Viro
>
> In PPC_PTRACE_GETHWDBGINFO and PPC_PTRACE_SETHWDEBUG we do an
> access_ok() check and then __copy_{from,to}_user().
>
> Instead we should just use copy_{from,to}_user() which does all that
> for us and is less error p
Hi,
Any progress/update with this patch ?
Please do let know, if something more is needed here.
Regards,
Vipin
On Wednesday 14 March 2018 01:22 PM, Vipin K Parashar wrote:
printk() in unmap_cpu_from_node() uses KERN_ERR message severity,
for a WARNING message. Change it to pr_warn().
Sig
On Wed, May 23, 2018 at 03:01:47PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> It is a simple patch just for moving kvmppc_save_tm/kvmppc_restore_tm()
> functionalities to tm.S. There is no logic change. The reconstruct of
> those APIs will be done in later patches to improve read
On Tue, 29 May 2018 19:58:41 +0530
"Aneesh Kumar K.V" wrote:
> When relaxing access (read -> read_write update), pte needs to be marked
> invalid
> to handle a nest MMU bug. We also need to do a tlb flush after the pte is
> marked invalid before updating the pte with new access bits.
>
> We als
On Tue, 2018-05-29 at 07:03 -0700, Christoph Hellwig wrote:
> On Tue, May 29, 2018 at 09:56:24AM +1000, Benjamin Herrenschmidt wrote:
> > I don't think forcing the addition of an emulated iommu in the middle
> > just to work around the fact that virtio "cheats" and doesn't use the
> > dma API unles
On Mon, May 28, 2018 at 12:49 PM, Christophe Leroy
wrote:
> At the time being, memcmp() compares two chunks of memory
> byte per byte.
>
> This patch optimises the comparison by comparing word by word.
>
> A small benchmark performed on an 8xx comparing two chuncks
> of 512 bytes performed 10
In commit eae5f709a4d7 ("powerpc: Add __printf verification to
prom_printf") __printf attribute was added to prom_printf(), which
means GCC started warning about type/format mismatches. As part of that
commit we changed some "%lx" formats to "%llx" where the type is
actually unsigned long long.
Un
On Tue, 2018-05-29 at 15:22 +, Diana Madalina Craciun wrote:
> Hi Scott,
>
> Thanks for the review.
>
> On 05/22/2018 11:31 PM, Scott Wood wrote:
> > On Tue, 2018-05-22 at 10:10 +0300, Diana Craciun wrote:
> > > Implement the barrier_nospec as a isync;sync instruction sequence.
> > > The impl
On Wed, May 16, 2018 at 09:16:47AM +0200, Peter Rosin wrote:
> Because it looks neater.
>
> For diolan, this allows factoring out some code that is now common
> between if and else.
>
> For eg20t, pch_i2c_writebytes is always called with a write in
> msgs->flags, and pch_i2c_readbytes with a read
On Wed, May 16, 2018 at 09:16:46AM +0200, Peter Rosin wrote:
> Because it looks neater.
>
> Signed-off-by: Peter Rosin
Applied to for-next, thanks!
signature.asc
Description: PGP signature
On 29/05/2018 18:22, Greg Kroah-Hartman wrote:
> When calling debugfs functions, there is no need to ever check the
> return value. The function can work or not, but the code logic should
> never do something different based on this.
>
> This cleans up the error handling a lot, as this code will
When calling debugfs functions, there is no need to ever check the
return value. The function can work or not, but the code logic should
never do something different based on this.
This cleans up the error handling a lot, as this code will never get
hit.
Cc: Paul Mackerras
Cc: Benjamin Herrensc
If CONFIG_PPC_SPLPAR is not selected, steal_time will always
be NUL, so accounting it is pointless
Signed-off-by: Christophe Leroy
---
New in v3
arch/powerpc/kernel/time.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/ker
scaled cputime is only meaningfull when the processor has
SPURR and/or PURR, which means only on PPC64.
Removing it on PPC32 significantly reduces the size of
vtime_account_system() and vtime_account_idle() on an 8xx:
Before:
0114 l F .text 00a8 vtime_delta
04c0 g F .text 00
arch_vtime_task_switch() is a small function which is called
only from vtime_common_task_switch(), so it is worth inlining
Signed-off-by: Christophe Leroy
---
v3: no change
v2: added a local pointer for get_accounting(prev) to avoid GCC to read it
twice
arch/powerpc/include/asm/cputime.h | 1
On Tue, 2018-05-29 at 15:24 +, Christophe Leroy wrote:
> On 05/29/2018 02:46 PM, Michal Suchánek wrote:
> > On Tue, 29 May 2018 16:13:49 +0200 Christophe LEROY
> > wrote:
[]
> > diff --git a/arch/powerpc/kernel/security.c
> > > > b/arch/powerpc/kernel/security.c index 0239383c7e4d..a0c32d5398
Latest GCC version emit the following warnings
As arch/powerpc code is built with -Werror, this breaks build with
GCC 8.1
This patch inhibits those warnings
CC arch/powerpc/kernel/syscalls.o
In file included from arch/powerpc/kernel/syscalls.c:24:
./include/linux/syscalls.h:233:18: error:
Latest GCC version emit the following warnings
As arch/powerpc code is built with -Werror, this breaks build with
GCC 8.1
This patch inhibits those warnings
CC arch/powerpc/platforms/cell/spu_syscalls.o
In file included from arch/powerpc/platforms/cell/spu_syscalls.c:26:
./include/linux/s
In order to simplify time critical exceptions handling 8xx
specific SW perf counters, this patch moves the counters into
the begining of memory. This is possible because .text is readable
and the counters are never modified outside of the handlers.
By doing this, we avoid having to set a second re
In 16k page size mode, the 8xx need only 4k for a page table.
This patch makes use of the pte_fragment functions in order
to avoid wasting memory space
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/mmu-8xx.h | 4 +++
arch/powerpc/include/asm/nohash/32/pgalloc.h | 44 ++
In order to allow the 8xx to handle pte_fragments, this patch
makes it common to PPC32 and PPC64 by moving the related code
to common files and by defining a new config item called
CONFIG_NEED_PTE_FRAG
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/mmu_context.h | 53 ++
We can now use SPRN_M_TW in the DAR Fixup code, freeing
SPRN_SPRG_SCRATCH2
Then SPRN_SPRG_SCRATCH2 may be used for something else in the future.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/po
Each handler must not exceed 64 instructions to fit into the main
exception area.
Following the significant size reduction of TLB handler routines,
the side handlers can be brought back close to the main part.
In the worst case:
Main part of ITLB handler is 45 insn, side part is 9 insn ==> total 5
Today, on the 8xx the TLB handlers do SW tablewalk by doing all
the calculation in ASM, in order to match with the Linux page
table structure.
The 8xx offers hardware assistance which allows significant size
reduction of the TLB handlers, hence also reduces the time spent
in the handlers.
However
commit 1bc54c03117b9 ("powerpc: rework 4xx PTE access and TLB miss")
introduced non atomic PTE updates and started the work of removing
PTE updates in TLB miss handlers, but kept PTE_ATOMIC_UPDATES for the
8xx with the following comment:
/* Until my rework is finished, 8xx still needs atomic PTE up
On the 8xx, the GUARDED attribute of the pages is managed in the
L1 entry, therefore to avoid having to copy it into L1 entry
at each TLB miss, we set it in the PMD.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/32/pte-8xx.h | 3 ++-
arch/powerpc/kernel/head_8xx.S
On the 8xx, the GUARDED attribute of the pages is managed in the
L1 entry, therefore to avoid having to copy it into L1 entry
at each TLB miss, we have to set it in the PMD
In order to allow this, this patch splits the VM alloc space in two
parts, one for VM alloc and non Guarded IO, and one for G
Use _ALIGN_DOWN macro instead of open coding in define of VMALLOC_BASE
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/32/pgtable.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h
b/arch/powerpc/include/asm
__ioremap(), ioremap(), ioremap_wc() et ioremap_prot() are
very similar between PPC32 and PPC64, they can easily be
made common.
_PAGE_WRITE equals to _PAGE_RW on PPC32
_PAGE_RO and _PAGE_HWWRITE are 0 on PPC64
iounmap() can also be made common by renaming the PPC32
iounmap() as __iounmap() then
Today, early ioremap maps from IOREMAP_BASE down to up on PPC64
and from IOREMAP_TOP up to down on PPC32
This patchs modifies PPC32 behaviour to get same behaviour as PPC64
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 29 ++--
arch/power
This patch is the first of a serie that intends to make
io mappings common to PPC32 and PPC64.
It moves ioremap/unmap fonctions into a new file called ioremap.c with
no other modification to the functions.
For the time being, the PPC32 and PPC64 parts get enclosed into #ifdef.
Following patches wi
This reverts commit 4f94b2c7462d9720b2afa7e8e8d4c19446bb31ce.
That commit was buggy, as it used rlwinm instead of rlwimi.
Instead of fixing that bug, we revert the previous commit in order to
reduce the dependency between L1 entries and L2 entries
Signed-off-by: Christophe Leroy
---
arch/powerp
The purpose of this serie is to implement hardware assistance for TLB table walk
on the 8xx.
First part is to make L1 entries and L2 entries independant.
For that, we need to alter ioremap functions in order to handle GUARD attribute
at the PGD/PMD level.
Last part is to reuse PTE fragment implem
From: Christophe LEROY
> Sent: 29 May 2018 10:37
...
> - strncpy(new_part->header.name, name, 12);
> + memcpy(new_part->header.name, name, strnlen(name,
> sizeof(new_part->header.name)));
> >>>
> >>>
> >>> The comment for nvram_header.lgnth says:
> >>>
> >>> /*
On 05/29/2018 02:46 PM, Michal Suchánek wrote:
On Tue, 29 May 2018 16:13:49 +0200
Christophe LEROY wrote:
Le 28/05/2018 à 15:19, Michal Suchanek a écrit :
We now have barrier_nospec as mitigation so print it in
cpu_show_spectre_v1 when enabled.
Signed-off-by: Michal Suchanek
---
arch/
Hi Scott,
Thanks for the review.
On 05/22/2018 11:31 PM, Scott Wood wrote:
> On Tue, 2018-05-22 at 10:10 +0300, Diana Craciun wrote:
>> Implement the barrier_nospec as a isync;sync instruction sequence.
>> The implementation uses the infrastructure built for BOOK3S 64
>> with the difference that
On Tue, 29 May 2018 16:13:49 +0200
Christophe LEROY wrote:
> Le 28/05/2018 à 15:19, Michal Suchanek a écrit :
> > We now have barrier_nospec as mitigation so print it in
> > cpu_show_spectre_v1 when enabled.
> >
> > Signed-off-by: Michal Suchanek
> > ---
> > arch/powerpc/kernel/security.c | 5
When relaxing access (read -> read_write update), pte needs to be marked invalid
to handle a nest MMU bug. We also need to do a tlb flush after the pte is
marked invalid before updating the pte with new access bits.
We also move tlb flush to platform specific __ptep_set_access_flags. This will
hel
On Tue, May 29, 2018 at 09:56:24AM +1000, Benjamin Herrenschmidt wrote:
> I don't think forcing the addition of an emulated iommu in the middle
> just to work around the fact that virtio "cheats" and doesn't use the
> dma API unless there is one, is the right "fix".
Agreed.
> The right long term
In later patch, we use the vma and psize to do tlb flush. Do the prototype
update in separate patch to make the review easy.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 5 +++--
arch/powerpc/include/asm/book3s/64/pgtable.h | 8 +---
arch/powerpc/inclu
In later patch we will update them which require them to be moved
to pgtable-radix.c. Keeping the function in radix.h results in
compile warning as below.
./arch/powerpc/include/asm/book3s/64/radix.h: In function
‘radix__ptep_set_access_flags’:
./arch/powerpc/include/asm/book3s/64/radix.h:196:28:
In a later patch, we want to update __ptep_set_access_flags take page size
arg. This makes ptep_set_access_flags only work with mmu_virtual_psize.
To simplify the code make huge_ptep_set_access_flags directly call
__ptep_set_access_flags so that we can compute the hugetlb page size in
hugetlb funct
Le 28/05/2018 à 15:19, Michal Suchanek a écrit :
We now have barrier_nospec as mitigation so print it in
cpu_show_spectre_v1 when enabled.
Signed-off-by: Michal Suchanek
---
arch/powerpc/kernel/security.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc
Hi Michal,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.17-rc7 next-20180529]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux
2018-05-16 23:14 GMT+09:00 Nicholas Piggin :
> This eliminates the workaround that requires disabling
> -mprofile-kernel by default in Kconfig.
>
> [ Note: this depends on
> https://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git
> kconfig-shell-v3 ]
>
> Signed-off-by: Nicholas
2018-05-16 23:14 GMT+09:00 Nicholas Piggin :
> Some 64-bit toolchains uses the wrong ISA variant for compiling 32-bit
> kernels, even with -m32. Debian's powerpc64le is one such case, and
> that is because it is built with --with-cpu=power8.
>
> So when cross compiling a 32-bit kernel with a 64-bit
On Mon, 2018-05-21 at 16:50 +1000, Nicholas Piggin wrote:
> Ah, it's POWER8.
>
> I'm betting we have a bug with nohz timer offloading somewhere.
>
> I *think* we may have seen similar on P9 as well, but that may be
> related to problems with stop states.
>
> Can you reproduce it easily? I'm thin
From: Al Viro
In PPC_PTRACE_GETHWDBGINFO and PPC_PTRACE_SETHWDEBUG we do an
access_ok() check and then __copy_{from,to}_user().
Instead we should just use copy_{from,to}_user() which does all that
for us and is less error prone.
Signed-off-by: Al Viro
Signed-off-by: Michael Ellerman
---
arch
Stephen,
On Tue, May 29, 2018 at 2:23 PM, Stephen Rothwell wrote:
> Hi Mathieu,
>
> On Tue, 29 May 2018 13:56:48 +0200 Mathieu Malaterre wrote:
>>
>> On Tue, May 29, 2018 at 1:02 PM, Stephen Rothwell
>> wrote:
>> > Hi all,
>> >
>> > My qemu boots of today's powerpc linux-next kernel produced t
Signed-off-by: Naveen N. Rao
---
arch/powerpc/Kconfig | 1 +
arch/powerpc/include/asm/error-injection.h | 9 +
arch/powerpc/include/asm/ptrace.h | 5 +
3 files changed, 15 insertions(+)
create mode 100644 arch/powerpc/include/asm/error-injection.h
diff
We already have an arch-independent way to set the instruction pointer
with instruction_pointer_set(). Using this allows us to get rid of the
need for override_function_with_return() that each architecture has to
implement.
Furthermore, just_return_func() only has to encode arch-specific
assembly
The first patch simplifies code around function error-injection by
limiting the need for arch-specific helpers. The second patch adds
support for powerpc.
- Naveen
Naveen N. Rao (2):
error-injection: Simplify arch specific helpers
powerpc: Add support for function error injection
arch/pow
Stewart Smith writes:
> Abhishek Goel writes:
>> @@ -215,7 +216,7 @@ static inline void add_powernv_state(int index, const
>> char *name,
>> u64 psscr_val, u64 psscr_mask)
>> {
>> strlcpy(powernv_states[index].name, name, CPUIDLE_NAME_LEN);
>> -strlcp
Hi Mathieu,
On Tue, 29 May 2018 13:56:48 +0200 Mathieu Malaterre wrote:
>
> On Tue, May 29, 2018 at 1:02 PM, Stephen Rothwell
> wrote:
> > Hi all,
> >
> > My qemu boots of today's powerpc linux-next kernel produced the following
> > boot message differences:
> >
> > -Max number of cores passed
Michael,
On Tue, May 29, 2018 at 2:00 PM, Mathieu Malaterre wrote:
> On Tue, May 29, 2018 at 1:56 PM, Mathieu Malaterre wrote:
>> On Tue, May 29, 2018 at 1:02 PM, Stephen Rothwell
>> wrote:
>>> Hi all,
>>>
>>> My qemu boots of today's powerpc linux-next kernel produced the following
>>> boot
On Tue, May 29, 2018 at 1:56 PM, Mathieu Malaterre wrote:
> On Tue, May 29, 2018 at 1:02 PM, Stephen Rothwell
> wrote:
>> Hi all,
>>
>> My qemu boots of today's powerpc linux-next kernel produced the following
>> boot message differences:
>>
>> -Max number of cores passed to firmware: 2048 (NR_C
On Tue, May 29, 2018 at 12:15 PM, Michael Ellerman wrote:
> We recently added the __printf attribute to prom_printf(), which means
> GCC started warning about type/format mismatches. As part of that
> commit we changed some "%lx" formats to "%llx" where the type is
> actually unsigned long long.
>
On Tue, May 29, 2018 at 1:02 PM, Stephen Rothwell wrote:
> Hi all,
>
> My qemu boots of today's powerpc linux-next kernel produced the following
> boot message differences:
>
> -Max number of cores passed to firmware: 2048 (NR_CPUS = 2048)
> +Max number of cores passed to firmware: u (NR_CPUS = 20
Hi all,
My qemu boots of today's powerpc linux-next kernel produced the following
boot message differences:
-Max number of cores passed to firmware: 2048 (NR_CPUS = 2048)
+Max number of cores passed to firmware: u (NR_CPUS = 2048)
Seemingly caused by commit
eae5f709a4d7 ("powerpc: Add __print
Greetings!!!
I am observing kernel oops while running memory hotplug test on P6
machine, on main line kernel.
Machine: Power 6
kernel version 4.17.0-rc6
gcc version 4.8.3 20140911 (Red Hat 4.8.3-7)
Trace:
10:36:09 Unable to handle kernel paging request for data at address
0xc000492746462a
We recently added the __printf attribute to prom_printf(), which means
GCC started warning about type/format mismatches. As part of that
commit we changed some "%lx" formats to "%llx" where the type is
actually unsigned long long.
Unfortunately prom_printf() doesn't know how to print "%llx", it ju
Le 29/05/2018 à 11:05, Geert Uytterhoeven a écrit :
Hi Christophe,
On Tue, May 29, 2018 at 10:56 AM, Christophe LEROY
wrote:
Le 29/05/2018 à 09:47, Geert Uytterhoeven a écrit :
On Tue, May 29, 2018 at 8:03 AM, Christophe Leroy
wrote:
CC arch/powerpc/kernel/nvram_64.o
arch/power
Hi Christophe,
On Tue, May 29, 2018 at 10:56 AM, Christophe LEROY
wrote:
> Le 29/05/2018 à 09:47, Geert Uytterhoeven a écrit :
>> On Tue, May 29, 2018 at 8:03 AM, Christophe Leroy
>> wrote:
>>>
>>>CC arch/powerpc/kernel/nvram_64.o
>>> arch/powerpc/kernel/nvram_64.c: In function 'nvram_c
Le 29/05/2018 à 09:47, Geert Uytterhoeven a écrit :
Hi Christophe,
CC Geoff
On Tue, May 29, 2018 at 8:03 AM, Christophe Leroy
wrote:
CC arch/powerpc/kernel/nvram_64.o
arch/powerpc/kernel/nvram_64.c: In function 'nvram_create_partition':
arch/powerpc/kernel/nvram_64.c:1042:2: error:
Hi Christophe,
CC Geoff
On Tue, May 29, 2018 at 8:03 AM, Christophe Leroy
wrote:
> CC arch/powerpc/kernel/nvram_64.o
> arch/powerpc/kernel/nvram_64.c: In function 'nvram_create_partition':
> arch/powerpc/kernel/nvram_64.c:1042:2: error: 'strncpy' specified bound 12
> equals destination s
On 05/29/2018 06:58 AM, Christophe Leroy wrote:
Latest GCC version emit the following warnings
As arch/powerpc code is built with -Werror, this breaks build with
GCC 8.1
Argh ...
Now, I get the following error with older GCC:
arch/powerpc/kernel/syscalls.c:66:9: error: unknown option afte
Latest GCC version emit the following warnings
As arch/powerpc code is built with -Werror, this breaks build with
GCC 8.1
This patch inhibits those warnings
CC arch/powerpc/platforms/cell/spu_syscalls.o
In file included from arch/powerpc/platforms/cell/spu_syscalls.c:26:
./include/linux/s
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