On 17/04/18 12:09, Alastair D'Silva wrote:
From: Alastair D'Silva
The function removes the process element from NPU cache.
Signed-off-by: Alastair D'Silva
Hmm, personally I'd suggest pnv_ocxl_spa_clear_cache() because it's just
a wrapper around the OPAL call of a similar name.
But I don
On Tue, 2018-04-17 at 14:21 +1000, Andrew Donnellan wrote:
> On 17/04/18 12:09, Alastair D'Silva wrote:
> > From: Alastair D'Silva
> >
> > Switch the use of TIDR on it's CPU feature, rather than assuming it
> > is available based on architecture.
> >
> > Signed-off-by: Alastair D'Silva
>
> The
On Tue, 2018-04-17 at 10:41 +0530, Vaibhav Jain wrote:
> APC virtual machines arent used on POWER-9 chips and are already
> disabled in on-chip CAPP. They also need to be disabled on the PSL
> via
> 'PSL Data Send Control Register' by setting bit(47). This forces the
> PSL to send commands to CAPP
On 17/04/18 15:11, Vaibhav Jain wrote:
APC virtual machines arent used on POWER-9 chips and are already
disabled in on-chip CAPP. They also need to be disabled on the PSL via
'PSL Data Send Control Register' by setting bit(47). This forces the
PSL to send commands to CAPP with queue.id == 0.
Sig
APC virtual machines arent used on POWER-9 chips and are already
disabled in on-chip CAPP. They also need to be disabled on the PSL via
'PSL Data Send Control Register' by setting bit(47). This forces the
PSL to send commands to CAPP with queue.id == 0.
Signed-off-by: Vaibhav Jain
---
drivers/mi
On 17/04/18 12:09, Alastair D'Silva wrote:
From: Alastair D'Silva
Switch the use of TIDR on it's CPU feature, rather than assuming it
is available based on architecture.
Signed-off-by: Alastair D'Silva
There's a use of TIDR in restore_sprs() that's behind the ARCH_300 flag
as well, ideally
On 17/04/18 12:09, Alastair D'Silva wrote:
diff --git a/arch/powerpc/include/asm/switch_to.h
b/arch/powerpc/include/asm/switch_to.h
index be8c9fa23983..5b03d8a82409 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -94,6 +94,5 @@ static inline void c
On 17/04/18 12:09, Alastair D'Silva wrote:
From: Alastair D'Silva
Signed-off-by: Alastair D'Silva
---
Documentation/accelerators/ocxl.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/accelerators/ocxl.rst
b/Documentation/accelerators/ocxl.rst
index ddcc58d0
From: Alastair D'Silva
In order for a userspace AFU driver to call the Power9 specific
OCXL_IOCTL_ENABLE_P9_WAIT, it needs to verify that it can actually
make that call.
Signed-off-by: Alastair D'Silva
---
drivers/misc/ocxl/file.c | 25 +
include/uapi/misc/ocxl.h | 4 +
From: Alastair D'Silva
Signed-off-by: Alastair D'Silva
---
Documentation/accelerators/ocxl.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/accelerators/ocxl.rst
b/Documentation/accelerators/ocxl.rst
index ddcc58d01cfb..144595a80a1c 100644
--- a/Documentation/a
From: Alastair D'Silva
The current implementation of TID allocation, using a global IDR, may
result in an errant process starving the system of available TIDs.
Instead, use task_pid_nr(), as mentioned by the original author. The
scenario described which prevented it's use is not applicable, as
se
From: Alastair D'Silva
Switch the use of TIDR on it's CPU feature, rather than assuming it
is available based on architecture.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/kernel/process.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/process.c
From: Alastair D'Silva
The function removes the process element from NPU cache.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/include/asm/pnv-ocxl.h | 2 +-
arch/powerpc/platforms/powernv/ocxl.c | 4 ++--
drivers/misc/ocxl/link.c | 2 +-
3 files changed, 4 insertions(+), 4 de
From: Alastair D'Silva
In order to successfully issue as_notify, an AFU needs to know the TID
to notify, which in turn means that this information should be
available in userspace so it can be communicated to the AFU.
Signed-off-by: Alastair D'Silva
---
drivers/misc/ocxl/context.c | 5 +
From: Alastair D'Silva
This patch adds a CPU feature bit to show whether the CPU has
the TIDR register available, enabling as_notify/wait in userspace.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/include/asm/cputable.h | 3 ++-
arch/powerpc/include/asm/switch_to.h | 1 -
arch/powerpc/ker
From: Alastair D'Silva
The Power 9 as_notify/wait feature provides a lower latency way to
signal a thread that work is complete. This series enables the use of
this feature from OpenCAPI adapters, as well as addressing a potential
starvation issue when allocating thread IDs.
Alastair D'Silva (7)
From: Madhavan Srinivasan
If there is no d-cache-size property in the device tree, l1d_size could
be zero. We don't actually expect that to happen, it's only been seen
on mambo (simulator) in some configurations.
A zero-size l1d_size leads to the loop in the asm wrapping around to
2^64-1, and th
On Mon, 16 Apr 2018 14:32:40 +1000
Nicholas Piggin wrote:
> When running a SMP radix guest, KVM can get into page fault / tlbie
> storms -- hundreds of thousands to the same address from different
> threads -- due to partition scoped page faults invalidating the
> page table entry if it was found
On Sun, 15 Apr 2018 20:36:56 +0300
Mike Rapoport wrote:
> I didn't mean we should keep it as unorganized jumble of stuff and I agree
> that splitting the documentation by audience is better because developers
> are already know how to find it :)
>
> I just thought that putting the doc into the p
On Mon, Apr 9, 2018 at 4:05 PM, Dan Williams wrote:
> On Mon, Apr 9, 2018 at 1:52 PM, Rob Herring wrote:
>> On Mon, Apr 9, 2018 at 2:46 AM, Oliver O'Halloran wrote:
>>> Some OF platforms (pseries and some SPARC systems) has their own
>>> implementations of NUMA affinity detection rather than usi
From: Thomas Falcon
Date: Sun, 15 Apr 2018 18:53:36 -0500
> Due to a firmware bug, the hypervisor can send an interrupt to a
> transmit or receive queue just prior to a partition migration, not
> allowing the device enough time to handle it and send an EOI. When
> the partition migrates, the inte
On Wed, Apr 11, 2018 at 02:35:51PM +0800, Ran Wang wrote:
> From: Li Yang
Needs a commit msg and the subject should give some indication of what
the update is. And also start with "dt-bindings: ..."
>
> Signed-off-by: Li Yang
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Ran Wang
> ---
> C
Add a test of the relative branch patching logic in the alternate
section feature fixup code. This tests that if we branch past the last
instruction of the alternate section, the branch is not patched.
That's because the assembler will have created a branch that already
points to the first instruct
We want this to remain the last test (because it's disabled by
default), so give it a non-numbered name so we don't have to renumber
it when adding new tests before it.
Signed-off-by: Michael Ellerman
---
arch/powerpc/lib/feature-fixups-test.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-
The code patching code has always been a bit confused about whether
it's best to use void *, unsigned int *, char *, etc. to point to
instructions. In fact in the feature fixups tests we use both unsigned
int[] and u8[] in different places.
Unfortunately the tests that use unsigned int[] calculate
The expected case for this test was wrong, the source of the alternate
code sequence is:
FTR_SECTION_ELSE
2:or 2,2,2
PPC_LCMPI r3,1
beq 3f
blt 2b
b 3f
b 1b
ALT_FTR_SECTION_END(0, 1)
3:or 1,1,1
or
When we patch an alternate feature section, we have to adjust any
relative branches that branch out of the alternate section.
But currently we have a bug if we have a branch that points to past
the last instruction of the alternate section, eg:
FTR_SECTION_ELSE
1: b 2f
or
Ard Biesheuvel writes:
> On 11 April 2018 at 16:49, Michael Ellerman
> wrote:
>> On Tue, 2018-04-10 at 01:22:06 UTC, Michael Ellerman wrote:
>>> If you build the kernel with CONFIG_RELOCATABLE=n, then install the
>>> modules, rebuild the kernel with CONFIG_RELOCATABLE=y and leave the
>>> old mod
The patch
ASoC: fsl_esai: Add freq check in set_dai_sysclk()
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and se
Le 13/04/2018 à 13:59, Philippe Bergheaud a écrit :
Skiboot used to set the default Tunnel BAR register value when capi mode
was enabled. This approach was ok for the cxl driver, but prevented other
drivers from choosing different values.
Skiboot versions > 5.11 will not set the default value an
From: "Aneesh Kumar K.V"
Testing with a threaded version of mmap_bench which allocate 1G chunks and
with large number of threads we find:
without patch
32.72% mmap_bench [kernel.vmlinux][k] do_raw_spin_lock
|
---do_raw_spin_lock
|
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 10 --
arch/powerpc/include/asm/book3s/64/pgalloc.h | 8 +++-
arch/powerpc/include/asm/book3s/64/pgtable.h | 4 ++--
arch/powerpc/mm/hash_utils_64.c | 1 -
arc
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-4k.h | 2 +
arch/powerpc/include/asm/book3s/64/hash-64k.h | 7 +++
arch/powerpc/include/asm/book3s/64/mmu.h | 1 +
arch/powerpc/include/asm/book3s/64/pgalloc.h | 2 +
arch/powerpc
From: "Aneesh Kumar K.V"
Instead of encoding shift in the table address, use an enumerated index value.
This allow us to do different things in the callback for pte and pmd.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 10 +++
arch/powerpc/include/asm/
From: "Aneesh Kumar K.V"
4K config use one full page at level 4 of the pagetable. Add support for single
fragment allocation in pagetable fragment code and and use that for 4K config.
This makes both 4k and 64k use the same code path. Later we will switch pmd to
use the page table fragment code.
From: "Aneesh Kumar K.V"
Now that we have removed 64K page size support, the RCU page table free can
be much simpler for nohash. Make a copy of the the rcu callback to pgalloc.h
header similar to nohash 32. We could possibly merge 32 and 64 bit there. But
that is for a later patch
We also move t
From: "Aneesh Kumar K.V"
We have in Kconfig
config PPC_64K_PAGES
bool "64k page size"
depends on !PPC_FSL_BOOK3E && (44x || PPC_BOOK3S_64 || PPC_BOOK3E_64)
select HAVE_ARCH_SOFT_DIRTY if PPC_BOOK3S_64
Only supported BOOK3E 64 bit platforms is FSL_BOOK3E. Remove the dead
From: "Aneesh Kumar K.V"
We rename the alloc and get_from_cache to indicate they operate on pte
fragments. In later patch we will add pmd fragment support.
No functional change in this patch.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/pgtable_64.c | 9 +
1 file changed, 5 ins
From: "Aneesh Kumar K.V"
In later patch we switch pmd_lock from mm->page_table_lock to split pmd ptlock.
It avoid compilations issues, use pmd_lockptr helper.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/pgtable-book3s64.c | 4 ++--
arch/powerpc/mm/pgtable-hash64.c | 8 +---
arch/
From: "Aneesh Kumar K.V"
In the next set of patches, we will switch pmd allocator to use page fragments
and the locking will be updated to split pmd ptlock. We want to avoid using
fragments for partition-scoped table. Use slab cache similar to level 4 table
Signed-off-by: Aneesh Kumar K.V
---
From: "Aneesh Kumar K.V"
Only code movement and avoid #ifdef.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/pgtable-book3s64.c | 54
arch/powerpc/mm/pgtable_64.c | 56 --
2 files changed, 54 insertions(+), 56
8xx use slice code when hugetlbfs is enabled. We missed a header include on
8xx which resulted in the below build failure.
config: mpc885_ads_defconfig + CONFIG_HUGETLBFS
CC arch/powerpc/mm/slice.o
arch/powerpc/mm/slice.c: In function 'slice_get_unmapped_area':
arch/powerpc/mm/slice.c:655
This patch series add split pmd pagetable lock for book3s64. nohash64 also
should
be able to switch to this. I need to workout the code dependency. This series
also migh have broken the build on platforms otherthan book3s64. I am sending
this early
to get feedback on whether we should continue wi
43 matches
Mail list logo
