Currently a kernel that is built with CONFIG_PPC_RADIX_MMU=n, and then
booted on a 64-bit Hash MMU system will crash on the first SLB miss,
typically with an oops something like:
Unrecoverable exception 4100 at c0969504
cpu 0x0: Vector: 4100 at [c0de78e0]
pc: c09
Follow the example of the cpu feature code, and add a mask of possible
MMU features, MMU_FTRS_POSSIBLE.
This is used in mmu_has_feature(), which allows the possible mask to act
as a shortcut for any features that are not possible, but still allows
the feature bit itself to be defined.
We will use
On Wed, 2016-05-11 at 10:48 +0530, Aneesh Kumar K.V wrote:
> This should not have any impact on hash, because hash does tlb
> invalidate with every pte update and we don't implement
> flush_tlb_* functions for hash. With radix we should make an explicit
> call to flush tlb outside pte update.
>
>
> From: Alex Williamson [mailto:alex.william...@redhat.com]
> Sent: Thursday, May 05, 2016 11:05 PM
>
> On Thu, 5 May 2016 12:15:46 +
> "Tian, Kevin" wrote:
>
> > > From: Yongji Xie [mailto:xyj...@linux.vnet.ibm.com]
> > > Sent: Thursday, May 05, 2016 7:43 PM
> > >
> > > Hi David and Kevin,
This should not have any impact on hash, because hash does tlb
invalidate with every pte update and we don't implement
flush_tlb_* functions for hash. With radix we should make an explicit
call to flush tlb outside pte update.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/pgtable-book3s64.
On 10/05/16 14:57, Oliver O'Halloran wrote:
> POWER ISA v3 adds large decrementer (LD) mode of operation which increases
> the size of the decrementer register from 32 bits to an implementation
> defined with of up to 64 bits.
>
> This patch adds support for the LD on processors with the CPU_FTR
On 11/05/16 14:55, Rashmica Gupta wrote:
> The same logic for tm_abort appears twice, so pull it out into a
> function.
>
> Signed-off-by: Rashmica Gupta
> ---
> arch/powerpc/mm/hash_utils_64.c | 47
> ++---
> 1 file changed, 21 insertions(+), 26 deletions(
On 11/05/16 11:15, Gavin Shan wrote:
> When CONFIG_KVM_XICS is enabled, CPU_UP_PREPARE and other macros for
> CPU states in linux/cpu.h are needed by arch/powerpc/kvm/book3s_hv.c.
> Otherwise, build error as below is seen:
>
>gwshan@gwshan:~/sandbox/l$ make arch/powerpc/kvm/book3s_hv.o
>
The same logic for tm_abort appears twice, so pull it out into a
function.
Signed-off-by: Rashmica Gupta
---
arch/powerpc/mm/hash_utils_64.c | 47 ++---
1 file changed, 21 insertions(+), 26 deletions(-)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powe
Gavin,
On Tue, 3 May 2016 23:22:46 Gavin Shan wrote:
> This exports 4 functions, which base on the corresponding OPAL
> APIs to get/set PCI slot status. Those functions are going to
> be used by PowerNV PCI hotplug driver:
>
>pnv_pci_get_device_tree()opal_get_device_tree()
>pnv_pci_ge
On Thu, 2016-05-05 at 13:10 +0200, Arnd Bergmann wrote:
> On Thursday 05 May 2016 09:41:32 Yangbo Lu wrote:
> > > -Original Message-
> > > From: Arnd Bergmann [mailto:a...@arndb.de]
> > > Sent: Thursday, May 05, 2016 4:32 PM
> > > To: linuxppc-dev@lists.ozlabs.org
> > > Cc: Yangbo Lu; linux
Balbir Singh writes:
> On 11/05/16 04:09, Aneesh Kumar K.V wrote:
>> Balbir Singh writes:
>>
>>> Deduplicate to one function to compute the actual page size.
>>> Some additional warnings added for AP size as well.
>>
>>
>> This is getting chaned in a cleanup series I am testing before posting
When CONFIG_KVM_XICS is enabled, CPU_UP_PREPARE and other macros for
CPU states in linux/cpu.h are needed by arch/powerpc/kvm/book3s_hv.c.
Otherwise, build error as below is seen:
gwshan@gwshan:~/sandbox/l$ make arch/powerpc/kvm/book3s_hv.o
:
CC arch/powerpc/kvm/book3s_hv.o
arch/
On 11/05/16 04:09, Aneesh Kumar K.V wrote:
> Balbir Singh writes:
>
>> Deduplicate to one function to compute the actual page size.
>> Some additional warnings added for AP size as well.
>
>
> This is getting chaned in a cleanup series I am testing before posting.
> The change from ap to psi
The array crash_shutdown_handles is an array of size CRASH_HANDLER_MAX+1
containing up to CRASH_HANDLER_MAX shutdown_handlers. It is assumed to
be NULL terminated, which it is under normal circumstances. Array
accesses in the functions crash_shutdown_unregister() and
default_machine_crash_shutdown(
On Tue, 2016-05-10 at 18:50 +, Scott Wood wrote:
> On 05/09/2016 03:20 AM, Horia Ioan Geanta Neag wrote:
> > On 5/5/2016 6:37 PM, Horia Geantă wrote:
> > > This will allow device drivers to consistently use io{read,write}XX
> > > also for 64-bit accesses.
> > >
> > > Signed-off-by: Horia Ge
On Tue, 2016-16-02 at 06:31:53 UTC, Oliver O'Halloran wrote:
> There is a switch fallthough in instr_analyze() which can cause
> an invalid instruction to be emulated as a different, valid,
> instruction. The rld* (opcode 30) case extracts a sub-opcode from
> bits 3:1 of the instruction word. Howev
On Thu, 2016-05-05 at 20:44:44 UTC, Lennart Sorensen wrote:
> powerpc: Fix sstep compile on powerpcspe
>
> Commit be96f63375a14ee8e690856ac77e579c75bd0bae introduced ldarx and stdcx
> into the instructions in sstep.c, which are not accepted by the assembler
> on powerpcspe, but does seem to be acc
On Fri, 2016-29-04 at 08:55:15 UTC, Alexey Kardashevskiy wrote:
> We are going to have multiple different types of PHB on the same system
> with POWER8 + NVLink and PHBs will have different IOMMU ops. However
> we only really care about one callback - create_table - so we can
> relax the compatibil
On Wed, 2016-04-05 at 04:48:32 UTC, Ian Munsie wrote:
> From: Ian Munsie
>
> These defines are not used, but other equivalent definitions
> (CXL_SPA_SW_CMD_*) are used. Remove the unused defines.
>
> Signed-off-by: Ian Munsie
> Reviewed-by: Andrew Donnellan
Applied to powerpc next, thanks.
h
On Wed, 2016-04-05 at 04:46:30 UTC, Ian Munsie wrote:
> From: Ian Munsie
>
> num_of_process is a 16 bit field, theoretically allowing an AFU to
> support 16K processes, however the scheduled process area currently has
> a maximum size of 1MB, which limits the maximum number of processes to
> 7704
On Wed, 2016-04-05 at 04:52:58 UTC, Ian Munsie wrote:
> From: Ian Munsie
>
> In the cxl kernel API, it is possible to create a context and start it
> without allocating any interrupts. Since we assign or allocate the PSL
> interrupt when allocating AFU interrupts this will lead to a situation
> w
On Fri, 2016-22-04 at 13:39:22 UTC, Christophe Lombard wrote:
> In the PowerVM environment, the PHYP CoherentAccel component manages
> the state of the Coherent Accelerator Processor Interface adapter and
> virtualizes CAPI resources, handles CAPP, PSL, PSL Slice errors - and
> interrupts - and pro
On Fri, 2016-06-05 at 07:46:36 UTC, Ian Munsie wrote:
> From: Ian Munsie
>
> cxl devices typically access memory using an MMU in much the same way as
> the CPU, and each context includes a state register much like the MSR in
> the CPU. Like the CPU, the state register includes a bit to enable
> r
On Tue, 2016-01-03 at 05:47:46 UTC, Mahesh Salgaonkar wrote:
> From: Mahesh Salgaonkar
>
> The routine machine_check_pSeries_early() is only used on powernv, not
> pseries. Hence rename machine_check_pSeries_early to
> machine_check_powernv_early.
>
> Reported-by: Paul Mackerras
> Signed-off-by
On Fri, 2016-26-02 at 00:26:26 UTC, Gavin Shan wrote:
> The function is used to update the MMU with software PTE. It can
> be called by data access exception handler (0x300) or instruction
> access exception handler (0x400). If the function is called by
> 0x400 handler , the local variable @access
On Wed, 2015-23-12 at 05:49:50 UTC, Rashmica Gupta wrote:
> Currently there is a reg.h in pmu/ebb that has defines that are useful in
> other powerpc selftests so move this up into selftests/powerpc folder. Also
> include in utils.h - as this is often used in self tests. Add in some other
> useful
On Thu, 2016-05-05 at 07:54:08 UTC, Oliver O'Halloran wrote:
> The zone that contains the top of memory will be either ZONE_NORMAL
> or ZONE_HIGHMEM depending on the kernel config. There are two functions
> that require this information and both of them use an #ifdef to set
> a local variable (top_
On Tue, 2016-03-05 at 05:41:20 UTC, Gavin Shan wrote:
> Each PHB has one instance of "struct pci_controller_ops" that includes
> various callbacks called by PCI subsystem. In the definition of this
> struct, some callbacks have explicit names for its arguments, but the
> left don't have.
>
> This
On 11 May 2016 01:05, "Aneesh Kumar K.V"
wrote:
>
>
> I am finding the below softlockups with kvm guest. This is using the
> same version of kernel for host and guest.
>
> [ 323.547841] NMI watchdog: BUG: soft lockup - CPU#7 stuck for 22s!
[systemd-timesyn:3116]
> [ 323.548023] Modules linked in
bit of a conundrum here ... we have a legacy MPC8360 system here, on
which we installed linux built with wind river linux 8. we obviously
want to push the various bus frequencies to their max for best
performance, and the device tree that was being used for this system
assigned rather slow speed
On 05/09/2016 03:20 AM, Horia Ioan Geanta Neag wrote:
> On 5/5/2016 6:37 PM, Horia Geantă wrote:
>> This will allow device drivers to consistently use io{read,write}XX
>> also for 64-bit accesses.
>>
>> Signed-off-by: Horia Geantă
>
> It would be great if PPC maintainers could Ack this patch.
>
Balbir Singh writes:
> The .longs with the shifts are harder to read, use more
> meaningful names for the opcodes. PPC_TLBIE_5 is introduced
> for the 5 opcode variation of the instruction due to an existing
> op-code for the 2 opcode variant
>
> Signed-off-by: Balbir Singh
Reviewed-by: Aneesh
Balbir Singh writes:
> Deduplicate to one function to compute the actual page size.
> Some additional warnings added for AP size as well.
This is getting chaned in a cleanup series I am testing before posting.
The change from ap to psize need more update in commit message.
commit 701e0d3dc33
On 05/02/2016 01:57 PM, Bjorn Helgaas wrote:
On Thu, Apr 14, 2016 at 06:55:24PM -0300, Guilherme G. Piccoli wrote:
The domain/PHB field of PCI addresses has its value obtained from a
global variable, incremented each time a new domain (represented by
struct pci_controller) is added on the system
On 09/05/2016 10:14, Thomas Huth wrote:
>> > Tested-by: Thomas Huth
> Ping!
>
> Alex, Paul, could you please pick up this patch? This patch is required
> to get the kvm-unit-tests working properly with kvm-pr, so I'd be glad
> if we could get this included finally...
I have a pull request for
Le 06/05/2016 09:46, Ian Munsie a écrit :
From: Ian Munsie
cxl devices typically access memory using an MMU in much the same way as
the CPU, and each context includes a state register much like the MSR in
the CPU. Like the CPU, the state register includes a bit to enable
relocation, which we cu
On Tue, 2016-05-10 at 12:30 -0400, Tejun Heo wrote:
> Hello,
>
> On Tue, May 10, 2016 at 11:34:40AM +0530, Vinod Koul wrote:
> >
> > >
> > > slave-dma [1], branch topic/dw. But I think Vinod can tell us
> > > which
> > > tag/branch will be immutable. Vinod?
> > Please use branch topic/dw. I will
Hello,
On Tue, May 10, 2016 at 11:34:40AM +0530, Vinod Koul wrote:
> > slave-dma [1], branch topic/dw. But I think Vinod can tell us which
> > tag/branch will be immutable. Vinod?
>
> Please use branch topic/dw. I will not rebase this before sending to Linus.
Okay, pulled topic/dw into libata/fo
The .longs with the shifts are harder to read, use more
meaningful names for the opcodes. PPC_TLBIE_5 is introduced
for the 5 opcode variation of the instruction due to an existing
op-code for the 2 opcode variant
Signed-off-by: Balbir Singh
---
arch/powerpc/include/asm/ppc-opcode.h | 14 +++
I am finding the below softlockups with kvm guest. This is using the
same version of kernel for host and guest.
[ 323.547841] NMI watchdog: BUG: soft lockup - CPU#7 stuck for 22s!
[systemd-timesyn:3116]
[ 323.548023] Modules linked in:
[ 323.548029] CPU: 7 PID: 3116 Comm: systemd-timesyn Not
Deduplicate to one function to compute the actual page size.
Some additional warnings added for AP size as well.
Signed-off-by: Balbir Singh
---
arch/powerpc/mm/hugetlbpage-radix.c | 31 ---
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/
This patch cleans up some bits of the radix tree implementation
no functionality changes were introduced. Most of them were based
on review comments. I've lightly tested the patches and checked
for correctness of code generation for the .long instruction change
bits. Please review
On Thu, 28 Apr 2016, Josh Poimboeuf wrote:
> Change livepatch to use a basic per-task consistency model. This is the
> foundation which will eventually enable us to patch those ~10% of
> security patches which change function or data semantics. This is the
> biggest remaining piece needed to mak
On Tuesday 10 May 2016 08:37:52 Benjamin Herrenschmidt wrote:
> On Mon, 2016-05-09 at 17:08 +0200, Arnd Bergmann wrote:
> >
> > Unfortunately, I don't see any way this could be done in MIPS specific
> > code: There is typically a byteswap between the internal bus and the PCI
> > bus on big-endian
On 05/08/2016 11:07 PM, Aneesh Kumar K.V wrote:
> oliver writes:
>
>> > Hi,
>> >
>> > I've been working on kernel support for a persistent memory (nvdimm)
>> > device and the kernel driver infrastructure requires ZONE_DEVICE for
>> > DAX support.. I've had it enabled in my tree for some time (wit
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