Le 15/01/2016 14:57, Sebastian Hesselbarth a écrit :
> On 15.01.2016 05:01, Shaohui Xie wrote:
>>> -Original Message-
>>> From: Andrew Lunn [mailto:and...@lunn.ch]
>>> Sent: Friday, January 15, 2016 12:44 AM
>>> To: shh@gmail.com
>>> Cc: devicet...@vger.kernel.org; net...@vger.kernel.or
On 13 January 2016 03:39:17 GMT+11:00, Steven Munroe
wrote:
>On Mon, 2016-01-11 at 15:48 -0500, Carlos O'Donell wrote:
>> On 01/11/2016 02:55 PM, Tulio Magno Quites Machado Filho wrote:
>> > "Carlos O'Donell" writes:
>> >
>> >> On 01/11/2016 10:16 AM, Tulio Magno Quites Machado Filho wrote:
>
On 1/11/16 5:55 PM, Tulio Magno Quites Machado Filho wrote:
However, I do agree with the concerns raised by Peter and Adhemerval: glibc
should be in sync with the kernel by the time of the release in order to
guarantee both bits are reserved for the exact same goal and we should have
both AT_H
On 15.01.2016 05:01, Shaohui Xie wrote:
>> -Original Message-
>> From: Andrew Lunn [mailto:and...@lunn.ch]
>> Sent: Friday, January 15, 2016 12:44 AM
>> To: shh@gmail.com
>> Cc: devicet...@vger.kernel.org; net...@vger.kernel.org; linuxppc-
>> d...@lists.ozlabs.org; f.faine...@gmail.com;
On Fri, Jan 15, 2016 at 10:29:12PM +0100, Peter Zijlstra wrote:
> On Fri, Jan 15, 2016 at 09:39:12AM -0800, Paul E. McKenney wrote:
> > Should we start putting litmus tests for the various examples
> > somewhere, perhaps in a litmus-tests directory within each participating
> > architecture? I hav
On Fri, Jan 15, 2016 at 10:27:14PM +0100, Peter Zijlstra wrote:
> On Fri, Jan 15, 2016 at 09:46:12AM -0800, Paul E. McKenney wrote:
> > On Fri, Jan 15, 2016 at 10:13:48AM +0100, Peter Zijlstra wrote:
>
> > > And the stuff we're confused about is how best to express the difference
> > > and guarant
On Fri, Jan 15, 2016 at 09:39:12AM -0800, Paul E. McKenney wrote:
> Should we start putting litmus tests for the various examples
> somewhere, perhaps in a litmus-tests directory within each participating
> architecture? I have a pile of powerpc-related litmus tests on my laptop,
> but they probab
On Fri, Jan 15, 2016 at 09:46:12AM -0800, Paul E. McKenney wrote:
> On Fri, Jan 15, 2016 at 10:13:48AM +0100, Peter Zijlstra wrote:
> > And the stuff we're confused about is how best to express the difference
> > and guarantees of these two forms of transitivity and how exactly they
> > interact.
Madhavan Srinivasan [ma...@linux.vnet.ibm.com] wrote:
> > +enum {
> > +#include "power8-events-list.h"
> > +};
> >
>
> IIUC we dont use this enum as a index to
> some array, so can we do something like this?
Possibly, but its already a macro soup and we would add another
layer of indirection? I
On Fri, Jan 15, 2016 at 09:54:01AM -0800, Paul E. McKenney wrote:
> On Fri, Jan 15, 2016 at 10:24:32AM +, Will Deacon wrote:
> > On Thu, Jan 14, 2016 at 02:55:10PM -0800, Paul E. McKenney wrote:
> > > On Thu, Jan 14, 2016 at 01:36:50PM -0800, Leonid Yegoshin wrote:
> > > > On 01/14/2016 01:29 P
Commit c118baf80256 ("arch/powerpc/mm/numa.c: do not allocate bootmem
memory for non existing nodes") avoided bootmem memory allocation for
non existent nodes.
When DEBUG_PER_CPU_MAPS enabled, powerNV system failed to boot because
in sched_init_numa, cpumask_or operation was done on unallocated no
On 01/15/2016 01:57 AM, Will Deacon wrote:
Paul,
I think you figured this out while I was sleeping, but just to confirm:
1. The MIPS64 ISA doc [1] talks about SYNC in a way that applies only
to memory accesses appearing in *program-order* before the SYNC
2. We need WRC+sync+addr to w
On Fri, Jan 15, 2016 at 10:24:32AM +, Will Deacon wrote:
> On Thu, Jan 14, 2016 at 02:55:10PM -0800, Paul E. McKenney wrote:
> > On Thu, Jan 14, 2016 at 01:36:50PM -0800, Leonid Yegoshin wrote:
> > > On 01/14/2016 01:29 PM, Paul E. McKenney wrote:
> > > >
> > > >>On 01/14/2016 12:34 PM, Paul E.
On Fri, Jan 15, 2016 at 10:13:48AM +0100, Peter Zijlstra wrote:
> On Fri, Jan 15, 2016 at 09:55:54AM +0100, Peter Zijlstra wrote:
> > On Thu, Jan 14, 2016 at 01:29:13PM -0800, Paul E. McKenney wrote:
> > > So smp_mb() provides transitivity, as do pairs of smp_store_release()
> > > and smp_read_acqu
On Fri, Jan 15, 2016 at 09:55:54AM +0100, Peter Zijlstra wrote:
> On Thu, Jan 14, 2016 at 01:29:13PM -0800, Paul E. McKenney wrote:
> > So smp_mb() provides transitivity, as do pairs of smp_store_release()
> > and smp_read_acquire(),
>
> But they provide different grades of transitivity, which is
From: Yongji Xie
> Sent: 15 January 2016 07:06
>
> MSI-X tables are not allowed to be mmapped in vfio-pci
> driver in case that user get to touch this directly.
> This will cause some performance issues when when PCI
> adapters have critical registers in the same page as
> the MSI-X table.
...
If t
- Original Message -
> From: "Raghavendra K T"
> To: "Jan Stancek"
> Cc: linuxppc-dev@lists.ozlabs.org, "raghavendra kt"
> , vdavy...@parallels.com,
> b...@kernel.crashing.org, pau...@samba.org, m...@ellerman.id.au,
> an...@samba.org, n...@linux.vnet.ibm.com,
> gk...@linux.vnet.ibm.co
* Jan Stancek [2016-01-09 18:03:55]:
> Hi,
>
> I'm seeing bare metal ppc64le system crashing early during boot
> with latest upstream kernel (4.4.0-rc8):
>
> # git describe
> v4.4-rc8-96-g751e5f5
>
> [0.625451] Unable to handle kernel paging request for data at address
> 0x
> [
On Thu, Jan 14, 2016 at 02:55:10PM -0800, Paul E. McKenney wrote:
> On Thu, Jan 14, 2016 at 01:36:50PM -0800, Leonid Yegoshin wrote:
> > On 01/14/2016 01:29 PM, Paul E. McKenney wrote:
> > >
> > >>On 01/14/2016 12:34 PM, Paul E. McKenney wrote:
> > >>>
> > >>>The WRC+addr+addr is OK because data de
Hi Linus,
Please pull powerpc updates for 4.5:
The following changes since commit 1ec218373b8ebda821aec00bb156a9c94fad9cd4:
Linux 4.4-rc2 (2015-11-22 16:45:59 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
tags/powerpc-4.5-1
On Fri, 2016-01-15 at 15:59 +1100, Stewart Smith wrote:
> Michael Ellerman writes:
> > So my preference would be just an incremental patch ASAP to fix the kernel
> > to
> > do the right thing with the new interface.
>
> I see that's merged now, which is great! Even if someone is bisecting
> back,
Paul,
On Thu, Jan 14, 2016 at 02:20:46PM -0800, Paul E. McKenney wrote:
> On Thu, Jan 14, 2016 at 01:24:34PM -0800, Leonid Yegoshin wrote:
> > It is not so simple, I mean "local ordering for address and data
> > dependencies". Local ordering is NOT enough. It happens that current
> > MIPS R6 doesn
From: chenhui zhao
Issue:
As a master, the PCI IP block can combine a memory write to the last PCI
double word (4 bytes) of a cacheline with a 4 byte memory write to the
first PCI double word of the subsequent cacheline. This affects 32-bit
PCI target devices that blindly assert STOP on memory-wr
On Fri, Jan 15, 2016 at 09:55:54AM +0100, Peter Zijlstra wrote:
> On Thu, Jan 14, 2016 at 01:29:13PM -0800, Paul E. McKenney wrote:
> > So smp_mb() provides transitivity, as do pairs of smp_store_release()
> > and smp_read_acquire(),
>
> But they provide different grades of transitivity, which is
On Thu, Jan 14, 2016 at 01:29:13PM -0800, Paul E. McKenney wrote:
> So smp_mb() provides transitivity, as do pairs of smp_store_release()
> and smp_read_acquire(),
But they provide different grades of transitivity, which is where all
the confusion lays.
smp_mb() is strongly/globally transitive,
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