On Wed, 2016-01-13 at 11:16 +0530, Aneesh Kumar K.V wrote:
> Michael Ellerman writes:
> > On Thu, 2016-01-07 at 19:16 +1100, Stephen Rothwell wrote:
> > > After merging the powerpc tree, today's linux-next build (powerpc64
> > > allnoconfig) failed like this:
> > >
> > > arch/powerpc/mm/hash_util
On Wed, 2016-01-13 at 11:37 +0530, Aneesh Kumar K.V wrote:
> Benjamin Herrenschmidt writes:
>
> > On Tue, 2016-01-12 at 10:42 +0300, Denis Kirjanov wrote:
> > > > +static inline unsigned long pte_io_cache_bits(void)
> > > > +{
> > > > + return _PAGE_NO_CACHE | _PAGE_GUARDED;
> > > > +}
> > >
Enhance KVM to cause a guest exit with KVM_EXIT_NMI
exit reasons upon a machine check exception (MCE) in
the guest address space if the KVM_CAP_PPC_FWNMI
capability is enabled (instead of delivering 0x200
interrupt to guest). This enables QEMU to build error
log and deliver machine check exception
This patch introduces a new KVM capability to control
how KVM behaves on machine check exception (MCE).
Without this capability, KVM redirects machine check
exceptions to guest's 0x200 vector if the address in
error belongs to the guest. With this capability KVM
causes a guest exit with NMI exit re
"p5ioc2 is used by approximately 2 machines in the world, and has never
ever been a supported configuration."
The code for p5ioc2 is essentially unused and complicates what is already
a very complicated codebase. Its removal is essentially a "free win" in
the effort to simplify the powernv PCI co
On Wed, 2016-01-13 at 17:39 +1100, Andrew Donnellan wrote:
> On 13/01/16 17:10, Russell Currey wrote:
> > "p5ioc2 is used by approximately 2 machines in the world, and has never
> > ever been a supported configuration."
> >
> > The code for p5ioc2 is essentially unused and complicates what is alre
On 13/01/16 17:10, Russell Currey wrote:
"p5ioc2 is used by approximately 2 machines in the world, and has never
ever been a supported configuration."
The code for p5ioc2 is essentially unused and complicates what is already
a very complicated codebase. Its removal is essentially a "free win" i
"p5ioc2 is used by approximately 2 machines in the world, and has never
ever been a supported configuration."
The code for p5ioc2 is essentially unused and complicates what is already
a very complicated codebase. Its removal is essentially a "free win" in
the effort to simplify the powernv PCI co
Benjamin Herrenschmidt writes:
> On Tue, 2016-01-12 at 10:42 +0300, Denis Kirjanov wrote:
>> > +static inline unsigned long pte_io_cache_bits(void)
>> > +{
>> > + return _PAGE_NO_CACHE | _PAGE_GUARDED;
>> > +}
>> This could be just plain #define
>
> Or just use pgprot_noncached()
>
#define pg
On Sun, 2016-01-10 at 01:08 -0200, Guilherme G. Piccoli wrote:weust changes the
way the arch checking is done in function
>
> This patch jeeh_add_device_early(): we use no more eeh_enabled(), but instead
> we check therunning architecture by using the macro machine_is(). If we are
> running on
Balbir Singh writes:
> On Tue, 12 Jan 2016 12:45:36 +0530
> "Aneesh Kumar K.V" wrote:
>
>> Not really needed. But this brings it back to as it was before
>>
>
> Could you expand on not really needed. Could the changelog describe how
> the bits will be used in the follow on patches.
>
What conf
Michael Ellerman writes:
> On Thu, 2016-01-07 at 19:16 +1100, Stephen Rothwell wrote:
>> Hi all,
>>
>> After merging the powerpc tree, today's linux-next build (powerpc64
>> allnoconfig) failed like this:
>>
>> arch/powerpc/mm/hash_utils_64.c: In function 'get_paca_psize':
>> arch/powerpc/mm/ha
On Tue, 2016-01-12 at 10:42 +0300, Denis Kirjanov wrote:
> > +static inline unsigned long pte_io_cache_bits(void)
> > +{
> > + return _PAGE_NO_CACHE | _PAGE_GUARDED;
> > +}
> This could be just plain #define
Or just use pgprot_noncached()
Cheers,
Ben.
On Tue, 12 Jan 2016 12:45:36 +0530
"Aneesh Kumar K.V" wrote:
> Not really needed. But this brings it back to as it was before
>
Could you expand on not really needed. Could the changelog describe how
the bits will be used in the follow on patches.
Balbir
___
On 01/12/2016 05:07 PM, Benjamin Herrenschmidt wrote:
On Tue, 2016-01-12 at 15:40 +1100, Alexey Kardashevskiy wrote:
Quite often drivers set only "write" permission assuming that this
includes "read" permission as well and this works on plenty
platforms.
However IODA2 is strict about this and
On 13/01/16 12:04, Russell Currey wrote:
The recently added OPAL API call, OPAL_CONSOLE_FLUSH, originally took no
parameters and returned nothing. The call was updated to accept the
terminal number to flush, and returned various values depending on the
state of the output buffer.
The prototype
The recently added OPAL API call, OPAL_CONSOLE_FLUSH, originally took no
parameters and returned nothing. The call was updated to accept the
terminal number to flush, and returned various values depending on the
state of the output buffer.
The prototype has been updated and its usage in the OPAL
On 01/12/2016 01:40 PM, Peter Zijlstra wrote:
It is selectable only for MIPS R2 but not MIPS R6. The reason is - most of
MIPS R2 CPUs have short pipeline and that SYNC is just waste of CPU
resource, especially taking into account that "lightweight syncs" are
converted to a heavy "SYNC 0" in man
On Tue, 2016-01-12 at 15:40 +1100, Alexey Kardashevskiy wrote:
> Quite often drivers set only "write" permission assuming that this
> includes "read" permission as well and this works on plenty
> platforms.
> However IODA2 is strict about this and produces an EEH when "read"
> permission is not and
On Tue, 2016-01-12 at 13:29 +, David Laight wrote:
> From: Michael Ellerman
> > Sent: 11 January 2016 09:14
> > On Tue, 2015-24-11 at 10:56:18 UTC, Vaibhav Jain wrote:
> > > Presently when a user-space process issues CXL_IOCTL_START_WORK ioctl we
> > > store the pid of the current task_struct a
On Tue, 2016-01-12 at 10:42 -0500, Steven Rostedt wrote:
> On Tue, 12 Jan 2016 23:14:22 +1100
> Michael Ellerman wrote:
> > From: Ulrich Weigand
> >
> > If a text section starts out with a data blob before the first
> > function start label, disassembly parsing doing in recordmcount.pl
> > gets
On Tue, Jan 12, 2016 at 12:45:14PM -0800, Leonid Yegoshin wrote:
> (I try to answer on multiple mails in one)
>
> First of all, it seems like some generic notes should be given here:
>
> 1. Generic MIPS "SYNC" (aka "SYNC 0") instruction is a very heavy in some
> CPUs. On that CPUs it basically ki
(I try to answer on multiple mails in one)
First of all, it seems like some generic notes should be given here:
1. Generic MIPS "SYNC" (aka "SYNC 0") instruction is a very heavy in
some CPUs. On that CPUs it basically kills pipelines in each CPU, can do
a special memory/IO bus transaction (sim
On Tue, Jan 12, 2016 at 08:28:44AM -0800, Paul E. McKenney wrote:
> On Sun, Jan 10, 2016 at 04:16:32PM +0200, Michael S. Tsirkin wrote:
> > From: Davidlohr Bueso
> >
> > With commit b92b8b35a2e ("locking/arch: Rename set_mb() to smp_store_mb()")
> > it was made clear that the context of this call
Lothar Waßmann wrote:
- select SND_SOC_FSL_SSI
+ select SND_SOC_FSL_SAI if SOC_IMX6UL
+ select SND_SOC_FSL_SSI if SOC_IMX6Q || SOC_IMX6SL || SOC_IMX6SX
I don't think this is compatible with a multiarch kernel.
___
Linuxppc-dev mailin
On Tue, Jan 12, 2016 at 07:13:30PM +0100, Lothar Waßmann wrote:
> i.MX6UL does not have the audio multiplexer (AUDMUX) like e.g. i.MX6Q,
> but apart from that can use the same audio driver. Make audmux
> optional for the imx-sgtl5000 driver, so it can be used on i.MX6UL
> too. Also i.MX6UL require
i.MX6UL does not have the audio multiplexer (AUDMUX) like e.g. i.MX6Q,
but apart from that can use the same audio driver. Make audmux
optional for the imx-sgtl5000 driver, so it can be used on i.MX6UL
too. Also i.MX6UL requires use of the SAI interface rather than SSI.
Signed-off-by: Lothar Waßman
i.MX6UL does not provide an SSI interface like the other i.MX6 SoCs,
but only an SAI interface.
Select the appropriate interface(s) depending on the enabled SoC types.
Signed-off-by: Lothar Waßmann
---
sound/soc/fsl/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/so
This patchset adds support for the i.MX6UL SoC to the imx-sgtl5000
sound driver.
The first patch makes the audmux setup optional for the driver, since
i.MX6UL does not have this unit.
The second patch selects the SAI interface rather than the SSI
interface for the i.MX6UL SoC.
A patch to make the
Add the necessary clock to use the KPP interface on i.MX6UL.
Signed-off-by: Lothar Waßmann
---
drivers/clk/imx/clk-imx6ul.c | 1 +
include/dt-bindings/clock/imx6ul-clock.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/cl
remove whitespace before TAB.
Signed-off-by: Lothar Waßmann
---
drivers/clk/imx/clk-imx6ul.c | 62 ++---
include/dt-bindings/clock/imx6ul-clock.h | 146 +++
2 files changed, 104 insertions(+), 104 deletions(-)
diff --git a/drivers/clk/imx/clk-imx
This patchset adds the clock which is necessary to operate the KPP
unit on i.MX6UL.
The first patch removes bogus whitespace before TABs in indentation.
The second patch adds the clock definition.
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.o
On 01/12/2016 11:39 AM, Steven Munroe wrote:
>> That's the rule. There are no other discussions to be had.
>>
> Well is was posted to to powerpc next:
> https://git.kernel.org/powerpc/c/e708c24cd01ce80b1609d8bacc
>
> We have agreement between the kernel and GLIBC (and the ABI).
>
> The issue is
On Sun, Jan 10, 2016 at 04:17:09PM +0200, Michael S. Tsirkin wrote:
> On powerpc read_barrier_depends, smp_read_barrier_depends
> smp_store_mb(), smp_mb__before_atomic and smp_mb__after_atomic match the
> asm-generic variants exactly. Drop the local definitions and pull in
> asm-generic/barrier.h i
On Mon, 2016-01-11 at 15:48 -0500, Carlos O'Donell wrote:
> On 01/11/2016 02:55 PM, Tulio Magno Quites Machado Filho wrote:
> > "Carlos O'Donell" writes:
> >
> >> On 01/11/2016 10:16 AM, Tulio Magno Quites Machado Filho wrote:
> >>> Adhemerval Zanella writes:
> >>>
> On 08-01-2016 13:36, Pe
On Sun, Jan 10, 2016 at 04:16:32PM +0200, Michael S. Tsirkin wrote:
> From: Davidlohr Bueso
>
> With commit b92b8b35a2e ("locking/arch: Rename set_mb() to smp_store_mb()")
> it was made clear that the context of this call (and thus set_mb)
> is strictly for CPU ordering, as opposed to IO. As such
On Tue, 12 Jan 2016 23:14:22 +1100
Michael Ellerman wrote:
> From: Ulrich Weigand
>
> If a text section starts out with a data blob before the first
> function start label, disassembly parsing doing in recordmcount.pl
> gets confused on powerpc, leading to creation of corrupted module
> objects
On Sun, 10 Jan 2016, Michael S. Tsirkin wrote:
> As on most architectures, on x86 read_barrier_depends and
> smp_read_barrier_depends are empty. Drop the local definitions and pull
> the generic ones from asm-generic/barrier.h instead: they are identical.
>
> This is in preparation to refactorin
On Sun, 10 Jan 2016, Michael S. Tsirkin wrote:
> This defines __smp_xxx barriers for x86,
> for use by virtualization.
>
> smp_xxx barriers are removed as they are
> defined correctly by asm-generic/barriers.h
>
> Signed-off-by: Michael S. Tsirkin
> Acked-by: Arnd Bergmann
Reviewed-by: Thomas
From: Michael Ellerman
> Sent: 11 January 2016 09:14
> On Tue, 2015-24-11 at 10:56:18 UTC, Vaibhav Jain wrote:
> > Presently when a user-space process issues CXL_IOCTL_START_WORK ioctl we
> > store the pid of the current task_struct and use it to get pointer to
> > the mm_struct of the process, whi
On Sun, Jan 10, 2016 at 04:16:22PM +0200, Michael S. Tsirkin wrote:
> I parked this in vhost tree for now, though the inclusion of patch 1 from tip
> creates a merge conflict - but one that is trivial to resolve.
>
> So I intend to just merge it all through my tree, including the
> duplicate patch
On Fri, 2016-08-01 at 05:16:47 UTC, Russell Currey wrote:
> PCI in powernv now supports quite a bit more than p5ioc2, so remove the
> outdated comment.
>
> Signed-off-by: Russell Currey
> Acked-by: Stewart Smith
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/b0eab5b29a55fd9f
On Mon, 2016-11-01 at 03:30:31 UTC, Michael Ellerman wrote:
> On Fri, 2016-01-08 at 17:50 -0500, Steven Rostedt wrote:
> > > Are you going to take this, or do you want me to?
>
> Sorry, yep I'll take it.
>
> I trimmed the change log a bit, final version below.
>
> powerpc: Implement save_stack_trac
On Mon, 2016-11-01 at 02:59:04 UTC, Michael Ellerman wrote:
> In order to support Power9 we need two new HWCAP bits. We are merging
> these ahead of the cputable entry so that glibc can start referring to
> them.
>
> Signed-off-by: Michael Ellerman
Applied to powerpc next.
https://git.kernel.or
On Fri, 2016-08-01 at 00:35:09 UTC, Alistair Popple wrote:
> The emulated NVLink PCI devices share the same IODA2 TCE tables but
> only support a single TVT (instead of the normal two for PCI
> devices). This requires the kernel to manually replace windows with
> either the bypass or non-bypass win
On Sun, 2016-10-01 at 00:54:59 UTC, Hugh Dickins wrote:
> Swapoff after swapping hangs on the G5, when CONFIG_CHECKPOINT_RESTORE=y
> but CONFIG_MEM_SOFT_DIRTY is not set. That's because the non-zero
> _PAGE_SWP_SOFT_DIRTY bit, added by CONFIG_HAVE_ARCH_SOFT_DIRTY=y, is not
> discounted when CONFIG
On Mon, 2016-11-01 at 15:49:34 UTC, "Aneesh Kumar K.V" wrote:
> Core kernel expect swp_entry_t to be consisting of
> only swap type and swap offset. We should not leak pte bits to
> swp_entry_t. This breaks swapoff which use the swap type and offset
> to build a swp_entry_t and later compare that t
On Thu, 2016-07-01 at 08:16:13 UTC, Stephen Rothwell wrote:
> Hi all,
>
> After merging the powerpc tree, today's linux-next build (powerpc64
> allnoconfig) failed like this:
>
> arch/powerpc/mm/hash_utils_64.c: In function 'get_paca_psize':
> arch/powerpc/mm/hash_utils_64.c:869:19: error: 'struc
On Mon, 2015-07-12 at 22:03:32 UTC, Uma Krishnan wrote:
> Add support for future IBM Coherent Accelerator (CXL) device
> with ID of 0x0601.
>
> Signed-off-by: Uma Krishnan
> Reviewed-by: Matthew R. Ochs
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/68adb7bfd66504e97364651fb
On Mon, 2016-11-01 at 05:53:50 UTC, Alistair Popple wrote:
> P8+ hardware reports all errors on PE#0. This patch ensures PE#0 is
> not assigned to NPU devices so that it can be used for EEH.
>
> Signed-off-by: Alistair Popple
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/08f
On Fri, 2016-08-01 at 18:30:10 UTC, Brian Norris wrote:
> Some developers really like to have -Werror enabled for their code, as
> it helps to ensure warning free code. Others don't want -Werror, as it
> (for example) can cause problems when newer (or older) compilers have
> different sets of warni
On Fri, 2016-08-01 at 18:30:09 UTC, Brian Norris wrote:
> GCC 4.6.3 does not support -Wno-unused-const-variable. Instead, use the
> kbuild infrastructure that checks if this options exists.
>
> Fixes: 2cd55c68c0a4 ("cxl: Fix build failure due to -Wunused-variable
> behaviour change")
> Suggested-
On Mon, 2016-11-01 at 05:53:49 UTC, Alistair Popple wrote:
> The P8+ hardware supports four partitionable endpoints (PEs) however
> the hardware reports all errors as occurring on PE#0. This means we
> need to reserve this PE for error handling (EEH) and not assign it to
> a NPU device, implying th
From: Ulrich Weigand
GCC 6 will include changes to generated code with -mcmodel=large,
which is used to build kernel modules on powerpc64le. This was
necessary because the large model is supposed to allow arbitrary
sizes and locations of the code and data sections, but the ELFv2
global entry poi
From: Ulrich Weigand
If a text section starts out with a data blob before the first
function start label, disassembly parsing doing in recordmcount.pl
gets confused on powerpc, leading to creation of corrupted module
objects.
This was not a problem so far since the compiler would never create
su
On Tue, 2016-01-12 at 15:17 +1100, Russell Currey wrote:
> On Tue, 2016-01-12 at 14:44 +1100, Stewart Smith wrote:
> > Michael Ellerman writes:
> > > On Fri, 2015-27-11 at 06:23:07 UTC, Russell Currey wrote:
> > > > On BMC machines, console output is controlled by the OPAL firmware and
> > > > is
On Mon, 2015-12-14 at 23:18 +0300, Denis Kirjanov wrote:
> ./drmgr -c cpu -a -r gives the following warning:
>
> [ 2327.035563]
> RCU used illegally from offline CPU!
> rcu_scheduler_active = 1, debug_locks = 1
> [ 2327.035564] no locks held by swapper/12/0.
> [ 2327.035565]
> stack backtrace:
>
Hi Hemant,
>From: Hemant Kumar [mailto:hem...@linux.vnet.ibm.com]
>
>perf probe through debuginfo__find_probes() in util/probe-finder.c
>checks for the functions' frame descriptions in either .eh_frame section
>of an ELF or the .debug_frame. The check is based on whether either one
>of these secti
On Tue, Jan 12, 2016 at 11:40:12AM +0100, Peter Zijlstra wrote:
> On Tue, Jan 12, 2016 at 11:25:55AM +0100, Peter Zijlstra wrote:
> > On Tue, Jan 12, 2016 at 10:27:11AM +0100, Peter Zijlstra wrote:
> > > 2) the changelog _completely_ fails to explain the sync 0x11 and sync
> > > 0x12 semantics nor
Hi Shilpa,
On Tue, Jan 12, 2016 at 04:24:27AM -0600, Shilpasri G Bhat wrote:
> +static inline int get_chip_index(struct kobject *kobj)
Probably have "get_chip_index(int id)". See the reason below.
> +{
> + int i, id;
> +
> + i = kstrtoint(kobj->name + 4, 0, &id);
> + if (i)
> +
On 01/12/2016 03:54 PM, Shilpasri G Bhat wrote:
> cpu_to_chip_id() does a DT walk through to find out the chip id by taking a
> contended device tree lock. This adds an unnecessary overhead in a hot-path.
> So instead of cpu_to_chip_id() use PIR of the cpu to find the chip id.
>
> Reported-by: A
Hi Shilpa,
Just saw this resend!
On Tue, Jan 12, 2016 at 04:24:26AM -0600, Shilpasri G Bhat wrote:
> Record the throttle event with a trace print replacing the printk,
> except for events like throttling below nominal and occ reset
> event which print a warning message.
>
> Signed-off-by: Shilpa
On 12/23/15, Steven Rostedt wrote:
> On Mon, 14 Dec 2015 23:18:06 +0300
> Denis Kirjanov wrote:
>
>> ./drmgr -c cpu -a -r gives the following warning:
>>
>> [ 2327.035563]
>> RCU used illegally from offline CPU!
>> rcu_scheduler_active = 1, debug_locks = 1
>> [ 2327.035564] no locks held by swapp
On Tue, Jan 12, 2016 at 11:25:55AM +0100, Peter Zijlstra wrote:
> On Tue, Jan 12, 2016 at 10:27:11AM +0100, Peter Zijlstra wrote:
> > 2) the changelog _completely_ fails to explain the sync 0x11 and sync
> > 0x12 semantics nor does it provide a publicly accessible link to
> > documentation that doe
Create sysfs attributes to export throttle information in
/sys/devices/system/cpu/cpufreq/chipN. The newly added sysfs files are as
follows:
1)/sys/devices/system/cpu/cpufreq/chip0/throttle_frequencies
This gives the throttle stats for each of the available frequencies.
The throttle stat of a
This patch adds the powernv_throttle tracepoint to trace the CPU
frequency throttling event, which is used by the powernv-cpufreq
driver in POWER8.
Signed-off-by: Shilpasri G Bhat
CC: Ingo Molnar
CC: Steven Rostedt
---
No changes from v2 and v3.
include/trace/events/power.h | 22 +
Record the throttle event with a trace print replacing the printk,
except for events like throttling below nominal and occ reset
event which print a warning message.
Signed-off-by: Shilpasri G Bhat
---
Changes from v3:
- Separate this patch to contain trace_point changes
- Move struct chip member
cpu_to_chip_id() does a DT walk through to find out the chip id by taking a
contended device tree lock. This adds an unnecessary overhead in a hot-path.
So instead of cpu_to_chip_id() use PIR of the cpu to find the chip id.
Reported-by: Anton Blanchard
Signed-off-by: Shilpasri G Bhat
---
driver
In POWER8, OCC(On-Chip-Controller) can throttle the frequency of the
CPU when the chip crosses its thermal and power limits. Currently,
powernv-cpufreq driver detects and reports this event as a console
message. Some machines may not sustain the max turbo frequency in all
conditions and can be thro
On Tue, Jan 12, 2016 at 10:27:11AM +0100, Peter Zijlstra wrote:
> 2) the changelog _completely_ fails to explain the sync 0x11 and sync
> 0x12 semantics nor does it provide a publicly accessible link to
> documentation that does.
Ralf pointed me at: https://imgtec.com/mips/architectures/mips64/
>
On Tue, Jan 12, 2016 at 10:43:36AM +0200, Michael S. Tsirkin wrote:
> On Mon, Jan 11, 2016 at 05:14:14PM -0800, Leonid Yegoshin wrote:
> > On 01/10/2016 06:18 AM, Michael S. Tsirkin wrote:
> > >On mips dma_rmb, dma_wmb, smp_store_mb, read_barrier_depends,
> > >smp_read_barrier_depends, smp_store_re
On Mon, Jan 11, 2016 at 05:14:14PM -0800, Leonid Yegoshin wrote:
> This statement doesn't fit MIPS barriers variations. Moreover, there is a
> reason to extend that even more specific, at least for smp_store_release and
> smp_load_acquire, look into
>
> http://patchwork.linux-mips.org/patch/1
On Mon, Jan 11, 2016 at 05:14:14PM -0800, Leonid Yegoshin wrote:
> On 01/10/2016 06:18 AM, Michael S. Tsirkin wrote:
> >On mips dma_rmb, dma_wmb, smp_store_mb, read_barrier_depends,
> >smp_read_barrier_depends, smp_store_release and smp_load_acquire match
> >the asm-generic variants exactly. Drop
On 1/12/16, Aneesh Kumar K.V wrote:
> They differ between radix and hash. Hence we need a helper
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/include/asm/book3s/32/pgtable.h | 11 +++
> arch/powerpc/include/asm/book3s/64/hash.h| 11 +++
> arch/powerpc/include/asm/
On 1/12/16, Aneesh Kumar K.V wrote:
> We will have different values for hash and radix. Hence we
> cannot use #define constants. Add helper
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/include/asm/book3s/32/pgtable.h | 5 +
> arch/powerpc/include/asm/book3s/64/hash.h| 5 +
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 42 ---
arch/powerpc/include/asm/book3s/64/hash.h | 14 +++
arch/powerpc/include/asm/book3s/64/pgtable.h | 154 +-
arch/powerpc/mm/pgtable-hash64.c | 58 +-
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