On Tue, Oct 27, 2015 at 11:42:57PM +0300, Alexander Popov wrote:
> >> Hello,
> >>
> >> I've done my best to fix the issues pointed by Timur Tabi and Vinod Koul.
> >> Could I have a feedback please?
> >
> > I dont see to have v4 in my list :( Can you please repost
>
> Hello, Vinod
>
> I'm sure I
NV-Link is a high speed interconnect that is used in conjunction with
a PCI-E connection to create an interface between CPU and GPU that
provides very high data bandwidth. A PCI-E connection to a GPU is used
as the control path to initiate and report status of large data
transfers sent via the NV-L
This commit removed the pcidev field from struct pci_dn as it was no
longer in use by the kernel. However to support finding the
association of Nvlink devices to GPU devices from the device-tree this
field is required.
This reverts commit 250c7b277c65.
Signed-off-by: Alistair Popple
---
arch/po
This series adds support for Nvlink, a high speed interconnect that is
used in conjunction with PCI-E to create a high bandwidth interface
between GPU and CPU.
As the Nvlink hardware interface is similar to IBM's existing PCIe
host bridges no major new kernel or user interfaces are added by this
p
Currently we copy the whole mm_context_t to the paca but only access a
few bits of it. This is wasteful of space paca and also takes quite
some time in the hot path of context switching.
This patch pulls in only the required bits from the mm_context_t to
the paca and on context switch, copies onl
This adds a function to copy the mm->context to the paca. This is
only a basic conversion for now but will be used more extensively in
the next patch.
This also adds #ifdef CONFIG_PPC_BOOK3S around this code since it's
not used elsewhere.
Signed-off-by: Michael Neuling
---
arch/powerpc/include
Hi Anton,
[auto build test ERROR on powerpc/next -- if it's inappropriate base, please
suggest rules for selecting the more suitable base]
url:
https://github.com/0day-ci/linux/commits/Anton-Blanchard/powerpc-Don-t-disable-kernel-FP-VMX-VSX-MSR-bits-on-context-switch/20151028-091736
config:
Acked-by: Ian Munsie
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
sparse identifies the following issues:
drivers/misc/cxl/vphb.c:131:17: warning: incorrect type in assignment
(different address spaces)
drivers/misc/cxl/vphb.c:131:17:expected void volatile [noderef]
*
drivers/misc/cxl/vphb.c:131:17:got void *
drivers/misc/cxl/vphb.c:252:2
On Tue, 2015-10-27 at 19:30 -0700, Nishanth Aravamudan wrote:
> On 28.10.2015 [11:20:05 +0900], Benjamin Herrenschmidt wrote:
> > On Tue, 2015-10-27 at 18:54 -0700, Nishanth Aravamudan wrote:
> > >
> > > In "bypass" mode, what TCE size is used? Is it guaranteed to be
> > > 4K?
> >
> > None :-) Th
Hi Anton,
[auto build test ERROR on powerpc/next -- if it's inappropriate base, please
suggest rules for selecting the more suitable base]
url:
https://github.com/0day-ci/linux/commits/Anton-Blanchard/powerpc-Don-t-disable-kernel-FP-VMX-VSX-MSR-bits-on-context-switch/20151028-091736
config:
Hi Anton,
[auto build test ERROR on powerpc/next -- if it's inappropriate base, please
suggest rules for selecting the more suitable base]
url:
https://github.com/0day-ci/linux/commits/Anton-Blanchard/powerpc-Don-t-disable-kernel-FP-VMX-VSX-MSR-bits-on-context-switch/20151028-091736
config:
On 28.10.2015 [11:20:05 +0900], Benjamin Herrenschmidt wrote:
> On Tue, 2015-10-27 at 18:54 -0700, Nishanth Aravamudan wrote:
> >
> > In "bypass" mode, what TCE size is used? Is it guaranteed to be 4K?
>
> None :-) The TCEs are completely bypassed. You get a N:M linear mapping
> of all memory sta
On Tue, 2015-10-27 at 18:54 -0700, Nishanth Aravamudan wrote:
>
> In "bypass" mode, what TCE size is used? Is it guaranteed to be 4K?
None :-) The TCEs are completely bypassed. You get a N:M linear mapping
of all memory starting at 1<<59 PCI side.
> Seems like this would be a different platform
On 28.10.2015 [12:00:20 +1100], Alexey Kardashevskiy wrote:
> On 10/28/2015 09:27 AM, Nishanth Aravamudan wrote:
> >On 27.10.2015 [17:02:16 +1100], Alexey Kardashevskiy wrote:
> >>On 10/24/2015 07:57 AM, Nishanth Aravamudan wrote:
> >>>On Power, the kernel's page size can differ from the IOMMU's pa
On 27.10.2015 [17:53:22 -0700], David Miller wrote:
> From: Nishanth Aravamudan
> Date: Tue, 27 Oct 2015 15:20:10 -0700
>
> > Well, looks like I should spin up a v4 anyways for the powerpc changes.
> > So, to make sure I understand your point, should I make the generic
> > dma_get_page_shift a co
On Tue, Oct 27, 2015 at 06:11:13PM -0500, Bjorn Helgaas wrote:
>On Mon, Oct 26, 2015 at 11:15:50AM +0800, Wei Yang wrote:
>> This patchset enables EEH on SRIOV VFs. The general idea is to create proper
>> VF edev and VF PE and handle them properly.
>> ...
>
>> Gavin Shan (1):
>> powerpc/eeh: Don'
On Wed, Oct 28, 2015 at 09:04:34AM +1100, Daniel Axtens wrote:
>Hi,
>
>>
>> diff --git a/arch/powerpc/include/asm/pci-bridge.h
>> b/arch/powerpc/include/asm/pci-bridge.h
>> index b3a226b..3d7e537 100644
>> --- a/arch/powerpc/include/asm/pci-bridge.h
>> +++ b/arch/powerpc/include/asm/pci-bridge.h
>
On Tue, Oct 27, 2015 at 06:06:54PM -0500, Bjorn Helgaas wrote:
>On Mon, Oct 26, 2015 at 11:15:51AM +0800, Wei Yang wrote:
>> During EEH recovery, hotplug is applied to the devices which don't
>> have drivers or their drivers don't support EEH. However, the hotplug,
>> which was implemented based on
On 10/28/2015 09:27 AM, Nishanth Aravamudan wrote:
On 27.10.2015 [17:02:16 +1100], Alexey Kardashevskiy wrote:
On 10/24/2015 07:57 AM, Nishanth Aravamudan wrote:
On Power, the kernel's page size can differ from the IOMMU's page size,
so we need to override the generic implementation, which alwa
Remove a bunch of unnecessary fallback functions and group
things in a more logical way.
Signed-off-by: Anton Blanchard
---
arch/powerpc/include/asm/switch_to.h | 39 ++--
1 file changed, 11 insertions(+), 28 deletions(-)
diff --git a/arch/powerpc/include/asm/swi
Most of __switch_to() is housekeeping, TLB batching, timekeeping etc.
Move these away from the more complex and critical context switching
code.
Signed-off-by: Anton Blanchard
---
arch/powerpc/kernel/process.c | 52 +--
1 file changed, 26 insertions(+), 26
Create a single function that flushes everything (FP, VMX, VSX, SPE).
Doing this all at once means we only do one MSR write.
Signed-off-by: Anton Blanchard
---
arch/powerpc/include/asm/switch_to.h | 1 +
arch/powerpc/kernel/process.c| 22 ++
arch/powerpc/kvm/book3s_h
Create a single function that gives everything up (FP, VMX, VSX, SPE).
Doing this all at once means we only do one MSR write.
A context switch microbenchmark using yield():
http://ozlabs.org/~anton/junkcode/context_switch2.c
./context_switch2 --test=yield --fp --altivec --vector 0 0
shows an im
More consolidation of our MSR available bit handling.
Signed-off-by: Anton Blanchard
---
arch/powerpc/include/asm/processor.h | 2 --
arch/powerpc/kernel/fpu.S| 16
arch/powerpc/kernel/process.c| 6 --
arch/powerpc/kernel/vector.S | 10 -
Add a boot option that strictly manages the MSR unavailable bits.
This catches kernel uses of FP/Altivec/SPE that would otherwise
corrupt user state.
Signed-off-by: Anton Blanchard
---
Documentation/kernel-parameters.txt | 6 ++
arch/powerpc/include/asm/reg.h | 9 +
arch/pow
The enable_kernel_*() functions leave the relevant MSR bits enabled
until we exit the kernel sometime later. Create disable versions
that wrap the kernel use of FP, Altivec VSX or SPE.
While we don't want to disable it normally for performance reasons
(MSR writes are slow), it will be used for a d
Create helper functions to set and clear MSR bits after first
checking if they are already set. Grouping them will make it
easy to avoid the MSR writes in a subsequent optimisation.
Signed-off-by: Anton Blanchard
---
arch/powerpc/kernel/process.c | 107 --
With the recent change to enable_kernel_vsx(), we no longer need
to call enable_kernel_fp() and enable_kernel_altivec().
Signed-off-by: Anton Blanchard
---
drivers/crypto/vmx/aes.c | 3 ---
drivers/crypto/vmx/aes_cbc.c | 3 ---
drivers/crypto/vmx/aes_ctr.c | 3 ---
drivers/crypto/vmx/ghash.c
Move the MSR modification into c. Removing it from the assembly
function will allow us to avoid costly MSR writes by batching them
up.
Check the FP and VMX bits before calling the relevant giveup_*()
function. This makes giveup_vsx() and flush_vsx_to_thread() perform
more like their sister functio
Move the MSR modification into new c functions. Removing it from
the low level functions will allow us to avoid costly MSR writes
by batching them up.
Move the check_if_tm_restore_required() check into these new functions.
Signed-off-by: Anton Blanchard
---
arch/powerpc/include/asm/switch_to.h
We used to allow giveup_*() to be called with a NULL task struct
pointer. Now those cases are handled in the caller we can remove
the checks. We can also remove giveup_altivec_notask() which is also
unused.
Signed-off-by: Anton Blanchard
---
arch/powerpc/include/asm/switch_to.h | 1 -
arch/powe
mtmsrd_isync() will do an mtmsrd followed by an isync on older
processors. On newer processors we avoid the isync via a feature fixup.
Signed-off-by: Anton Blanchard
---
arch/powerpc/include/asm/reg.h | 8
arch/powerpc/kernel/process.c | 30 ++
2 files chan
Instead of having multiple giveup_*_maybe_transactional() functions,
separate out the TM check into a new function called
check_if_tm_restore_required().
This will make it easier to optimise the giveup_*() functions in a
subsequent patch.
Signed-off-by: Anton Blanchard
---
arch/powerpc/kernel/p
The UP only lazy floating point and vector optimisations were written
back when SMP was not common, and neither glibc nor gcc used vector
instructions. Now SMP is very common, glibc aggressively uses vector
instructions and gcc autovectorises.
We want to add new optimisations that apply to both UP
No need to execute mflr twice.
Signed-off-by: Anton Blanchard
---
arch/powerpc/kernel/entry_64.S | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index e84e5bc..c8b4225 100644
--- a/arch/powerpc/kernel/entry_64
Move all our context switch SPR save and restore code into two
helpers. We do a few optimisations:
- Group all mfsprs and all mtsprs. In many cases an mtspr sets a
scoreboarding bit that an mfspr waits on, so the current practise of
mfspr A; mtspr A; mfpsr B; mtspr B is the worst scheduling we can
Similar to the non TM load_up_*() functions, don't disable the MSR
bits on the way out.
Signed-off-by: Anton Blanchard
---
arch/powerpc/kernel/fpu.S| 4
arch/powerpc/kernel/vector.S | 4
2 files changed, 8 deletions(-)
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/f
Writing the MSR is slow, so we want to avoid it whenever possible.
A subsequent patch will add a debug option that strictly manages the
FP/VMX/VSX unavailable bits. For now just remove it, matching what
we do in other areas of the kernel (eg enable_kernel_altivec()).
A context switch microbenchma
From: Julian Calaby
Date: Wed, 28 Oct 2015 10:43:35 +1100
> You'll be CCing the maintainers of each architecture on the patches to
> add the functions, so if they do have specific requirements, I'm sure
> they'll let you know or provide patches.
People miss things, maintainers get busy, so while
From: "Busch, Keith"
Date: Tue, 27 Oct 2015 22:36:43 +
> If you're suggesting to compile-time break architectures that currently
> work just fine with NVMe, let me stop you right there.
Silently "working" without the architecture maintainer having to explicity
look at the new interface and m
From: Nishanth Aravamudan
Date: Tue, 27 Oct 2015 15:20:10 -0700
> Well, looks like I should spin up a v4 anyways for the powerpc changes.
> So, to make sure I understand your point, should I make the generic
> dma_get_page_shift a compile-error kind of thing? It will only fail on
> architectures
On Wed, 2015-10-28 at 10:43 +1100, Julian Calaby wrote:
> Hi Nishanth,
> You'll be CCing the maintainers of each architecture on the patches
> to
> add the functions, so if they do have specific requirements, I'm sure
> they'll let you know or provide patches.
That sort of accross-all-arch change
On Mon, Oct 26, 2015 at 11:15:50AM +0800, Wei Yang wrote:
> This patchset enables EEH on SRIOV VFs. The general idea is to create proper
> VF edev and VF PE and handle them properly.
> ...
> Gavin Shan (1):
> powerpc/eeh: Don't block PCI config on resetting VF PE
>
> Wei Yang (11):
> PCI/IOV:
On Mon, Oct 26, 2015 at 11:15:51AM +0800, Wei Yang wrote:
> During EEH recovery, hotplug is applied to the devices which don't
> have drivers or their drivers don't support EEH. However, the hotplug,
> which was implemented based on PCI bus, can't be applied to VF directly.
>
> The patch renames v
On Tue, Oct 27, 2015 at 03:20:10PM -0700, Nishanth Aravamudan wrote:
> On 26.10.2015 [18:27:46 -0700], David Miller wrote:
> > From: Nishanth Aravamudan
> > Date: Fri, 23 Oct 2015 13:54:20 -0700
> >
> > > 1) add a generic dma_get_page_shift implementation that just returns
> > > PAGE_SHIFT
> >
>
Hi Denis,
On Monday 26 October 2015 06:47 PM, Denis Kirjanov wrote:
On 10/26/15, Anju T wrote:
This short patch series add the ability to sample the interrupted
machine state for each hardware sample
Hi,
how can we check your patch series without testing details?
I have mentioned about the c
On Tue, Oct 27, 2015 at 05:02:16PM +1100, Alexey Kardashevskiy wrote:
> >+unsigned long dma_get_page_shift(struct device *dev)
> >+{
> >+struct iommu_table *tbl = get_iommu_table_base(dev);
> >+if (tbl)
> >+return tbl->it_page_shift;
>
>
> All PCI devices have this initialized
Hi Nishanth,
On Wed, Oct 28, 2015 at 10:40 AM, Nishanth Aravamudan
wrote:
> On 28.10.2015 [09:57:48 +1100], Julian Calaby wrote:
>> Hi Nishanth,
>>
>> On Wed, Oct 28, 2015 at 9:20 AM, Nishanth Aravamudan
>> wrote:
>> > On 26.10.2015 [18:27:46 -0700], David Miller wrote:
>> >> From: Nishanth Arav
This allows new-style clock references to be used, which is needed for
fman. The old clock nodes will be removed and all clock references
converted to new-style once the qoriq-cpufreq driver is updated to stop
depending on the old-style references in cpu nodes.
Signed-off-by: Scott Wood
---
Patc
On 28.10.2015 [09:57:48 +1100], Julian Calaby wrote:
> Hi Nishanth,
>
> On Wed, Oct 28, 2015 at 9:20 AM, Nishanth Aravamudan
> wrote:
> > On 26.10.2015 [18:27:46 -0700], David Miller wrote:
> >> From: Nishanth Aravamudan
> >> Date: Fri, 23 Oct 2015 13:54:20 -0700
> >>
> >> > 1) add a generic dma
Hi James,
This series has been reviewed/acked. Is there anything else you're looking
for before this can make it into -next?
-matt
> On Oct 21, 2015, at 3:08 PM, Matthew R. Ochs
> wrote:
>
> This patch set contains various fixes and corrections for issues that
> were found during test and co
Hi Nishanth,
On Wed, Oct 28, 2015 at 9:20 AM, Nishanth Aravamudan
wrote:
> On 26.10.2015 [18:27:46 -0700], David Miller wrote:
>> From: Nishanth Aravamudan
>> Date: Fri, 23 Oct 2015 13:54:20 -0700
>>
>> > 1) add a generic dma_get_page_shift implementation that just returns
>> > PAGE_SHIFT
>>
>>
On 27.10.2015 [17:02:16 +1100], Alexey Kardashevskiy wrote:
> On 10/24/2015 07:57 AM, Nishanth Aravamudan wrote:
> >On Power, the kernel's page size can differ from the IOMMU's page size,
> >so we need to override the generic implementation, which always returns
> >the kernel's page size. Lookup th
On 27.10.2015 [16:56:10 +1100], Alexey Kardashevskiy wrote:
> On 10/24/2015 07:59 AM, Nishanth Aravamudan wrote:
> >When DDW (Dynamic DMA Windows) are present for a device, we have stored
> >the TCE (Translation Control Entry) size in a special device tree
> >property. Check if we have enabled DDW
On 26.10.2015 [18:27:46 -0700], David Miller wrote:
> From: Nishanth Aravamudan
> Date: Fri, 23 Oct 2015 13:54:20 -0700
>
> > 1) add a generic dma_get_page_shift implementation that just returns
> > PAGE_SHIFT
>
> I won't object to this patch series, but if I had implemented this I
> would have
Hi,
>
> diff --git a/arch/powerpc/include/asm/pci-bridge.h
> b/arch/powerpc/include/asm/pci-bridge.h
> index b3a226b..3d7e537 100644
> --- a/arch/powerpc/include/asm/pci-bridge.h
> +++ b/arch/powerpc/include/asm/pci-bridge.h
> @@ -210,6 +210,7 @@ struct pci_dn {
> #define IODA_INVALID_PE
There are powerpc generic version and x86 local version for
skip_ioresource_align().
Move the powerpc version to setup-bus.c, and kill x86 local version.
Also kill dummy version in microblaze.
Cc: Michal Simek
Cc: Paul Mackerras
Cc: Michael Ellerman
Cc: Arnd Bergmann
Cc: linuxppc-dev@lists.o
Current is using !flags, and we are going to use
IORESOURCE_DISABLED instead of clearing resource flags.
Let's convert all !flags to helper function resource_disabled().
resource_disabled will check !flags and IORESOURCE_DISABLED both.
Cc: linux-al...@vger.kernel.org
Cc: linux-i...@vger.kernel.or
For device resource PREF bit setting under bridge 64-bit pref resource,
we need to make sure only set PREF for 64bit resource, so set
IORESOUCE_MEM_64 for 64bit resource during of device resource flags
parsing.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=96261
Link: https://bugzilla.kernel.o
On 27.10.2015 05:22, Vinod Koul wrote:
> On Thu, Oct 22, 2015 at 01:15:03AM +0300, Alexander Popov wrote:
>> On 12.10.2015 00:08, Alexander Popov wrote:
>>> This driver for Freescale MPC512x LocalPlus Bus FIFO (called SCLPC
>>> in the Reference Manual) allows Direct Memory Access transfers
>>> betw
Update the cpu dlpar add/remove paths to do better error recovery when
a failure occurs during the add/remove operation.
Signed-off-by: Nathan Fontenot
---
Updates for v2:
- Corrected some pr_* statements moving pr_info to pr_debug staements
and pr_debug to pr_warn statements.
arch/powerpc/p
Enable new kernel cpu hotplug functionality by allowing cpu dlpar requests
to be initiated from sysfs.
Signed-off-by: Nathan Fontenot
---
arch/powerpc/platforms/pseries/dlpar.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/dlpar.c
b/arch/powerpc/pla
Add the ability to hotplug add cpus via rtas hotplug events by either
specifying the drc index of the CPU to add, or providing a count of the
number of CPUs to add.
Signed-off-by: Nathan Fontenot
---
arch/powerpc/platforms/pseries/hotplug-cpu.c | 94 ++
1 file changed,
Add the ability to dlpar remove CPUs via hotplug rtas events, either by
specifying the drc-index of the CPU to remove or providing a count of cpus
to remove.
To remove multiple cpus in a single request we create a list of possible
DR (Dynamic Reconfiguration) cpus and their drc indexes that can be
Re-factor the cpu hotplug code to support doing cpu hotplug completely in
the kernel and using the existing sysfs probe/release interfaces. This
patch pulls out pieces of existing cpu hotplug code into common routines,
dlpar_cpu_add() and dlpar_cpu_remove(), to be used by both interfaces.
There are
No functional changes, this patch is simply a move of the cpu hotplug
code from pseries/dlpar.c to pseries/hotplug-cpu.c. This is in an effort
to consolidate all of the cpu hotplug code in a common place.
Signed-off-by: Nathan Fontenot
---
arch/powerpc/platforms/pseries/dlpar.c | 226
To better support CPU hotplug in PowerKVM and PowerVM environments, the
handling of CPU dlpar should be done entirely in the kernel. This will allow
a common entry point to be used for PowerVM and PowerKVM CPU dlpar requests.
For both environments the entry point is the same one introduced in a pr
User space checkpoint and restart tool (CRIU) needs the page's change
to be soft tracked. This allows to do a pre checkpoint and then dump
only touched pages.
This is done by using a newly assigned PTE bit (_PAGE_SOFT_DIRTY) when
the page is backed in memory, and a new _PAGE_SWP_SOFT_DIRTY bit whe
Regards,
Igal Liberman
> -Original Message-
> From: Wood Scott-B07421
> Sent: Saturday, September 26, 2015 2:02 AM
> To: Liberman Igal-B31950
> Cc: net...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; linux-
> ker...@vger.kernel.org; Bucur Madalin-Cristian-B32716
>
> Subject: Re: [V5
On Tue, 2015-10-27 at 10:46 -0500, Nathan Fontenot wrote:
> Commit a030e1e4bbd085bbcfd0a23f8d355fcd41f39bed make a change to use
> kstrndup() instead of kmalloc() + strlcpy() in the
> pseries_of_derive_parent()
> routine that introduces a subtle change in the parent path name
> generated.
> The kst
Commit a030e1e4bbd085bbcfd0a23f8d355fcd41f39bed make a change to use
kstrndup() instead of kmalloc() + strlcpy() in the pseries_of_derive_parent()
routine that introduces a subtle change in the parent path name generated.
The kstrndup() routine will copy n characters followed by a terminating null,
Hello,
sorry for the message format, but I don't have the original e-mail.
[...]
diff --git a/drivers/soc/fsl/qbman/bman.h b/drivers/soc/fsl/qbman/bman.h
new file mode 100644
index 000..c987938
--- /dev/null
+++ b/drivers/soc/fsl/qbman/bman.h
@@ -0,0 +1,542 @@
+/* Copyright 2008 - 2015 Free
On 10/27/2015 03:17 AM, Andy Shevchenko wrote:
> On Mon, 2015-10-26 at 14:33 -0500, Nathan Fontenot wrote:
>> Commit a030e1e4bbd085bbcfd0a23f8d355fcd41f39bed made a change to use
>> kstrndup() instead of kmalloc() + strlcpy() in
>> pseries_of_derive_parent()
>> which introduces a subtle change in t
Enable TWR_P102x option by default in mpc85xx_smp_defconfig to support
p1025twr board.
Signed-off-by: Pengbo Li
---
arch/powerpc/configs/mpc85xx_basic_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/configs/mpc85xx_basic_defconfig
b/arch/powerpc/configs/mpc85xx_basic_
On Mon, 2015-10-26 at 14:33 -0500, Nathan Fontenot wrote:
> Commit a030e1e4bbd085bbcfd0a23f8d355fcd41f39bed made a change to use
> kstrndup() instead of kmalloc() + strlcpy() in
> pseries_of_derive_parent()
> which introduces a subtle change in the parent path name generated.
> The kstrndup() routi
On Tue, 2015-10-27 at 02:34 -0500, Zhao Qiang-B45475 wrote:
> On Tue, Oct 27, 2015 at 2:50 PM, Wood Scott-B07421 wrote:
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Tuesday, October 27, 2015 2:50 PM
> > To: Zhao Qiang-B45475
> > Cc: linux-ker...@vger.kernel.org; linuxppc-de
On Tue, Oct 27, 2015 at 2:50 PM, Wood Scott-B07421 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, October 27, 2015 2:50 PM
> To: Zhao Qiang-B45475
> Cc: linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> lau...@codeaurora.org; Xie Xiaobo-R63061 ;
> b...@
78 matches
Mail list logo
