On Tue, 2015-10-06 at 01:10 +0200, Rasmus Villemoes wrote:
> Hi PPC maintainers
>
> Can I get you to ack or nak this? It's a prerequisite for a minor
> patch series for kernel/cpu.c and include/linux/cpumask.h of mine.
Yeah fine by me.
Acked-by: Michael Ellerman
cheers
> On Mon, Sep 28 2015,
On Fri, 2015-10-02 at 16:01 +0200, Christophe Lombard wrote:
> This moves the initialisation of the num_procs to before the SPA
> allocation.
Why? What does it fix? I can't tell from the diff or the change log.
cheers
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On 02/10/15 01:58, Matthew R. Ochs wrote:
When running with an unsupported AFU, the cxlflash driver fails
the probe. When the driver is removed, the following Oops is
encountered on a show_interrupts() thread:
Call Trace:
[c01fba5a7a10] [0003] 0x3 (unreliable)
[c01fba5a7a60]
On Fri, 2015-10-02 at 13:11 -0700, Nishanth Aravamudan wrote:
> Drivers like NVMe need to be able to determine the page size used for
> DMA transfers. Add a new API that defaults to return PAGE_SHIFT on all
> architectures.
>
> Signed-off-by: Nishanth Aravamudan
>
> diff --git a/include/asm-gene
On Sat, 2015-10-03 at 04:33 +0800, kbuild test robot wrote:
> Hi Nishanth,
>
> [auto build test results on v4.3-rc3 -- if it's inappropriate base, please
> ignore]
>
> config: powerpc-defconfig (attached as .config)
> reproduce:
> wget
> https://git.kernel.org/cgit/linux/kernel/git/wfg/
On Fri, 2015-10-02 at 08:43 -0700, Laura Abbott wrote:
> Hi,
>
> We received a report (https://bugzilla.redhat.com/show_bug.cgi?id=1267395) of
> bad assembly
> when compiling on powerpc with little endian
...
> After some discussion with the binutils folks, it turns out that the tlbie
> instruc
On Fri, Oct 02, 2015 at 10:18:00AM -0700, Nishanth Aravamudan wrote:
> We will leverage this macro in the NVMe driver, which needs to know the
> configured IOMMU page shift to properly configure its device's page
> size.
>
> Signed-off-by: Nishanth Aravamudan
>
> ---
> Given this is available, i
On Mon, Oct 05, 2015 at 03:44:07PM +0100, Will Deacon wrote:
> On Thu, Oct 01, 2015 at 07:03:01PM +0100, Paul E. McKenney wrote:
> > On Thu, Oct 01, 2015 at 07:13:04PM +0200, Peter Zijlstra wrote:
> > > On Thu, Oct 01, 2015 at 08:09:09AM -0700, Paul E. McKenney wrote:
> > > > On Thu, Oct 01, 2015 a
On 10/03/2015 05:00 PM, Segher Boessenkool wrote:
On Fri, Oct 02, 2015 at 09:24:46PM -0500, Peter Bergner wrote:
Ok, than we can just zero out r5 for example and use it in tlbie as RS,
right?
That won't assemble _unless_ your assembler is in POWER7 mode. It also
won't do the right thing at ru
Acked-by: Ian Munsie
Excerpts from Christophe Lombard's message of 2015-10-03 00:01:25 +1000:
> This moves the initialisation of the num_procs to before the SPA
> allocation.
>
> Signed-off-by: Christophe Lombard
> ---
> drivers/misc/cxl/native.c | 2 +-
> 1 file changed, 1 insertion(+), 1 del
Hi PPC maintainers
Can I get you to ack or nak this? It's a prerequisite for a minor
patch series for kernel/cpu.c and include/linux/cpumask.h of mine.
Thanks,
Rasmus
On Mon, Sep 28 2015, Rasmus Villemoes wrote:
> Gah, I didn't check for struct members called cpu_online_mask :(
>
> PPC people:
On 01.10.2015 20:11, Timur Tabi wrote:
> On 09/30/2015 04:24 PM, Alexander Popov wrote:
>>> Driver code that has to parse #address-cells or #size-cells
>>> is usually wrong.
>>
>> I would not call it "parsing", I just check whether the dts-file is good.
>> Anyway, could you give me a clue how to do
On Monday, September 14, 2015 03:58:09 PM Viresh Kumar wrote:
> On 14-09-15, 14:01, Shilpasri G Bhat wrote:
> > Log a 'critical' message if the max frequency is reduced below nominal
> > frequency. We already log 'info' message if the max frequency is
> > capped below turbo frequency. CPU should gu
On Thu, Oct 01, 2015 at 07:03:01PM +0100, Paul E. McKenney wrote:
> On Thu, Oct 01, 2015 at 07:13:04PM +0200, Peter Zijlstra wrote:
> > On Thu, Oct 01, 2015 at 08:09:09AM -0700, Paul E. McKenney wrote:
> > > On Thu, Oct 01, 2015 at 02:24:40PM +0200, Peter Zijlstra wrote:
> >
> > > > I must say I'm
Hi Geoff,
Am Sonntag, 4. Oktober 2015, 12:27:19 schrieb Geoff Levand:
> Hi,
>
> On Thu, 2015-09-17 at 12:28 +0200, Marc Dietrich wrote:
> > well, I like to but I couldn't get the kernel booting for some reason.
> > Still trying.
>
> I just tested the ps3-queue branch (v4.3-rc4 based) of my ps3-l
This is the continuation (rebased and reworked) of the series
posted at https://lkml.org/lkml/2014/5/5/153 (which is V6). I remember
to have incremented the version count for the re-send of the first four
patches of the series to Peter Z for generic review which got pulled in
last year. The
This patch enables SW based post processing of BHRB captured branches
to be able to meet more user defined branch filtration criteria in perf
branch stack sampling framework. These changes increase the number of
branch filters and their valid combinations on any powerpc64 server
platform with BHRB
Branch record attributes 'mispred' and 'predicted' are single bit
fields as defined in the perf ABI. Hence the data type of the field
'pred' used during BHRB processing should be changed from integer
to bool. This patch also changes the name of the variable from 'pred'
to 'mispred' making the logic
This patch does some code re-arrangements to make it clear that kernel
ignores any separate privilege level branch filter request and does not
support any combinations of HW PMU branch filters.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/power8-pmu.c | 22 +++---
1 fil
This patch cleans up some existing indentation problem in code and
re organizes the BHRB processing code with an helper function named
'update_branch_entry' making it more readable. This patch does not
change any functionality.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/perf/core-book3s.c
Generic powerpc branch analysis support added in the code patching
library which will help the subsequent patch on SW based filtering
of branch records in perf.
Signed-off-by: Anshuman Khandual
---
arch/powerpc/include/asm/code-patching.h | 15
arch/powerpc/lib/code-patching.c |
This patch adds a test for verifying that all the branch stack
sampling filters supported on powerpc work correctly. It also
adds some assembly helper functions in this regard. This patch
extends the generic event description to handle kernel mapped
ring buffers.
Signed-off-by: Anshuman Khandual
'commit 9de5cb0f6df8 ("powerpc/perf: Add per-event excludes on Power8")'
broke the PMU based BHRB privilege level filter. BHRB depends on the
same MMCR0 bits for privilege level filter which was used to freeze all
the PMCs as a group. Once we moved to individual event based privilege
filters throug
The kernel now supports SW based branch filters for book3s systems with
some specific requirements while dealing with HW supported branch filters
in order to achieve overall OR semantics prevailing in perf branch stack
sampling framework. This patch adapts the BHRB branch filter configuration
to me
This patch enables privilege mode SW branch filters. Also modifies
POWER8 PMU branch filter configuration so that the privilege mode
branch filter implemented as part of base PMU event configuration
is reflected in bhrb filter mask. As a result, the SW will skip and
not try to process the privilege
This patch simply changes the name of the variable from 'bhrb_filter' to
'bhrb_hw_filter' in order to add one more variable which will track SW
filters in generic powerpc book3s code which will be implemented in the
subsequent patch. This patch does not change any functionality.
Signed-off-by: Ans
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