CONFIG_CXL_EEH is for CXL's EEH related code.
Other drivers can depend on or #ifdef on this symbol to configure
PERST behaviour, allowing CXL to participate in the EEH process.
Reviewed-by: Cyril Bur
Signed-off-by: Daniel Axtens
---
drivers/misc/cxl/Kconfig | 6 ++
1 file changed, 6 insert
EEH (Enhanced Error Handling) allows a driver to recover from the
temporary failure of an attached PCI card. Enable basic CXL support
for EEH.
Signed-off-by: Daniel Axtens
---
drivers/misc/cxl/cxl.h | 1 +
drivers/misc/cxl/pci.c | 253
drivers
Provide a kernel API and a sysfs entry which allow a user to specify
that when a card is PERSTed, it's image will stay the same, allowing
it to participate in EEH.
cxl_reset is used to reflash the card. In that case, we cannot safely
assert that the image will not change. Therefore, disallow cxl_r
If the driver doesn't participate in EEH, the AFUs will be removed
by cxl_remove, which will be invoked by EEH.
If the driver does particpate in EEH, the vPHB needs to stick around
so that the it can particpate.
In both cases, we shouldn't remove the AFU/vPHB.
Reviewed-by: Cyril Bur
Signed-off-
As with an adapter, some aspects of initialisation are done only once
in the lifetime of an AFU: for example, allocating memory, or setting
up sysfs/debugfs files.
However, we may want to be able to do some parts of the initialisation
multiple times: for example, in error recovery we want to be ab
Some aspects of initialisation are done only once in the lifetime of
an adapter: for example, allocating memory for the adapter,
allocating the adapter number, or setting up sysfs/debugfs files.
However, we may want to be able to do some parts of the
initialisation multiple times: for example, in
- MMIO pointer unmapping is guarded by a null pointer check.
However, iounmap doesn't null the pointer, just invalidate it.
Therefore, explicitly null the pointer after unmapping.
- afu_desc_mmio also needs to be unmapped.
- PCI regions are allocated in cxl_map_adapter_regs.
Therefore
Check if an IRQ is mapped before releasing it.
This will simplify future EEH code by allowing unconditional unmapping
of IRQs.
Acked-by: Cyril Bur
Signed-off-by: Daniel Axtens
---
drivers/misc/cxl/irq.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/misc/cxl/irq.c b/drive
Previously the SPA was allocated and freed upon entering and leaving
AFU-directed mode. This causes some issues for error recovery - contexts
hold a pointer inside the SPA, and they may persist after the AFU has
been detached.
We would ideally like to allocate the SPA when the AFU is allocated, an
If the PCI channel has gone down, don't attempt to poke the hardware.
We need to guard every time cxl_whatever_(read|write) is called. This
is because a call to those functions will dereference an offset into an
mmio register, and the mmio mappings get invalidated in the EEH
teardown.
Check in th
We're about to make these more complex, so make them functions
first.
Signed-off-by: Daniel Axtens
---
drivers/misc/cxl/cxl.h | 51 ++
1 file changed, 35 insertions(+), 16 deletions(-)
diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
i
CXL accelerators are unfortunately not immune from failure. This patch
set enables them to particpate in the Extended Error Handling process.
This series starts with a number of preparatory patches:
- Patch 1 is cleanup: converting macros to static inlines.
- Patch 2 makes sure we don't touch
On Wed, 2015-29-07 at 07:10:03 UTC, Anshuman Khandual wrote:
> This patch just simplifies the existing code logic while fetching
> the SLB size property from the device tree. This also changes the
> function name from check_cpu_slb_size to init_mmu_slb_size as
> it just initializes the mmu_slb_size
On Fri, 2015-07-08 at 03:18:17 UTC, Daniel Axtens wrote:
> It's a good idea, and it brings us in line with the rest of arch/powerpc.
>
> Signed-off-by: Daniel Axtens
> Acked-by: Michael Neuling
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/d3d73f4b38a8ece19846
cheers
_
On Fri, 2015-07-08 at 03:18:20 UTC, Daniel Axtens wrote:
> An IO address, tagged with __iomem, is passed to debugfs_create_file
> as private data. This requires that it be cast to void *. The cast
> creates a sparse warning:
> /scratch/dja/linux-capi/drivers/misc/cxl/debugfs.c:51:57: warning: cast
On Thu, 2015-06-08 at 13:05:07 UTC, Anshuman Khandual wrote:
> This patch just replaces hard coded values with existing
> DRCONF flags while procesing detected LMBs from the device
> tree. This does not change any functionality.
>
> Signed-off-by: Anshuman Khandual
Applied to powerpc next, thank
On Wed, 2015-29-07 at 07:10:04 UTC, Anshuman Khandual wrote:
> Value of the 'valid' variable is zero when 'esid' is zero and it does
> not matter when 'esid' is non-zero. The variable 'valid' can be dropped
> from the function 'dump_segments' by checking for validity of 'esid'
> inside the nested c
On Wed, 2015-29-07 at 07:10:02 UTC, Anshuman Khandual wrote:
> This patch adds some documentation to 'patch_slb_encoding' function
> explaining about how it clears the existing immediate value in the
> given instruction and inserts a new one there.
>
> Signed-off-by: Anshuman Khandual
Applied to
On Fri, 2015-07-08 at 03:18:18 UTC, Daniel Axtens wrote:
> A few declarations were identified by sparse as needing to be static:
>
> /scratch/dja/linux-capi/drivers/misc/cxl/irq.c:408:6: warning: symbol
> 'afu_irq_name_free' was not declared. Should it be static?
> /scratch/dja/linux-capi/drivers
On Wed, 2015-29-07 at 07:09:58 UTC, Anshuman Khandual wrote:
> This patch just removes one redundant entry for one extern variable
> 'slb_compare_rr_to_size' from the scope. This patch does not change
> any functionality.
>
> Signed-off-by: Anshuman Khandual
Applied to powerpc next, thanks.
htt
On Wed, 2015-29-07 at 07:09:59 UTC, Anshuman Khandual wrote:
> These are essentially SLB individual slots with entries what we are
> dealing with in these functions. Usage of both 'entry' and 'slot'
> synonyms makes it real confusing sometimes. This patch makes it
> uniform across the file by repla
On Tue, Aug 11, 2015 at 11:03:40PM +1000, Alexey Kardashevskiy wrote:
>On 08/06/2015 02:11 PM, Gavin Shan wrote:
>>This adds the refcount to PE, which represents number of PCI
>>devices contained in the PE. When last device leaves from the
>>PE, the PE together with its consumed resources (IO, DMA,
On Tue, Aug 11, 2015 at 12:50:33PM +1000, Alexey Kardashevskiy wrote:
>On 08/11/2015 10:43 AM, Gavin Shan wrote:
>>On Tue, Aug 11, 2015 at 12:39:02AM +1000, Alexey Kardashevskiy wrote:
>>>On 08/06/2015 02:11 PM, Gavin Shan wrote:
The available PE#, represented by a bitmap in the PHB, is allocat
On Tue, Aug 11, 2015 at 12:47:25PM +1000, Alexey Kardashevskiy wrote:
>On 08/11/2015 10:38 AM, Gavin Shan wrote:
>>On Mon, Aug 10, 2015 at 07:53:02PM +1000, Alexey Kardashevskiy wrote:
>>>On 08/06/2015 02:11 PM, Gavin Shan wrote:
Each PHB maintains an array helping to translate RID (Request
>>>
On Mon, Aug 10, 2015 at 07:43:48PM +1000, Alexey Kardashevskiy wrote:
>On 08/06/2015 02:11 PM, Gavin Shan wrote:
>>On P7IOC, the whole DMA32 space is divided evenly to 256MB segments.
>>Each PE can consume one or multiple DMA32 segments. Current code
>>doesn't trace the available DMA32 segments and
On Tue, Aug 11, 2015 at 12:39:02PM +1000, Alexey Kardashevskiy wrote:
>On 08/11/2015 10:29 AM, Gavin Shan wrote:
>>On Mon, Aug 10, 2015 at 07:31:11PM +1000, Alexey Kardashevskiy wrote:
>>>On 08/06/2015 02:11 PM, Gavin Shan wrote:
The original implementation of pnv_ioda_setup_dma() iterates the
On Mon, Aug 10, 2015 at 07:21:12PM +1000, Alexey Kardashevskiy wrote:
>On 08/06/2015 02:11 PM, Gavin Shan wrote:
>>For P7IOC, the whole available DMA32 space, which is below the
>>MEM32 space, is divided evenly into 256MB segments. The number
>>of continuous segments assigned to one particular PE d
On Tue, Aug 11, 2015 at 12:32:13PM +1000, Alexey Kardashevskiy wrote:
>On 08/11/2015 10:12 AM, Gavin Shan wrote:
>>On Mon, Aug 10, 2015 at 05:40:08PM +1000, Alexey Kardashevskiy wrote:
>>>On 08/06/2015 02:11 PM, Gavin Shan wrote:
There're 3 windows (IO, M32 and M64) for PHB, root port and upstr
Hi,
On Wed, Aug 12, 2015 at 10:42 PM, Boaz Harrosh wrote:
> On 08/12/2015 10:05 AM, Christoph Hellwig wrote:
>> It turns out most DMA mapping implementation can handle SGLs without
>> page structures with some fairly simple mechanical work. Most of it
>> is just about consistently using sg_phys.
On Wed, Aug 12, 2015 at 10:57:33PM +1000, Alexey Kardashevskiy wrote:
>On 08/12/2015 09:20 PM, Gavin Shan wrote:
>>On Wed, Aug 12, 2015 at 09:05:09PM +1000, Alexey Kardashevskiy wrote:
>>>On 08/12/2015 08:45 PM, Gavin Shan wrote:
On Tue, Aug 11, 2015 at 12:23:42PM +1000, Alexey Kardashevskiy wr
> The function above doesn't even use the 'rc' value.
Darn, you're right.
I'll fix that in a new version.
--
Regards,
Daniel
--
Regards,
Daniel
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Description: This is a digitally signed message part
___
Linuxppc-dev mailing list
Linuxp
On Wed, Aug 12, 2015 at 10:00 AM, James Bottomley
wrote:
> On Wed, 2015-08-12 at 09:05 +0200, Christoph Hellwig wrote:
...
>> However the ccio (parisc) and sba_iommu (parisc & ia64) IOMMUs seem
>> to be operate mostly on virtual addresses. It's a fairly odd concept
>> that I don't fully grasp, so
Christoph,
On 12 August 2015 at 08:05, Christoph Hellwig wrote:
> Signed-off-by: Christoph Hellwig
> ---
> include/asm-generic/dma-mapping-common.h | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/include/asm-generic/dma-mapping-common.h
> b/include/asm-generic/dm
From: Madalin Bucur
Add qman_delete_cgr_safe() that can be called from any CPU.
This in turn schedules qman_delete_cgr() on the proper CPU.
Signed-off-by: Madalin Bucur
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/qman_api.c | 46 ++
1 file changed
From: Geoff Thorpe
Add debugfs sypport for querying the state of hardware based
queues managed by the DPAA 1.0 Queue Manager.
Signed-off-by: Geoff Thorpe
Signed-off-by: Emil Medve
Signed-off-by: Madalin Bucur
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/Makefile |1 +
drive
From: Hai-Ying Wang
Add support for CPU hotplug for the DPAA 1.0 Buffer Manager
driver
Signed-off-by: Hai-Ying Wang
Signed-off-by: Emil Medve
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/bman_portal.c | 40 +++
drivers/soc/fsl/qbman/dpaa_sys.h|
From: Geoff Thorpe
Add debugfs support for querying the state of hardware based
Buffer Manager pools used in DPAA 1.0.
Signed-off-by: Geoff Thorpe
Signed-off-by: Emil Medve
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/Kconfig|7 ++
drivers/soc/fsl/qbman/Makefile |
From: Geoff Thorpe
This driver enables the Freescale DPAA 1.0 Buffer Manager block. BMan
is a hardware buffer pool manager that allows accelerators
connected to the SoC datapath to acquire and release buffers during
data processing.
Signed-off-by: Geoff Thorpe
Signed-off-by: Emil Medve
Signed-
From: Geoff Thorpe
Add a self test for the DPAA 1.0 Buffer Manager driver. This
test ensures that the driver can properly acquire and release
buffers using the BMan portal infrastructure.
Signed-off-by: Geoff Thorpe
Signed-off-by: Emil Medve
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbma
From: Geoff Thorpe
Add a self test for the DPAA 1.0 Queue Manager driver. The tests
ensure that the driver can properly enqueue and dequeue from frame
queues using the QMan portal infrastructure.
Signed-off-by: Geoff Thorpe
Signed-off-by: Emil Medve
Signed-off-by: Roy Pledge
---
drivers/soc/
From: Hai-Ying Wang
Add support for CPU hotplug for the DPAA 1.0 Queue Manager
driver.
Signed-off-by: Hai-Ying Wang
Signed-off-by: Emil Medve
Signed-off-by: Roy Pledge
---
drivers/soc/fsl/qbman/qman_portal.c | 43 +++
1 file changed, 43 insertions(+)
diff -
The Freescale Data Path Acceleration Architecture (DPAA) is a set of hardware
components on specific QorIQ multicore processors. This architecture provides
the infrastructure to support simplified sharing of networking interfaces and
accelerators by multiple CPU cores and the accelerators.
The
From: Emil Medve
devm_ioremap_prot() was removed in commit dedd24a12,
and was introduced in commit b41e5fffe8.
This reverts commit dedd24a12fe6735898feeb06184ee346907abb5d.
Signed-off-by: Emil Medve
---
arch/powerpc/include/asm/io.h |3 +++
arch/powerpc/lib/Makefile |1 +
arch/pow
On 12.08.15 21:06, nick wrote:
>
>
> On 2015-08-12 03:05 PM, Alexander Graf wrote:
>>
>>
>> On 07.08.15 17:54, Nicholas Krause wrote:
>>> This fixes the incorrect return statement in the function
>>> mpic_set_default_irq_routing from always returning zero
>>> to signal success to this function'
On 2015-08-12 03:05 PM, Alexander Graf wrote:
>
>
> On 07.08.15 17:54, Nicholas Krause wrote:
>> This fixes the incorrect return statement in the function
>> mpic_set_default_irq_routing from always returning zero
>> to signal success to this function's caller to instead
>> return the return va
On 10.08.15 17:27, Nicholas Krause wrote:
> This fixes the wrapper functions kvm_umap_hva_hv and the function
> kvm_unmap_hav_range_hv to return the return value of the function
> kvm_handle_hva or kvm_handle_hva_range that they are wrapped to
> call internally rather then always making the calle
On 07.08.15 17:54, Nicholas Krause wrote:
> This fixes the incorrect return statement in the function
> mpic_set_default_irq_routing from always returning zero
> to signal success to this function's caller to instead
> return the return value of kvm_set_irq_routing as this
> function can fail and
On 06.08.15 12:16, Laurent Vivier wrote:
> Hi,
>
> I'd also like to see this patch in the mainstream as it fixes a bug
> appearing when we switch from vCPU context to hypervisor context (guest
> crash).
Thanks, applied to kvm-ppc-queue.
Alex
___
Lin
On Wed, 2015-08-12 at 09:05 +0200, Christoph Hellwig wrote:
> Dan Williams started to look into addressing I/O to and from
> Persistent Memory in his series from June:
>
> http://thread.gmane.org/gmane.linux.kernel.cross-arch/27944
>
> I've started looking into DMA mapping of these SGLs spe
On Wed, Aug 12, 2015 at 12:05 AM, Christoph Hellwig wrote:
> + for_each_sg(sg, s, nents, i) {
> + if (sg_has_page(s))
> + kmemcheck_mark_initialized(sg_virt(s), s->length);
> + }
[ Again, I'm responding to one random patch - this pattern was in
othe
On Wed, Aug 12, 2015 at 12:05 AM, Christoph Hellwig wrote:
> Make all cache invalidation conditional on sg_has_page() and use
> sg_phys to get the physical address directly.
So this worries me a bit (I'm just reacting to one random patch in the series).
The reason?
I think this wants a big honk
On 08/12/2015 10:05 AM, Christoph Hellwig wrote:
> Dan Williams started to look into addressing I/O to and from
> Persistent Memory in his series from June:
>
> http://thread.gmane.org/gmane.linux.kernel.cross-arch/27944
>
> I've started looking into DMA mapping of these SGLs specifically i
ioremap_base is not initialised and is nowhere used so remove it
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/mmu_decl.h | 1 -
arch/powerpc/mm/pgtable_32.c| 1 -
arch/powerpc/platforms/embedded6xx/mpc10x.h | 8
3 files changed, 10 deletions(-)
d
We are spending between 40 and 160 cycles with a mean of 65 cycles
in the TLB handling routines (measured with mftbl) so make it more
simple althought it adds one instruction
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 15 ---
1 file changed, 4 insertions(+),
Commit 771168494719 ("[POWERPC] Remove unused machine call outs")
removed the call to setup_io_mappings(), so remove the associated
progress line message
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/init_32.c | 4
1 file changed, 4 deletions(-)
diff --git a/arch/powerpc/mm/init_32.c
clear_pages() is never used, and PPC32 is the only architecture
(still) having this function. Neither PPC64 nor any other
architecture has it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/page_32.h | 3 +--
arch/powerpc/kernel/misc_32.S | 7 +++
arch/powerpc/kernel/ppc_k
On PPC8xx, flushing instruction cache is performed by writing
in register SPRN_IC_CST. This registers suffers CPU6 ERRATA.
The patch rewrites the fonction in C so that CPU6 ERRATA will
be handled transparently
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/misc_32.S | 10 --
arc
There is no real need to have set_context() in assembly.
Now that we have mtspr() handling CPU6 ERRATA directly, we
can rewrite set_context() in C language for easier maintenance.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 44 --
CPU6 ERRATA is now handled directly in mtspr(), so we can use the
standard set_dec() fonction in all cases.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/time.h | 6 +-
arch/powerpc/kernel/head_8xx.S | 18 --
2 files changed, 1 insertion(+), 23 deletions(-)
MPC8xx has an ERRATA on the use of mtspr() for some registers
This patch includes the ERRATA handling directly into mtspr() macro
so that mtspr() users don't need to bother about that errata
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h | 2 +
arch/powerpc/include/asm/r
Move 8xx SPRN defines into reg_8xx.h and add some missing ones
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/mmu-8xx.h | 26 +-
arch/powerpc/include/asm/reg_8xx.h | 24
2 files changed, 37 insertions(+), 13 deletions(-)
diff --git
On recent kernels, with some debug options like for instance
CONFIG_LOCKDEP, the BSS requires more than 8M memory, allthough
the kernel code fits in the first 8M.
Today, it is necessary to activate CONFIG_PIN_TLB to get more than 8M
at startup, allthough pinning TLB is not necessary for that.
This
IMMR is now mapped at 0xff00 by page tables so it is not
anymore necessary to PIN TLBs
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig.debug | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 70168a2..452b086 100644
--- a
show IMMR area in startup memory layout
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/mem.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index e1fe333..f987321 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -367,6
Once the linear memory space has been mapped with 8Mb pages, as
seen in the related commit, we get 11 millions DTLB missed during
the reference 600s period. 77% of the missed are on user addresses
and 23% are on kernel addresses (1 fourth for linear address space
and 3 fourth for virtual address sp
x_mapped_by_bats() and x_mapped_by_tlbcam() serve the same kind of
purpose, so lets group them into a single function.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/pgtable_32.c | 33 ++---
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/arch/powe
iounmap() cannot vunmap() area mapped by TLBCAMs either
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/pgtable_32.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 7692d1b..03a073a 100644
--- a/arch/pow
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xf000 : fixmap
* 0xfde0..0xfe00 : consistent mem
* 0xfddf6000..0xfde0 : early ioremap
* 0xc900..0xfddf6000
Now we have a 8xx specific .c file for that so put it in there
as other powerpc variants do
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/8xx_mmu.c | 17 +
arch/powerpc/mm/init_32.c | 19 ---
2 files changed, 17 insertions(+), 19 deletions(-)
diff --git a/a
Now the noltlbs kernel parameter is also applicable to PPC8xx
Signed-off-by: Christophe Leroy
---
Documentation/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/kernel-parameters.txt
b/Documentation/kernel-parameters.txt
index ca80921..572d
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTL
The main purpose of this patchset is to dramatically reduce the time
spent in DTLB miss handler. This is achieved by:
1/ Mapping RAM with 8M pages
2/ Mapping IMMR with a fixed 512K page
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we ge
We are spending between 40 and 160 cycles with a mean of 65 cycles in
the TLB handling routines (measured with mftbl) so make it more
simple althought it adds one instruction.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 13 -
1 file changed, 4 insertions(+),
On 08/12/2015 09:20 PM, Gavin Shan wrote:
On Wed, Aug 12, 2015 at 09:05:09PM +1000, Alexey Kardashevskiy wrote:
On 08/12/2015 08:45 PM, Gavin Shan wrote:
On Tue, Aug 11, 2015 at 12:23:42PM +1000, Alexey Kardashevskiy wrote:
On 08/11/2015 10:03 AM, Gavin Shan wrote:
On Mon, Aug 10, 2015 at 05:
The paca display is already more than 24 lines, which can be problematic
if you have an old school 80x24 terminal, or more likely you are on a
virtual terminal which does not scroll for whatever reason.
We'd like to expand the paca display even more, so add a way to limit
the number of lines that
On Wed, 12 Aug 2015, Christoph Hellwig wrote:
> Use sg_phys() instead of page_to_phys(sg_page(sg)) so that we don't
> require a page structure for all DMA memory.
>
> Signed-off-by: Christoph Hellwig
Acked-by: Sebastian Ott
> ---
> arch/s390/pci/pci_dma.c | 20 ++--
> 1 file
On Wed, Aug 12, 2015 at 09:05:09PM +1000, Alexey Kardashevskiy wrote:
>On 08/12/2015 08:45 PM, Gavin Shan wrote:
>>On Tue, Aug 11, 2015 at 12:23:42PM +1000, Alexey Kardashevskiy wrote:
>>>On 08/11/2015 10:03 AM, Gavin Shan wrote:
On Mon, Aug 10, 2015 at 05:16:40PM +1000, Alexey Kardashevskiy wr
On 08/12/2015 08:45 PM, Gavin Shan wrote:
On Tue, Aug 11, 2015 at 12:23:42PM +1000, Alexey Kardashevskiy wrote:
On 08/11/2015 10:03 AM, Gavin Shan wrote:
On Mon, Aug 10, 2015 at 05:16:40PM +1000, Alexey Kardashevskiy wrote:
On 08/06/2015 02:11 PM, Gavin Shan wrote:
The patch is adding 6 bitma
On Tue, Aug 11, 2015 at 12:06:26PM +1000, Alexey Kardashevskiy wrote:
>On 08/11/2015 09:45 AM, Gavin Shan wrote:
>>On Mon, Aug 10, 2015 at 04:30:09PM +1000, Alexey Kardashevskiy wrote:
>>>On 08/06/2015 02:11 PM, Gavin Shan wrote:
The patch enables M64 window on P7IOC, which has been enabled on
On Tue, Aug 11, 2015 at 12:23:42PM +1000, Alexey Kardashevskiy wrote:
>On 08/11/2015 10:03 AM, Gavin Shan wrote:
>>On Mon, Aug 10, 2015 at 05:16:40PM +1000, Alexey Kardashevskiy wrote:
>>>On 08/06/2015 02:11 PM, Gavin Shan wrote:
The patch is adding 6 bitmaps, three to PE and three to PHB, to t
On Wednesday 12 August 2015 12:39 PM, Christoph Hellwig wrote:
> Make all cache invalidation conditional on sg_has_page() and use
> sg_phys to get the physical address directly.
>
> Signed-off-by: Christoph Hellwig
With a minor nit below.
Acked-by: Vineet Gupta
> ---
> arch/arc/include/asm/dm
From: Cyril Bur
> Sent: 11 August 2015 07:01
...
> You have a dilema with the use of ugly if (rc = foo()). I don't like it but
> the
> file is littered with it.
>
> Looks like the majority of uses in this file the conditional block is only
> one line then it makes sense (or at least in terms of n
Around Wed 12 Aug 2015 09:05:39 +0200 or thereabout, Christoph Hellwig wrote:
> Make all cache invalidation conditional on sg_has_page() and use
> sg_phys to get the physical address directly, bypassing the noop
> page_to_bus.
>
> Signed-off-by: Christoph Hellwig
Acked-by: Hans-Christian Egtvedt
On Wed, 2015-08-12 at 09:05 +0200, Christoph Hellwig wrote:
> Just remove a BUG_ON, the code handles them just fine as-is.
>
> Signed-off-by: Christoph Hellwig
Acked-by: David Woodhouse
--
David WoodhouseOpen Source Technology Centre
david.woodho...@intel.com
On Wed, 2015-08-12 at 13:24 +0530, Anshuman Khandual wrote:
> On 08/12/2015 12:27 PM, Michael Ellerman wrote:
> > @@ -2090,9 +2092,12 @@ static void dump_one_paca(int cpu)
> > printf(" %-*s = %s\n", 16, "present", cpu_present(cpu) ? "yes" : "no");
> > printf(" %-*s = %s\n", 16, "online", cp
On Sun 09-08-15 01:22:52, Eric B Munson wrote:
> With the refactored mlock code, introduce a new system call for mlock.
> The new call will allow the user to specify what lock states are being
> added. mlock2 is trivial at the moment, but a follow on patch will add
> a new mlock state making it us
On Tue, Aug 11, 2015 at 09:14:00PM -0700, Sukadev Bhattiprolu wrote:
> | +static void __perf_read_group_add(struct perf_event *leader, u64
> read_format, u64 *values)
> | {
> | + struct perf_event *sub;
> | + int n = 1; /* skip @nr */
>
> This n = 1 is to skip over the values[0] = 1 + nr_sib
On 08/09/2015 07:57 AM, Benjamin Herrenschmidt wrote:
> On Tue, 2015-08-04 at 19:57 +1000, Michael Ellerman wrote:
>> > On Mon, 2015-13-07 at 08:16:06 UTC, Anshuman Khandual wrote:
>>> > > This patch enables facility unavailable exceptions for generic facility,
>>> > > FPU, ALTIVEC and VSX in /proc
On 08/12/2015 12:27 PM, Michael Ellerman wrote:
> The paca display is already more than 24 lines, which can be problematic
> if you have an old school 80x24 terminal, or more likely you are on a
> virtual terminal which does not scroll for whatever reason.
>
> We'd like to expand the paca display
Signed-off-by: Christoph Hellwig
---
include/asm-generic/dma-mapping-common.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/asm-generic/dma-mapping-common.h
b/include/asm-generic/dma-mapping-common.h
index 940d5ec..afc3eaf 100644
--- a/include/asm-generic/dma-
Just remove a BUG_ON, the code handles them just fine as-is.
Signed-off-by: Christoph Hellwig
---
drivers/iommu/intel-iommu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 3541d65..ae10573 100644
--- a/drivers/iommu/intel-iommu
Make all cache invalidation conditional on sg_has_page() and use
sg_phys to get the physical address directly.
Signed-off-by: Christoph Hellwig
---
arch/parisc/kernel/pci-dma.c | 29 ++---
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/arch/parisc/kernel/
Make all cache invalidation conditional on sg_has_page().
Signed-off-by: Christoph Hellwig
---
arch/powerpc/kernel/dma.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index 35e4dcc..cece40b 100644
--- a/arch/p
Make all cache invalidation conditional on sg_has_page() and use
sg_phys to get the physical address directly. To do this consolidate
the two platform callouts using pages and virtual addresses into a
single one using a physical address.
Signed-off-by: Christoph Hellwig
---
arch/mips/bmips/dma.
Make all cache invalidation conditional on sg_has_page() and use
sg_phys to get the physical address directly.
Signed-off-by: Christoph Hellwig
---
arch/openrisc/kernel/dma.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/k
Only call kmap_atomic_primary when the SG entry is mapped into
kernel virtual space.
XXX: the code already looks odd due to the lack of pairing between
kmap_atomic_primary and kunmap_atomic_primary. Does it work either
before or after this patch?
Signed-off-by: Christoph Hellwig
---
arch/frv/m
Make all cache invalidation conditional on sg_has_page().
Signed-off-by: Christoph Hellwig
---
arch/xtensa/include/asm/dma-mapping.h | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/xtensa/include/asm/dma-mapping.h
b/arch/xtensa/include/asm/dma-mapping
Make all cache invalidation conditional on sg_has_page().
Signed-off-by: Christoph Hellwig
---
arch/sh/kernel/dma-nommu.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/sh/kernel/dma-nommu.c b/arch/sh/kernel/dma-nommu.c
index 5b0bfcd..3b64dc7 100644
--- a/ar
Make all cache invalidation conditional on sg_has_page().
Signed-off-by: Christoph Hellwig
---
arch/metag/include/asm/dma-mapping.h | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/arch/metag/include/asm/dma-mapping.h
b/arch/metag/include/asm/dma-mapp
Switch from sg_virt to sg_phys as blackfin like all nommu architectures
has a 1:1 virtual to physical mapping.
Signed-off-by: Christoph Hellwig
---
arch/blackfin/kernel/dma-mapping.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/blackfin/kernel/dma-mapping.c
b/arc
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