On 20.02.2015 17:06, Sebastian Andrzej Siewior wrote:
On 02/20/2015 03:57 PM, Paolo Bonzini wrote:
On 20/02/2015 15:54, Sebastian Andrzej Siewior wrote:
Usually you see "scheduling while atomic" on -RT and convert them to
raw locks if it is appropriate.
Bogdan wrote in 2/2 that he needs to l
On 20.02.2015 16:54, Sebastian Andrzej Siewior wrote:
On 02/20/2015 03:12 PM, Paolo Bonzini wrote:
Thomas, what is the usual approach for patches like this? Do you take
them into your rt tree or should they get integrated to upstream?
Patch 1 is definitely suitable for upstream, that's the rea
On Mon, 2015-02-23 at 14:40 +1100, Ian Munsie wrote:
> Excerpts from Rasmus Villemoes's message of 2015-02-21 00:26:22 +1100:
> > C99 says that a precision given as simply '.' with no following digits
> > or * should be interpreted as 0. The kernel's printf implementation,
> > however, treats this
Uli,
Sorry for the slow response.
> Michael Neuling wrote on 28.01.2015 05:28:09:
>
> > Sorry, I'm rethinking this as we didn't consider user suspended
> > transactions.
> >
> > It makes sense for normal transactions but for user suspended
> > transactions the running values are the ones you wa
From: Ian Munsie
Commit a6130ed253a931d2169c26ab0958d81b0dce4d6e upstream.
We were missing a return statement in the PSL interrupt handler in the
case of an AFU error, which would trigger an "Unhandled CXL PSL IRQ"
warning. We do actually handle these type of errors (by notifying
userspace), so
From: Ryan Grimm
Commit 6f963ec2d6bf2476a16799eece920acb2100ff1c upstream.
When unbinding and rebinding the driver on a system with a card in PHB0, this
error condition is reached after a few attempts:
ERROR: Bad of_node_put() on /pciex@3fffe4000
CPU: 0 PID: 3040 Comm: bash Not tainted 3.18
From: Ryan Grimm
Commit 4beb5421babee1204757b877622830c6aa31be6d upstream.
Select defaults such that a PERST causes flash image reload. Select which
image based on what the card is set up to load.
CXL_VSEC_PERST_LOADS_IMAGE selects whether PERST assertion causes flash image
load.
CXL_VSEC_PER
Excerpts from Rasmus Villemoes's message of 2015-02-21 00:26:22 +1100:
> C99 says that a precision given as simply '.' with no following digits
> or * should be interpreted as 0. The kernel's printf implementation,
> however, treats this case as if the precision was omitted. C99 also
> says that if
On Fri, 2014-11-28 at 11:11 +1100, Michael Ellerman wrote:
> On Wed, 2014-26-11 at 04:10:04 UTC, Benjamin Herrenschmidt wrote:
> > This adds files in debugfs that can be used to retrieve the
> > OPALv3 firmware "live binary traces" which can then be parsed
> > using a userspace tool.
> >
> > Mostl
On Sat, 2015-21-02 at 19:00:50 UTC, Nishanth Aravamudan wrote:
> On 20.02.2015 [15:31:29 +1100], Michael Ellerman wrote:
> > On Thu, 2015-02-19 at 10:41 -0800, Nishanth Aravamudan wrote:
> > > After d905c5df9aef ("PPC: POWERNV: move iommu_add_device earlier"), the
> > > refcnt on the kobject backin
On Fri, Feb 20, 2015 at 05:19:17PM -0600, Bjorn Helgaas wrote:
>On Thu, Jan 15, 2015 at 10:27:58AM +0800, Wei Yang wrote:
>> From: Gavin Shan
>>
>> pci_dn is the extension of PCI device node and it's created from
>> device node. Unfortunately, VFs that are enabled dynamically by
>> PF's driver an
On Sun, 2015-02-22 at 23:13 +0100, Frederic Weisbecker wrote:
> Yes that should work. After all "self-IPI" is an oxymoron. One would
> expect an IPI to be triggered by an irq controller but if such
> operation isn't supported with the current CPU being both source and
> destination, anything trigge
Hi Ben,
2015-02-16 5:06 GMT+01:00 Benjamin Herrenschmidt :
> On Mon, 2015-02-16 at 11:08 +1100, Michael Ellerman wrote:
>> On Fri, 2015-02-13 at 13:38 -0600, Paul Clarke wrote:
>> > implement arch_irq_work_has_interrupt() for powerpc
>> >
>> > Commit 9b01f5bf3 introduced a dependency on "IRQ work
On Fri, Jan 30, 2015 at 4:46 PM, Sukadev Bhattiprolu
wrote:
> From: Cody P Schafer
>
> Signed-off-by: Cody P Schafer
> Signed-off-by: Sukadev Bhattiprolu
> ---
> Changelog[v6]
> Update Contact info to Linux on Power Developer list
>
> .../testing/sysfs-bus-event_source-devices-hv_24x7
We don't support real-mode areas now that 970 support is removed.
Remove the remaining details of rma from the code. Also rename
rma_setup_done to hpte_setup_done to better reflect the changes.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_host.h | 3 +--
arch/powerpc/kvm/boo
[PATCH v2 5/7] AES for PPC/SPE - ECB/CBC/CTR/XTS modes
The assembler block cipher module that controls the core
AES functions.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes-spe-modes.S
b/arch/powerpc/crypto/aes-spe-modes.S
new file mode 100644
index 000..ad48032
--
[PATCH v2 6/7] AES for PPC/SPE - glue code
Integrate the assembler modules into the kernel crypto
framework. Take care to avoid long intervals of disabled
preemption.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes_spe_glue.c
b/arch/powerpc/crypto/aes_spe_glue.c
new file
[PATCH v2 7/7] AES for PPC/SPE - kernel config
Integrate the module into the kernel configuration
v2 changes
- better explanation of use case in help text
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/Makefile b/arch/powerpc/crypto/Makefile
index a07e763..1698fb9 100644
--
[PATCH v2 4/7] AES for PPC/SPE - key handling
Key generation for big endian core routines.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes-spe-keys.S
b/arch/powerpc/crypto/aes-spe-keys.S
new file mode 100644
index 000..be8090f
--- /dev/null
+++ b/arch/powerpc/crypto/
[PATCH v2 2/7] AES for PPC/SPE - aes tables
4K AES tables for big endian. To reduce the possiblity of
timing attacks, the size has been cut to 8KB + 256 bytes
in contrast to 16KB in the generic implementation. That
is not perfect but at least a good tradeoff for CPU limited
router devices.
v2 ch
[PATCH v2 3/7] AES for PPC/SPE - assembler core
The assembler AES encryption and decryption core routines.
Implemented & optimized for big endian. Nevertheless they
work on little endian too.
For most efficient reuse in (higher level) block cipher
routines they are implemented as "fast" call mod
[PATCH v2 1/7] AES for PPC/SPE - register defines
Define some register aliases for better readability.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes-spe-regs.h
b/arch/powerpc/crypto/aes-spe-regs.h
new file mode 100644
index 000..30d217b
--- /dev/null
+++ b/arch/pow
[PATCH v2 0/7] AES for PPC/SPE
The following patches add support for 64bit accelerated AES
calculation on PPC processors with SPE instruction set. Besides
the AES core module it implements ECB/CBC/CTR/XTS as block
ciphers. The implementation takes care of the following
constraints:
- save SPE re
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