From: Wang Dongsheng
QIXIS System Logic FPGA support to manage system power. So we
through QIXIS to power off freescale SOC.
Signed-off-by: Wang Dongsheng
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index 1f309cc..e1a1eb5 100644
-
On Thu, Jan 29, 2015 at 08:21:53PM +1100, Alexey Kardashevskiy wrote:
> At the moment writing new TCE value to the IOMMU table fails with EBUSY
> if there is a valid entry already. However PAPR specification allows
> the guest to write new TCE value without clearing it first.
>
> Another problem t
Since commit cd1e65044d44 ("of/device: Don't register disabled
devices"), the disabled device will not be registered at all. So
we don't need to do the check again in the platform device driver.
And the check in the current code is useless even if we really
run into a disabled device. In this case
On Tue, Feb 03, 2015 at 06:19:26PM -0600, Bjorn Helgaas wrote:
>On Tue, Feb 03, 2015 at 03:01:43PM +0800, Wei Yang wrote:
>> The actual IOV BAR range is determined by the start address and the actual
>> size for vf_num VFs BAR. After shifting the IOV BAR, there would be a
>> chance the actual end a
> -Original Message-
> From: Emil Medve [mailto:emilian.me...@freescale.com]
> Sent: Wednesday, January 21, 2015 6:04 PM
> To: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
> mturque...@linaro.org; haoke...@gmail.com; Tang Yuantian-B29983
> Cc: Medve Emilian-EMMEDVE1
> Subject: [PATCH v
On Tue, 2015-02-03 at 19:05 -0600, Scott Wood wrote:
> On Wed, 2015-02-04 at 11:58 +1100, Michael Ellerman wrote:
> > On Tue, 2015-02-03 at 11:20 -0600, Scott Wood wrote:
> > > Highlights include 8xx optimizations, some more work on datapath device
> > > tree content, e300 machine check support, t1
On Wed, 2015-02-04 at 11:58 +1100, Michael Ellerman wrote:
> On Tue, 2015-02-03 at 11:20 -0600, Scott Wood wrote:
> > Highlights include 8xx optimizations, some more work on datapath device
> > tree content, e300 machine check support, t1040 corenet error reporting,
> > and various cleanups and fix
On Tue, 2015-02-03 at 11:20 -0600, Scott Wood wrote:
> Highlights include 8xx optimizations, some more work on datapath device
> tree content, e300 machine check support, t1040 corenet error reporting,
> and various cleanups and fixes.
>
> The following changes since commit 31494cf3532cfee0bf5c913
On Tue, 2015-02-03 at 08:46 +0100, Greg Kurz wrote:
> On Tue, 03 Feb 2015 13:47:35 +1100
> Michael Ellerman wrote:
>
> > On Thu, 2015-01-29 at 19:03 +0100, Greg Kurz wrote:
> > > On Wed, 17 Dec 2014 10:40:46 +0100
> > > Greg Kurz wrote:
> > > > Hi,
> > > >
> > > > This series addresses remarks
On Tue, Feb 03, 2015 at 03:01:43PM +0800, Wei Yang wrote:
> The actual IOV BAR range is determined by the start address and the actual
> size for vf_num VFs BAR. After shifting the IOV BAR, there would be a
> chance the actual end address exceed the limit and overlap with other
> devices.
>
> This
From: Emil Medve
Date: Sun, 1 Feb 2015 15:58:31 -0600
> From: Shruti Kanetkar
>
> The device tree binding(s) document has fallen out of sync with the
> driver code. Update the list of supported devices to reflect current
> driver capabilities
>
> Change-Id: I440d8de2ee2d9c3b7b23e69b3da851cab18
From: Emil Medve
Probably we should have not upstreamed this in the first place
Signed-off-by: Emil Medve
---
arch/powerpc/boot/dts/b4860emu.dts | 223 -
1 file changed, 223 deletions(-)
delete mode 100644 arch/powerpc/boot/dts/b4860emu.dts
diff --git a/ar
Highlights include 8xx optimizations, some more work on datapath device
tree content, e300 machine check support, t1040 corenet error reporting,
and various cleanups and fixes.
The following changes since commit 31494cf3532cfee0bf5c913ac9962971aab7b1d4:
powerpc/powernv: Don't alloc IRQ map if n
On Tue, 2015-02-03 at 12:38 +0100, Christophe Leroy wrote:
> This patchset provides a further optimisation of TLB handling in the 8xx.
> Main changes are based on:
> - Using processor handling of PGD/PTE Validity bits instead of testing
> ourselves
> the entries validity
> - Aligning PGD address t
In powerpc32 architecture we have a function called cacheable_memcpy()
which does same thing as memcpy() but using dcbz/dcbt instructions for
an optimised copy (just like __copy_tofrom_user())
What seems strange is that it is almost nowhere used (only used in
drivers/net/ethernet/ibm/emac/core.c
On Tue, Feb 03, 2015 at 09:37:24AM +0800, Kevin Hao wrote:
> Add a stub for pci_device_to_OF_node() so drivers don't need to
> use #ifdef CONFIG_OF around calls to it.
>
> Signed-off-by: Kevin Hao
> Acked-by: Bjorn Helgaas
Applied to pci/misc for v3.20, thanks!
> ---
> Hi Bjorn,
>
> Here is t
On Mon, Feb 2, 2015 at 6:25 PM, Michael Ellerman wrote:
> On Mon, 2015-02-02 at 09:47 -0600, Bjorn Helgaas wrote:
>> On Sun, Feb 1, 2015 at 8:28 PM, Michael Ellerman wrote:
>> > On Sat, 2015-01-31 at 21:47 +0800, Kevin Hao wrote:
>> >> So we can avoid the ugly #ifdef in some drivers.
>> >>
>> >>
From: Markus Elfring
Date: Tue, 3 Feb 2015 14:34:10 +0100
The kfree() function tests whether its argument is NULL and then
returns immediately. Thus the test around the call is not needed.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
arch/powerpc
From: Markus Elfring
Date: Tue, 3 Feb 2015 13:55:53 +0100
The kfree() function tests whether its argument is NULL and then
returns immediately. Thus the test around the call is not needed.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
arch/powerpc
csum_tcpudp_magic() is only a few instructions, and does not modifies any other
register than the returned result. So it is not worth having it as a separate
function and suffer function branching and saving of volatile registers.
This patch makes it inline by use of the already existing csum_tcpud
The C version of csum_add() as defined in include/net/checksum.h gives the
following assembly:
0: 7c 04 1a 14 add r0,r4,r3
4: 7c 64 00 10 subfc r3,r4,r0
8: 7c 63 19 10 subfe r3,r3,r3
c: 7c 63 00 50 subfr3,r3,r0
include
On PPC_8xx, lwz has a 2 cycles latency, and branching also takes 2 cycles.
As the size of the header is minimum 5 words, we can unroll the loop for the
first words to reduce number of branching, and we can re-order the instructions
to limit loading latency.
Signed-off-by: Christophe Leroy
---
a
This patchset provides a few optimisations related to IP checksum functions.
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
---
arch/powerpc/include/asm/checksum.h | 28
arch/powerpc/lib/checksum_32.S | 16
2 files changed, 28 ins
We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/kernel/head_8xx.S | 9 -
1 file changed, 4 insertions(+), 5 de
CR only needs to be preserved when checking if we are handling a kernel address.
So we can preserve CR in a register:
- In ITLBMiss, check is done only when CONFIG_MODULES is defined. Otherwise we
don't need to do anything at all with CR.
- We use r10, then we reload SRR0/MD_EPN into r10 when CR is
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely
sufficient for most cases. However, kernel configuration allows to set TASK_SIZE
to another value, so the 8xx shall handle it.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change (but impacted by patch 07)
All accessed to PGD entries are done via 0(r11).
By using lower part of swapper_pg_dir as load index to r11, we can remove the
ori instruction.
Signed-off-by: Christophe Leroy
---
v2: fixed/added comments to explain what is the real content of M_TW
v3: no change
arch/powerpc/kernel/head_8xx.S
Having a macro will help keep clear code.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: Fixed the macro (missing -) and changed macro name to be more explicit
arch/powerpc/kernel/head_8xx.S | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/pow
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/kernel/head_8xx.S | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index a485ad7..a1571b3 100644
--- a/arch/powerpc/kernel/h
In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change (but impacted by patch 07)
arch/powerpc/kernel/head_8xx.S | 10 +++---
1 file changed, 7 insertions(+
Since commit 33fb845a6f01 ("powerpc/8xx: Don't use MD_TWC for walk"), MD_EPN and
MD_TWC are not writen anymore in FixupDAR so saving r3 has become useless.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/kernel/head_8xx.S | 6 --
1 file changed, 6 deletions(-)
When pages are not 4K, PGDIR table is allocated with kmalloc(). In order to
optimise TLB handlers, aligned memory is needed. kmalloc() doesn't provide
aligned memory blocks, so lets use a kmem_cache pool instead.
Signed-off-by: Christophe Leroy
---
v2: changed to apply cleanly to linux-next (due
Kernel MMU handling code handles validity of entries via _PMD_PRESENT which
corresponds to V bit in MD_TWC and MI_TWC. When the V bit is not set, MPC8xx
triggers TLBError exception. So we don't have to check that and branch ourself
to TLBError. We can set TLB entries with non present entries, remov
This patchset provides a further optimisation of TLB handling in the 8xx.
Main changes are based on:
- Using processor handling of PGD/PTE Validity bits instead of testing ourselves
the entries validity
- Aligning PGD address to allow direct bit manipulation
- Not saving registers like CR when not
L1 base address is now aligned so we can insert L1 index into r11 directly and
then preserve r10
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/kernel/head_8xx.S | 34 +++---
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git
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