> On Tue, Nov 25, 2014 at 12:43:25PM +0100, David Hildenbrand wrote:
> > Whenever we have pagefaults disabled, we have to use the atomic variants of
> > (set|get)_user and copy_(from|to)_user.
> >
> > Signed-off-by: David Hildenbrand
> > ---
> > arch/powerpc/sysdev/fsl_pci.c | 2 +-
> > 1 file c
Register a notifier for a OPAL message indicating that the machine
should prepare itself for a graceful power off.
OPAL will tell us if the power off is a reboot or shutdown, but for now
we perform the same orderly_poweroff action.
Signed-off-by: Joel Stanley
---
v2:
- combine the reboot and o
On Wed, 2015-07-01 at 04:43:07 UTC, Mahesh Salgaonkar wrote:
> From: Mahesh Salgaonkar
>
> commit id 9975f5e added new config variable CONFIG_KVM_BOOK3S_HV_POSSIBLE
> that helps to select the relevant code in the kernel when HV and PR
> bits are built as separate modules. As part of that commit,
On Thu, Jun 26, 2014 at 11:58:58AM +0300, Alexandru-Cezar Sardan wrote:
> When adding an event to the PMU with PERF_EF_START the STOPPED and UPTODATE
> flags need to be cleared in the hw.event status variable because they are
> preventing the update of the event count on overflow interrupt.
>
> Si
On 09/15/2014 02:22 PM, Preeti U Murthy wrote:
> On 09/15/2014 12:29 PM, Michael Ellerman wrote:
>> On Fri, 2014-09-12 at 16:31 +0530, Preeti U Murthy wrote:
>>> Today the procfs interface /proc/sys/kernel/powersave-nap is used to control
>>> entry into deep idle states beyond snooze. Check for the
> Von: Scott Wood [scottw...@freescale.com]
> Gesendet: Freitag, 30. Januar 2015 01:49
> An: Markus Stockhausen
> Cc: Michael Ellerman; linuxppc-dev@lists.ozlabs.org; Herbert Xu
> Betreff: Re: AW: SPE & Interrupt context (was how to make use of SPE
> instructions)
>
> On Wed, 2015-01-28 at 05:00
On Wed, Nov 12, 2014 at 11:40:13AM +0800, Zhao Qiang wrote:
> ls1 has qe and ls1 has arm cpu.
> move qe from arch/powerpc to drivers/soc/fsl
> to adapt to powerpc and arm
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v2:
> - move code to driver/soc
> Changes for v3:
> - change dri
On Mon, Dec 08, 2014 at 04:29:20AM -0600, Emil Medve wrote:
> From: Kumar Gala
>
> Change-Id: If643fa5ba0a903aef8f5056a2c90ebecc995b760
> Signed-off-by: Kumar Gala
> Signed-off-by: Geoff Thorpe
> Signed-off-by: Hai-Ying Wang
> Signed-off-by: Chunhe Lan
> Signed-off-by: Poonam Aggrwal
> [Emil
On Tue, Nov 25, 2014 at 12:43:25PM +0100, David Hildenbrand wrote:
> Whenever we have pagefaults disabled, we have to use the atomic variants of
> (set|get)_user and copy_(from|to)_user.
>
> Signed-off-by: David Hildenbrand
> ---
> arch/powerpc/sysdev/fsl_pci.c | 2 +-
> 1 file changed, 1 insert
On Tue, 2015-01-20 at 02:51 -0600, Liberman Igal-B31950 wrote:
>
>
> Regaeds,
> Igal Liberman.
>
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Tuesday, January 20, 2015 9:44 AM
> > To: Liberman Igal-B31950
> > Cc: linuxppc-dev@lists.ozlabs.org; Medve Emilian-EMMEDVE1
> > S
On Wed, 2015-14-01 at 13:51:57 UTC, Geert Uytterhoeven wrote:
> of_find_node_by_name() calls of_node_put() on its "from" parameter,
> which must not be done on "master", as it's still in use, and will be
> released manually later. This may cause a zero kref refcount.
> Use of_get_child_by_name() i
On Wed, 2015-28-01 at 02:13:06 UTC, Preeti U Murthy wrote:
> The device tree now exposes the residency values for different idle states.
> Read
> these values instead of calculating residency from the latency values. The
> values
> exposed in the DT are validated for optimal power efficiency. How
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, January 30, 2015 10:44 AM
> To: Xie Shaohui-B21989
> Cc: linuxppc-dev@lists.ozlabs.org; devicet...@vger.kernel.org; Medve
> Emilian-EMMEDVE1
> Subject: Re: [PATCH][v4] power/fsl: add MDIO dt binding for FMan
>
> On Thu, 2015-01
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, January 30, 2015 8:54 AM
> To: shh@gmail.com
> Cc: linuxppc-dev@lists.ozlabs.org; devicet...@vger.kernel.org; Medve
> Emilian-EMMEDVE1; Xie Shaohui-B21989
> Subject: Re: [PATCH][v4] power/fsl: add MDIO dt binding for FMan
>
On Thu, 2015-01-29 at 20:38 -0600, Xie Shaohui-B21989 wrote:
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Friday, January 30, 2015 8:54 AM
> > To: shh@gmail.com
> > Cc: linuxppc-dev@lists.ozlabs.org; devicet...@vger.kernel.org; Medve
> > Emilian-EMMEDVE1; Xie Shaohui-B21
On Wed, 2015-01-28 at 12:13 +0530, Naveen N. Rao wrote:
> On 2015/01/28 05:14PM, Michael Ellerman wrote:
> > On Wed, 2015-01-28 at 11:12 +0530, Naveen N. Rao wrote:
> > > On 2014/12/15 08:20PM, Naveen N Rao wrote:
> > > > This patchset fixes various issues with perf probe on powerpc across
> > > >
On Tue, 2014-10-06 at 07:32:10 UTC, Zhouyi Zhou wrote:
> NULL return of kzalloc_node should be handled
Yeah it should.
But just returning doesn't seem like it's going to end well. We end up with a
device that's not properly setup.
I think we need to rework that further so that either the error
On Thu, Jan 22, 2015 at 04:48:37AM -0600, Emil Medve wrote:
> From: Andy Fleming
>
> Change-Id: I4489db79957ad533f4ba3f04fe7d5bcb3288e981
> Signed-off-by: Andy Fleming
> Signed-off-by: Shaohui Xie
> Signed-off-by: Shruti Kanetkar
> ---
scott@snotra:~/fsl/git/linux/upstream$ ./scripts/checkpat
On Thu, Jan 22, 2015 at 04:48:37AM -0600, Emil Medve wrote:
> From: Andy Fleming
>
> Change-Id: I4489db79957ad533f4ba3f04fe7d5bcb3288e981
> Signed-off-by: Andy Fleming
> Signed-off-by: Shaohui Xie
> Signed-off-by: Shruti Kanetkar
> ---
These patches are missing your signoff. Everyone who pas
On Wed, Jan 28, 2015 at 10:58:42AM +1100, Benjamin Herrenschmidt wrote:
>On Tue, 2015-01-27 at 16:58 -0600, Brian King wrote:
>> I'd argue we are our own worst enemy here really. The new user is EEH
>> code.
>> I don't see a huge reason that code would need to use this exact same
>> API.
>>
>> > I
On Thu, Jan 29, 2015 at 03:52:24PM +0800, Shengzhou Liu wrote:
> +/include/ "qoriq-i2c-0.dtsi"
> +/include/ "qoriq-i2c-1.dtsi"
t1023 has only three i2c controllers -- where do you disable the fourth?
> +/include/ "t1023si-post.dtsi"
> +
> +/ {
> + aliases {
> + vga = &display;
>
On Thu, Jan 29, 2015 at 03:52:24PM +0800, Shengzhou Liu wrote:
> + corenet-cf@18000 {
> + compatible = "fsl,corenet2-cf";
While the damage has already been done by the t1040 device tree, this is
not 100% compatible with what's on t4240. I'm not sure if it's worth
doing anything ab
On Wed, 2015-01-28 at 19:54 +0800, shh@gmail.com wrote:
> +- interrupts
> + Usage: required
> + Value type:
> + Definition: Event interrupt of external MDIO controller.
What if this MDIO controller is not "external"? Should Usage say
"required for external
On Wed, 2015-01-28 at 05:00 +, Markus Stockhausen wrote:
> > > Von: Scott Wood [scottw...@freescale.com]
> > > Gesendet: Mittwoch, 28. Januar 2015 05:21
> > > An: Markus Stockhausen
> > > Cc: Michael Ellerman; linuxppc-dev@lists.ozlabs.org; Herbert Xu
> > > Betreff: Re: SPE & Interrupt context
Register a notifier for a OPAL message indicating that the machine
should prepare itself for a graceful power off.
OPAL will tell us if the power off is a reboot or shutdown, but for now
we perform the same orderly_poweroff action.
Signed-off-by: Joel Stanley
---
arch/powerpc/include/asm/opal.h
On Wed, 17 Dec 2014 10:40:46 +0100
Greg Kurz wrote:
> Hi,
>
> This series addresses remarks from Ben and Michael (see individual patches).
> The most notable changes are:
> - the parsing code being pull out into a separate file in patch 3/4. This
> allows to write userland tests like the one be
On 28 January 2015 at 20:52, Martin Hicks wrote:
>
> The reset code was pushed into the esdhc-imx driver, but missed being
> pushed into the FSL OF driver at the same time. The commit that broke
> the OF ESDHC driver was 0718e59ae259f7c48155b4e852d8b0632d59028e
>
> Signed-off-by: Martin Hicks
M
T1023RDB is a Freescale Reference Design Board that hosts T1023 SoC.
T1023RDB board Overview
---
- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- SDRAM
The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Accel
Add support for Freescale T1024/T1023 QorIQ Development System Board.
T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.
T1024QDS board Overview
---
- T1024 SoC integrating two 64-bit e5500 cores up
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC.
T1024RDB board Overview
---
- Processor: T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- DDR: 64-bit 4GB DDR3L UDIMM with ECC and interleaving support
- Ethernet: two 10M/100M/1Gbps RGMII ports
This moves page pinning (get_user_pages_fast()/put_page()) code out of
the platform IOMMU code and puts it to VFIO IOMMU driver where it belongs
to as the platform code does not deal with page pinning.
This makes iommu_take_ownership()/iommu_release_ownership() deal with
the IOMMU table bitmap onl
This adds create/remove window ioctls to create and remove DMA windows.
This changes VFIO_IOMMU_SPAPR_TCE_GET_INFO handler to return additional
information such as a number of supported windows and maximum number
levels of TCE tables.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include
iommu_take_ownership/iommu_release_ownership used to be used to mark
bits in iommu_table::it_map. Since the IOMMU tables are recreated for
VFIO, it_map is always NULL.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/iommu.h | 2 -
arch/powerpc/kernel/iommu.c | 96 -
Signed-off-by: Alexey Kardashevskiy
---
drivers/vfio/vfio_iommu_spapr_tce.c | 243 +++-
1 file changed, 155 insertions(+), 88 deletions(-)
diff --git a/drivers/vfio/vfio_iommu_spapr_tce.c
b/drivers/vfio/vfio_iommu_spapr_tce.c
index d0987ae..8bcafb7 100644
--- a/d
This extends powerpc_iommu_ops by a set of callbacks to support dynamic
DMA windows management.
query() returns IOMMU capabilities such as default DMA window address and
supported number of DMA windows and TCE table levels.
create_table() creates a TCE table with specific parameters. For now
it r
This changes few functions to receive a powerpc_iommu pointer
rather than PE as they are going to be a part of upcoming
powerpc_iommu_ops callback set.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 13 -
1 file changed, 8 insertions(+), 5 deletio
The iommu_free_table helper release memory it is using (the TCE table and
@it_map) and release the iommu_table struct as well. We might not want
the very last step as we store iommu_table in parent structures.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/iommu.h | 1 +
arch/
This adds multi-level TCE tables support to pnv_pci_ioda2_create_table()
and pnv_pci_ioda2_free_table() callbacks.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/iommu.h | 4 +
arch/powerpc/platforms/powernv/pci-ioda.c | 125 +++---
arch/power
Modern IBM POWERPC systems support multiple (currently two) TCE tables
per IOMMU group (a.k.a. PE). This adds a powerpc_iommu container
for TCE tables. Right now just one table is supported.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/iommu.h| 18 ++--
arch/powe
This adds a iommu_table_ops struct and puts pointer to it into
the iommu_table struct. This moves tce_build/tce_free/tce_get/tce_flush
callbacks from ppc_md to the new struct where they really belong to.
This adds the requirement for @it_ops to be initialized before calling
iommu_init_table() to m
This is a part of moving TCE table allocation into an iommu_ops
callback to support multiple IOMMU groups per one VFIO container.
This is a mechanical patch.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 88 +++
1 file changed, 6
This is a part of moving DMA window programming to an iommu_ops
callback.
This is a mechanical patch.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 84 ---
1 file changed, 56 insertions(+), 28 deletions(-)
diff --git a/arch/powe
This moves iommu_table creation to the beginning. This is a mechanical
patch.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 31 +--
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci
The existing implementation accounts the whole DMA window in
the locked_vm counter which is going to be even worse with multiple
containers and huge DMA windows.
This introduces 2 ioctls to register/unregister DMA memory which
receive user space address and size of the memory region which
needs to
This adds missing locks in iommu_take_ownership()/
iommu_release_ownership().
This marks all pages busy in iommu_table::it_map in order to catch
errors if there is an attempt to use this table while ownership over it
is taken.
This only clears TCE content if there is no page marked busy in it_map
The previous patch introduced iommu_table_ops::exchange() callback
which effectively disabled VFIO on pseries. This implements exchange()
for pseries/lpar so VFIO can work in nested guests.
Since exchange() callback returns an old TCE, it has to call H_GET_TCE
for every TCE being put to the table
At the moment the iommu_table struct has a set_bypass() which enables/
disables DMA bypass on IODA2 PHB. This is exposed to POWERPC IOMMU code
which calls this callback when external IOMMU users such as VFIO are
about to get over a PHB.
The set_bypass() callback is not really an iommu_table functi
This replaces multiple calls of kzalloc_node() with a new
iommu_table_alloc() helper. Right now it calls kzalloc_node() but
later it will be modified to allocate a powerpc_iommu struct with
a single iommu_table in it.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/iommu.h
At the moment writing new TCE value to the IOMMU table fails with EBUSY
if there is a valid entry already. However PAPR specification allows
the guest to write new TCE value without clearing it first.
Another problem this patch is addressing is the use of pool locks for
external IOMMU users such a
The pnv_pci_ioda_tce_invalidate() helper invalidates TCE cache. It is
supposed to be called on IODA1/2 and not called on p5ioc2. It receives
start and end host addresses of TCE table. This approach makes it possible
to get pnv_pci_ioda_tce_invalidate() unintentionally called on p5ioc2.
Another issu
Normally a bitmap from the iommu_table is used to track what TCE entry
is in use. Since we are going to use iommu_table without its locks and
do xchg() instead, it becomes essential not to put bits which are not
implied in the direction flag.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David
This enables PAPR defined feature called Dynamic DMA windows (DDW).
Each Partitionable Endpoint (IOMMU group) has a separate DMA window on
a PCI bus where devices are allows to perform DMA. By default there is
1 or 2GB window allocated at the host boot time and these windows are
used when an IOMM
There moves locked pages accounting to helpers.
Later they will be reused for Dynamic DMA windows (DDW).
While we are here, update the comment explaining why RLIMIT_MEMLOCK
might be required to be bigger than the guest RAM. This also prints
pid of the current process in pr_warn/pr_debug.
Signed-o
This checks that the TCE table page size is not bigger that the size of
a page we just pinned and going to put its physical address to the table.
Otherwise the hardware gets unwanted access to physical memory between
the end of the actual page and the end of the aligned up TCE page.
Since compoun
This makes use of the it_page_size from the iommu_table struct
as page size can differ.
This replaces missing IOMMU_PAGE_SHIFT macro in commented debug code
as recently introduced IOMMU_PAGE_XXX macros do not include
IOMMU_PAGE_SHIFT.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
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