On Tue, 2015-01-20 at 02:51 -0600, Liberman Igal-B31950 wrote:
>
>
> Regaeds,
> Igal Liberman.
>
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Tuesday, January 20, 2015 9:44 AM
> > To: Liberman Igal-B31950
> > Cc: linuxppc-dev@lists.ozlabs.org; Medve Emilian-EMMEDVE1
> > Subject: Re: [PATCH] powerpc/dts: Update platform PLL node
> >
> > On Mon, 2015-01-12 at 08:00 +0200, Igal.Liberman wrote:
> > > From: Igal Liberman <igal.liber...@freescale.com>
> > >
> > > Signed-off-by: Igal Liberman <igal.liber...@freescale.com>
> > > Change-Id: I92d020651237041d3767aa35e9345439714f9831
> > > ---
> > > arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 6 ++++--
> > > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > Please explain this more. Was it just wrong before? Is this for a new
> > chip? If
> > the latter, what effect does this have on existing chips?
> >
>
> It wasn't wrong, however it was missing some clocking options which
> might be used by some hardware accelerators available in T/B devices.
> I need this options for FMan, however it might be used for other
> accelerators too.
If the PLL had a div3 option and it wasn't described by the PLL node,
the node was wrong.
Do all chips that use this file have a div3?
> > > diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
> > > b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
> > > index 48e0b6e..7e1f074 100644
> > > --- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
> > > +++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
> > > @@ -49,14 +49,16 @@ global-utilities@e1000 {
> > > reg = <0x800 0x4>;
> > > compatible = "fsl,qoriq-core-pll-2.0";
> > > clocks = <&sysclk>;
> > > - clock-output-names = "pll0", "pll0-div2", "pll0-div4";
> > > + clock-output-names = "pll0", "pll0-div2", "pll0-div3",
> > > + "pll0-div4";
> >
> > You're changing the meaning of existing clock index 2.
> >
>
> Yes, however this platform PLL is a new work which is not yet used, so we
> aren't breaking any functionality.
No, it's the core PLL node which is already in use. However, it looks
like the driver already interprets clock index 2 differently based on
whether clock index 3 exists. None of this is mentioned in the binding
document...
-Scott
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