Hi,
In this patch series we use winkle for offlined cores. I successfully
tested the working of this with subcore functionality.
Test scenario was as follows:
1. Set SMT mode to 1, Set subores-per-core to 1
2. Offline a core, in this case cpu 32 (sending it to winkle)
3. Set subcores-per-core to
On Wed, 2014-09-17 at 22:33 +0200, christophe leroy wrote:
> Le 17/09/2014 18:40, Scott Wood a écrit :
> > On Wed, 2014-09-17 at 18:36 +0200, Christophe Leroy wrote:
> >> This patchset:
> >> 1) provides several MMU TLB handling optimisation on MPC8xx.
> >> 2) adds support of 16k pages on MPC8xx.
>
Le 17/09/2014 18:40, Scott Wood a écrit :
On Wed, 2014-09-17 at 18:36 +0200, Christophe Leroy wrote:
This patchset:
1) provides several MMU TLB handling optimisation on MPC8xx.
2) adds support of 16k pages on MPC8xx.
All changes have been successfully tested on a custom board equipped with MPC8
On 09/17/2014 02:07 AM, Michael Ellerman wrote:
>
> On Mon, 2014-09-15 at 15:33 -0500, Nathan Fontenot wrote:
>> This patch adds the ability to do memory hotplug remove in the kernel.
>>
>> Currently the hotplug add/remove of memory is handled by the drmgr
>> command. The drmgr command performs th
On Wed, Sep 17, 2014 at 04:37:30PM +0100, Kumar Gala wrote:
>
> On Sep 17, 2014, at 1:56 AM, Ganapatrao Kulkarni
> wrote:
>
> > From: Ganapatrao Kulkarni
> >
> > This patch adds property "nid" to memory node to provide the memory range to
> > numa node id mapping.
> >
> > Signed-off-by: Gana
On 09/17/2014 02:07 AM, Michael Ellerman wrote:
>
> On Mon, 2014-09-15 at 15:32 -0500, Nathan Fontenot wrote:
>> This patch adds the ability to do memory hotplug adding in the kernel.
>>
>> Currently the hotplug add/remove of memory is handled by the drmgr
>> command. The drmgr command performs th
On 09/17/2014 02:07 AM, Michael Ellerman wrote:
>
> On Mon, 2014-09-15 at 15:31 -0500, Nathan Fontenot wrote:
>> For pseries system the kernel will be notified of hotplug requests in
>> the form of rtas hotplug events.
>
> Can you flesh that design out a bit for me, I don't entirely get how it's
On Wed, Sep 17, 2014 at 06:25:10PM +0100, Sudeep Holla wrote:
> Hi Greg,
>
> On 03/09/14 18:00, Sudeep Holla wrote:
> >From: Sudeep Holla
> >
> >This patch adds initial support for providing processor cache information
> >to userspace through sysfs interface. This is based on already existing
> >
From: Cody P Schafer
CC: Sukadev Bhattiprolu
CC: Haren Myneni
CC: Cody P Schafer
Signed-off-by: Cody P Schafer
---
.../testing/sysfs-bus-event_source-devices-hv_24x7 | 22
1 file changed, 22 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-d
From: Cody P Schafer
Changelog[v6]:
- [Sukadev Bhattiprolu]: Update documentation of perf-list and
perf-record; Added documentation for perf-stat.
CC: Haren Myneni
CC: Cody P Schafer
Signed-off-by: Cody P Schafer
Signed-off-by: Sukadev Bhattiprolu
---
tools/perf/Documentat
From: Cody P Schafer
Event parameters are a basic way for partial events to be specified in
sysfs with per-event names given to the fields that need to be filled in
when using a particular event.
It is intended for supporting cases where the single 'cpu' parameter is
insufficient. For example, P
From: Cody P Schafer
This adds (in req-gen/) a framework for defining gpci counter requests.
It uses macro magic similar to ftrace.
Also convert the existing hv-gpci request structures and enum values to
use the new framework (and adjust old users of the structs and enum
values to cope with chan
From: Cody P Schafer
Add the remaining gpci requests that contain counters suitable for use
by perf. Omit those that don't contain any counters (but note their
ommision).
CC: Sukadev Bhattiprolu
CC: Haren Myneni
CC: Cody P Schafer
Signed-off-by: Cody P Schafer
---
arch/powerpc/perf/hv-gpci-
From: Cody P Schafer
Helper for constructing static struct perf_pmu_events_attr s.
CC: Sukadev Bhattiprolu
CC: Haren Myneni
CC: Cody P Schafer
Signed-off-by: Cody P Schafer
---
include/linux/perf_event.h |7 +++
1 file changed, 7 insertions(+)
diff --git a/include/linux/perf_event.
From: Cody P Schafer
Retrieves and parses the 24x7 catalog on POWER systems that supply it
(right now, only POWER 8). Events are exposed via sysfs in the standard
fashion, and are all parameterized.
Catalog is (at the moment) only parsed on boot. It needs re-parsing
when a some hypervisor events
From: Cody P Schafer
(struct perf_pmu_events_attr) is defined in include/linux/perf_event.h,
but the only "show" for it is in x86 and contains x86 specific stuff.
Make a generic one for those of us who are just using the event_str.
CC: Sukadev Bhattiprolu
CC: Haren Myneni
CC: Cody P Schafer
From: Cody P Schafer
Enable event specification like:
pmu/event_name,param1=0x1,param2=0x4/
Assuming that
/sys/bus/event_source/devices/pmu/events/event_name
Contains something like
param2=foo,bar=1,param1=baz
Changelog[v6]:
[Jiri Olsa] If the sysfs event fil
From: Cody P Schafer
This causes `perf list pmu` to show parameters for parameterized events
like follows:
pmu/event_name,param1=?,param2=?/ [Kernel PMU event]
An example:
hv_gpci/dispatch_timebase_by_processor_processor_time_in_timebase_cycles,phys_processor_idx=?/
[Kernel PMU event]
C
What this patchset does:
- the first patch (override sysfs in tools/perf via SYSFS_PATH) was sent out
previously, but needed a resend anyhow. Having it is useful for testing the
later changes to tools/perf.
- the second patch is a bugfix to the powerpc hv-24x7 code which was
previously
From: Cody P Schafer
Add documentation for the , .scale, and .unit
files in sysfs.
.scale and .unit were undocumented.
was previously documented only for specific powerpc pmu events.
CC: Sukadev Bhattiprolu
CC: Haren Myneni
CC: Cody P Schafer
Signed-off-by: Cody P Schafer
---
.../testing/
From: Cody P Schafer
Listing specific events doesn't actually help us at all here because:
- these events actually vary between different ppc processors, they
aren't garunteed to be present.
- the documentation of the (generic) file contents is now superceded by the
docs for arbitrary eve
catalog_read() implements the read interface for the sysfs file
/sys/bus/event_source/devices/hv_24x7/interface/catalog
It essentially takes a buffer, an offset and count as parameters
to the read() call. It makes a hypervisor call to read a specific
page from the catalog and copy the re
From: Cody P Schafer
Ian pointed out the use of __aligned(4096) caused rather large stack
consumption in single_24x7_request(), so use the kmem_cache
hv_page_cache (which we've already got set up for other allocations)
insead of allocating locally.
CC: Sukadev Bhattiprolu
CC: Haren Myneni
CC:
Miscellaenous fixes for perf and 24x7 counters in powerpc.
Patches 1,3,4 were submitted earlier as a part of the parametrized
events for 24x7 counters. But they are not directly related to the
parametrized events.
Patch 2 simplifies and fixes a bug in catalog_read() which causes the
catalog file
On Tue, Sep 16, 2014 at 10:13:16AM +0800, Shengjiu Wang wrote:
> Check if ipg clock is in clock-names property, then we can move the
> ipg clock enable and disable operation to startup and shutdown, that
> is only enable ipg clock when ssi is working and keep clock is disabled
> when ssi is in idle
On Tue, Sep 16, 2014 at 10:13:16AM +0800, Shengjiu Wang wrote:
> Check if ipg clock is in clock-names property, then we can move the
> ipg clock enable and disable operation to startup and shutdown, that
> is only enable ipg clock when ssi is working and keep clock is disabled
> when ssi is in idle
Hi Greg,
On 03/09/14 18:00, Sudeep Holla wrote:
From: Sudeep Holla
This patch adds initial support for providing processor cache information
to userspace through sysfs interface. This is based on already existing
implementations(x86, ia64, s390 and powerpc) and hence the interface is
intended
On 09/17/2014 02:07 AM, Michael Ellerman wrote:
>
> On Mon, 2014-09-15 at 15:30 -0500, Nathan Fontenot wrote:
>> diff --git a/arch/powerpc/platforms/pseries/pseries.h
>> b/arch/powerpc/platforms/pseries/pseries.h
>> index 361add6..b94516b 100644
>> --- a/arch/powerpc/platforms/pseries/pseries.h
>
On 09/17/2014 02:06 AM, Michael Ellerman wrote:
>
> On Mon, 2014-09-15 at 15:29 -0500, Nathan Fontenot wrote:
>> diff --git a/arch/powerpc/include/asm/rtas.h
>> b/arch/powerpc/include/asm/rtas.h
>> index b390f55..a01879e 100644
>> --- a/arch/powerpc/include/asm/rtas.h
>> +++ b/arch/powerpc/includ
On Wed, 2014-09-17 at 18:36 +0200, Christophe Leroy wrote:
> This patchset:
> 1) provides several MMU TLB handling optimisation on MPC8xx.
> 2) adds support of 16k pages on MPC8xx.
> All changes have been successfully tested on a custom board equipped with
> MPC885
>
> Signed-off-by: Christophe L
As we are not using anymore DAR to save registers, it is now available for
saving the r3 register used for CPU6 ERRATA handling. Therefore we can
remove the major hack which was to use memory location 0 to save r3.
Signed-off-by: Christophe Leroy
---
Changes in v3:
- New
linux/arch/powerpc/ker
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro.
Then we don't have to worry about this address directly in the code.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 29 -
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm doesn't.
Commit 5efab4a02c89c252fb4cce097aafde5f8208dbfe was invalidating them in
arch/powerpc/mm/fault.c.
This patch does the invalidation earlier in order to free th
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit
during TLB loading is useless.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/a
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss
handler as they are saved again to the same place in ITLBError handler we are
jumping to.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |8 +-
No need to re-set this bit at each TLB miss. Let's set it in the PTE.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- Removed PPC405 related macro from PPC8xx specific code
- PTE_NONE_MASK doesn't need PAGE_ACCESSED in Linux 2.6
arch/powerpc/include/asm/pgtable-ppc3
This patch activates the handling of 16k pages on the MPC8xx.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/mmu-8xx.h |2 ++
arch/powerpc/kernel/head_8xx.S |4
3 files cha
r10 and r3 are only used inside FixupDAR function. So lets save them inside
that function only.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 27 +--
1 files changed, 13 insertions(+), 14 deletions(-)
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires
4k aligned tables, which is only the case with 4k pages.
Consequently, we have to calculate the level 1 table index by ourselves.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/
In DTLBError handler there is not need to restore r10, r11 and cr registers
after fixing DAR as they are saved again to the same place just after.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |4 ++--
1 files changed, 2 ins
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked
to the page size and will vary when we change the page size. Lets define a const
for it in order to have it at only one place.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/pow
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions
and avoid the branching.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/
For PAGE size related operations, use PAGE size consts in order to be able to
use different page size in the futur.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 30 ++
1 files changed, 18 inserti
MD_TWC can only be used properly with 4k pages.
So lets calculate level 2 table index by ourselves.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- No need to save r11 in cr, we can do without modifying r11 in DataStoreTLBMiss
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 28 +
DataAccess exception is never generated by MPC8xx so do the job directly where
it is used to avoid an unnecessary branching.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- arch/powerpc/mm/fault.c uses the vector number, so make sure it understands
the new ones.
arc
By XORing the upper part of the instruction code, we get a value that can
directly be verified with the second test and we can remove the first test.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |6 ++
1 files changed,
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not
handled here anymore. So we fix the comment.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |8 ++--
1 files changed, 2 insertions(+), 6 deletio
This patchset:
1) provides several MMU TLB handling optimisation on MPC8xx.
2) adds support of 16k pages on MPC8xx.
All changes have been successfully tested on a custom board equipped with MPC885
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
---
Changes in v2:
- Patch number 10 r
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore
after FixupDAR. There is therefore no need to set it up with the value of DAR.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |7 +++
1 files
SCRATCH0 and SCRATCH1 are only used in Exceptions prologs where no other
exception can happen. There is therefore no need to preserve them accross
TLB handlers, we can use them there as in other exceptions. One of the
advantages is that they do not suffer CPU6 errata unlike M_TW register.
Signed-o
Exception InstructionAccess does not exist on MPC8xx. No need to branch there
from somewhere else.
Handling can be done directly in InstructionTLBError Exception.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- arch/powerpc/mm/fault.c uses the vector number, so make
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a
scratch register just like SPRG0 and SPRG1. So Declare it as such and fix
the comment which is not valid anymore since that commit.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/po
On Sep 17, 2014, at 1:56 AM, Ganapatrao Kulkarni
wrote:
> From: Ganapatrao Kulkarni
>
> This patch adds property "nid" to memory node to provide the memory range to
> numa node id mapping.
>
> Signed-off-by: Ganapatrao Kulkarni
>
> —
Adding the PPC guys as they’ve been doing NUMA on IBM P
Dear Alexander Gordeev,
On Sun, 7 Sep 2014 20:57:52 +0200, Alexander Gordeev wrote:
> Alexander Gordeev (3):
> patch 1 - PCI/MSI/PPC: Remove arch_msi_check_device()
> patch 2 - PCI/MSI/Armada-370-xp: Remove arch_msi_check_device()
> patch 3 - PCI/MSI: Remove arch_msi_check_device()
For th
I'm seeing a build warning in mm/nobootmem.c after removing
bootmem:
mm/nobootmem.c: In function '__free_pages_memory':
include/linux/kernel.h:713:17: warning: comparison of distinct pointer types
lacks a cast [enabled by default]
(void) (&_min1 == &_min2); \
^
mm/nobootmem.c:
We did part of sparse initialisation in setup_arch and part in
initmem_init. Put them together.
Signed-off-by: Anton Blanchard
Tested-by: Emil Medve
---
arch/powerpc/kernel/setup_64.c | 1 -
arch/powerpc/mm/mem.c | 1 +
arch/powerpc/mm/numa.c | 2 ++
3 files changed, 3 insertio
Lots of places included bootmem.h even when not using bootmem.
Signed-off-by: Anton Blanchard
Tested-by: Emil Medve
---
arch/powerpc/kernel/crash_dump.c | 1 -
arch/powerpc/kernel/irq.c | 1 -
arch/powerpc/kernel/pci_64.c | 1 -
arch/powerpc/
Now bootmem is gone from powerpc we can remove comments mentioning it.
Signed-off-by: Anton Blanchard
Tested-by: Emil Medve
---
arch/powerpc/kernel/prom.c | 5 +
arch/powerpc/kernel/rtas.c | 4 ++--
arch/powerpc/kvm/book3s_hv_builtin.c | 2 +-
arch/powerpc/mm/hugetlbpage
At the moment we transition from the memblock alloctor to the bootmem
allocator. Gitting rid of the bootmem allocator removes a bunch of
complicated code (most of which I owe the dubious honour of being
responsible for writing).
Signed-off-by: Anton Blanchard
Tested-by: Emil Medve
---
arch/powe
Hi Emil,
> While building corenet64_smp I get this:
>
> > ../arch/powerpc/mm/pgtable_64.c: In function 'early_alloc_pgtable':
> > ../arch/powerpc/mm/pgtable_64.c:77:95: error: 'MAX_DMA_ADDRESS'
> > undeclared (first use in this
> > function) ../arch/powerpc/mm/pgtable_64.c:77:95: note: each
> >
From: Igal Liberman
The Frame Manager (FMan) combines the Ethernet network interfaces with packet
distribution logic to provide intelligent distribution and queuing decisions
for incoming traffic at line rate.
This binding document describes Freescale's Frame Manager hardware attributes
that are
Hello Anton,
On 09/17/2014 12:58 AM, Anton Blanchard wrote:
> Lots of places included bootmem.h even when not using bootmem.
>
> Signed-off-by: Anton Blanchard
> ---
> arch/powerpc/kernel/crash_dump.c | 1 -
> arch/powerpc/kernel/irq.c | 1 -
> arch/powerpc/k
On Mon, 2014-09-15 at 15:33 -0500, Nathan Fontenot wrote:
> This patch adds the ability to do memory hotplug remove in the kernel.
>
> Currently the hotplug add/remove of memory is handled by the drmgr
> command. The drmgr command performs the add/remove by performing
> some work in user-space an
On Mon, 2014-09-15 at 15:32 -0500, Nathan Fontenot wrote:
> This patch adds the ability to do memory hotplug adding in the kernel.
>
> Currently the hotplug add/remove of memory is handled by the drmgr
> command. The drmgr command performs the add/remove by performing
> some work in user-space an
On Mon, 2014-09-15 at 15:31 -0500, Nathan Fontenot wrote:
> For pseries system the kernel will be notified of hotplug requests in
> the form of rtas hotplug events.
Can you flesh that design out a bit for me, I don't entirely get how it's going
to work.
The kernel gets the rtas hotplug events (
Instead of passing in the stack address of the link register
to be modified, just pass in the old value and return the
new value and rely on ftrace_graph_caller to do the
modification.
This removes the exception handling around the stack update -
it isn't needed and we weren't consistent about it.
mod_return_to_handler is the same as return_to_handler, except
it handles the change of the TOC (r2). Add this into
return_to_handler and remove mod_return_to_handler.
Signed-off-by: Anton Blanchard
---
arch/powerpc/kernel/entry_64.S | 24 +---
arch/powerpc/kernel/ftrace.c
We added -mno-sched-epilog in commit 7563dc645853 (powerpc:
Work around gcc's -fno-omit-frame-pointer bug).
We shouldn't apply -fno-omit-frame-pointer on powerpc any more (it's
protected by CONFIG_FRAME_POINTER and CONFIG_SCHED_OMIT_FRAME_POINTER).
It's also an undocumented gcc option, so lets re
On Mon, 2014-09-15 at 15:30 -0500, Nathan Fontenot wrote:
> diff --git a/arch/powerpc/platforms/pseries/pseries.h
> b/arch/powerpc/platforms/pseries/pseries.h
> index 361add6..b94516b 100644
> --- a/arch/powerpc/platforms/pseries/pseries.h
> +++ b/arch/powerpc/platforms/pseries/pseries.h
> @@ -59
On Mon, 2014-09-15 at 15:29 -0500, Nathan Fontenot wrote:
> diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
> index b390f55..a01879e 100644
> --- a/arch/powerpc/include/asm/rtas.h
> +++ b/arch/powerpc/include/asm/rtas.h
> @@ -273,6 +273,7 @@ inline uint32_t rtas_ext_
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