On 04.07.14 06:34, Madhavan Srinivasan wrote:
On Thursday 03 July 2014 05:21 PM, Alexander Graf wrote:
On 01.07.14 10:41, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation
Some Freescale boards like T1040RDB have on board CPLD connected on
the IFC bus. Add binding for this in board.txt file
Signed-off-by: Priyanka Jain
---
Changes for v2:
convert board name to lower-case based on Scott's suggestions
.../devicetree/bindings/powerpc/fsl/board.txt | 19 +
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, July 03, 2014 11:38 PM
> To: Jain Priyanka-B32167
> Cc: devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH] devicetree/binding/powerpc/fsl: Add binding for CPLD
>
> On Thu, 2014-07-03 at 15:39 +
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, July 04, 2014 3:40 AM
> To: Jain Priyanka-B32167
> Cc: devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; linux-
> s...@vger.kernel.org; linux-...@lists.infradead.org
> Subject: Re: [PATCH] devicetree/bindings: Add bin
On Thu, 2014-07-03 at 15:42 +0930, Joel Stanley wrote:
> On POWER8 when switching to a KVM guest we set bits in MMCR2 to freeze
> the PMU counters. Aside from on boot they are then never reset,
> resulting in stuck perf counters for any user in the guest or host.
Cc: sta...@vger.kernel.org
Fixes:
On Thu, 2014-07-03 at 15:42 +0930, Joel Stanley wrote:
> Instead of separate bits for every POWER8 PMU feature, have a single one
> for v2.07 of the architecture.
>
> This saves us adding a MMCR2 define for a future patch.
Cc: sta...@vger.kernel.org
Acked-by: Michael Ellerman
cheers
_
On Thu, 2014-07-03 at 15:42 +0930, Joel Stanley wrote:
> These two registers are already saved in the block above. Aside from
> being unnecessary, by the time we get down to the second save location
> r8 no longer contains MMCR2, so we are clobbering the saved value with
> PMC5.
MMCR2 primarily co
The POWER8 processor has a Micro Partition Prefetch Engine, which is
a fancy way of saying "has way to store and load contents of L2 or
L2+MRU way of L3 cache". We initiate the storing of the log (list of
addresses) using the logmpp instruction and start restore by writing
to a SPR.
The logmpp ins
On Fri, 2014-07-04 at 00:35 +0200, Alexander Graf wrote:
> On 04.07.14 00:31, Scott Wood wrote:
> > On Thu, 2014-07-03 at 17:15 -0500, Scott Wood wrote:
> >> On Thu, 2014-07-03 at 10:25 -0500, Caraman Mihai Claudiu-B02008 wrote:
> -Original Message-
> From: Alexander Graf [mailto:
On Mon, 2014-06-30 at 18:34 +0300, Mihai Caraman wrote:
> Add KVM Book3E AltiVec support. KVM Book3E FPU support gracefully reuse host
> infrastructure so follow the same approach for AltiVec.
>
> Signed-off-by: Mihai Caraman
> ---
> v2:
> - integrate Paul's FP/VMX/VSX changes
>
> arch/powerpc
On 04.07.14 01:00, Scott Wood wrote:
On Fri, 2014-07-04 at 00:35 +0200, Alexander Graf wrote:
On 04.07.14 00:31, Scott Wood wrote:
On Thu, 2014-07-03 at 17:15 -0500, Scott Wood wrote:
On Thu, 2014-07-03 at 10:25 -0500, Caraman Mihai Claudiu-B02008 wrote:
-Original Message-
From: Alex
On Thu, 2014-07-03 at 16:47 -0600, Bjorn Helgaas wrote:
> On Thu, Jun 19, 2014 at 05:22:44PM +1000, Gavin Shan wrote:
> > Commit d92a208d086 ("powerpc/pci: Mask linkDown on resetting PCI bus")
> > implemented same logic (resetting PCI secondary bus by bridge's config
> > register PCI_BRIDGE_CTL_BUS
On Thu, 2014-07-03 at 17:15 -0500, Scott Wood wrote:
> On Thu, 2014-07-03 at 10:25 -0500, Caraman Mihai Claudiu-B02008 wrote:
> > > -Original Message-
> > > From: Alexander Graf [mailto:ag...@suse.de]
> > > Sent: Thursday, July 03, 2014 3:21 PM
> > > To: Caraman Mihai Claudiu-B02008; kvm-..
On Thu, Jun 19, 2014 at 05:22:44PM +1000, Gavin Shan wrote:
> Commit d92a208d086 ("powerpc/pci: Mask linkDown on resetting PCI bus")
> implemented same logic (resetting PCI secondary bus by bridge's config
> register PCI_BRIDGE_CTL_BUS_RESET) in PCI core and arch-dependent
> code. In order to avoid
On 04.07.14 00:31, Scott Wood wrote:
On Thu, 2014-07-03 at 17:15 -0500, Scott Wood wrote:
On Thu, 2014-07-03 at 10:25 -0500, Caraman Mihai Claudiu-B02008 wrote:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Thursday, July 03, 2014 3:21 PM
To: Caraman Mihai Claudi
On 04.07.14 00:15, Scott Wood wrote:
On Thu, 2014-07-03 at 10:25 -0500, Caraman Mihai Claudiu-B02008 wrote:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Thursday, July 03, 2014 3:21 PM
To: Caraman Mihai Claudiu-B02008; kvm-...@vger.kernel.org
Cc: k...@vger.kernel
On Thu, 2014-07-03 at 10:25 -0500, Caraman Mihai Claudiu-B02008 wrote:
> > -Original Message-
> > From: Alexander Graf [mailto:ag...@suse.de]
> > Sent: Thursday, July 03, 2014 3:21 PM
> > To: Caraman Mihai Claudiu-B02008; kvm-...@vger.kernel.org
> > Cc: k...@vger.kernel.org; linuxppc-dev@li
On Thu, 2014-07-03 at 15:42 +0530, Priyanka Jain wrote:
> -Micron n25q512a memory is supported by m25p80 driver.
> Add compatible field required to support n25q512a in m25p80.txt
> -Add micron to the vendor-prefixes.txt file
>
> Signed-off-by: Priyanka Jain
> ---
> Documentation/devicetree/bind
On Thu, 2014-07-03 at 15:39 +0530, Priyanka Jain wrote:
> Some Freescale boards like T1040RDB have on board CPLD connected on
> the IFC bus. Add binding for this in board.txt file
>
> Signed-off-by: Priyanka Jain
> ---
> .../devicetree/bindings/powerpc/fsl/board.txt | 19 +
Am 03.07.2014 um 18:18 schrieb "mihai.cara...@freescale.com"
:
>> -Original Message-
>> From: Alexander Graf [mailto:ag...@suse.de]
>> Sent: Thursday, July 03, 2014 4:37 PM
>> To: Caraman Mihai Claudiu-B02008; kvm-...@vger.kernel.org
>> Cc: k...@vger.kernel.org; linuxppc-dev@lists.ozlab
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, July 03, 2014 4:37 PM
> To: Caraman Mihai Claudiu-B02008; kvm-...@vger.kernel.org
> Cc: k...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 3/5 v4] KVM: PPC: Book3s: Remove kvmppc_read
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, July 03, 2014 3:34 PM
> To: Caraman Mihai Claudiu-B02008; kvm-...@vger.kernel.org
> Cc: k...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 5/6 v2] KVM: PPC: Book3E: Add ONE_REG AltiVe
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, July 03, 2014 3:32 PM
> To: Caraman Mihai Claudiu-B02008; kvm-...@vger.kernel.org
> Cc: k...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 4/6 v2] KVM: PPC: Book3E: Add AltiVec suppor
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, July 03, 2014 6:31 PM
> To: Caraman Mihai Claudiu-B02008; Wood Scott-B07421; kvm-
> p...@vger.kernel.org
> Cc: k...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 1/6 v2] KVM: PPC: Boo
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, July 03, 2014 3:29 PM
> To: Caraman Mihai Claudiu-B02008; kvm-...@vger.kernel.org
> Cc: k...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 3/6 v2] KVM: PPC: Book3E: Increase FPU lazin
On 03.07.14 17:25, mihai.cara...@freescale.com wrote:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Thursday, July 03, 2014 3:21 PM
To: Caraman Mihai Claudiu-B02008; kvm-...@vger.kernel.org
Cc: k...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, July 03, 2014 3:21 PM
> To: Caraman Mihai Claudiu-B02008; kvm-...@vger.kernel.org
> Cc: k...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 1/6 v2] KVM: PPC: Book3E: Use common defines
Enable E.PT for vcpus with MMU MAV 2.0 to support Hardware Page Tablewalk (HTW)
in guests.
Signed-off-by: Mihai Caraman
---
arch/powerpc/kvm/e500_mmu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
index b775e6a
KVM Book3E support for Hardware Page Tablewalk enabled guests.
Mihai Caraman (4):
powerpc/booke64: Add LRAT next and max entries to tlb_core_data
structure
KVM: PPC: Book3E: Handle LRAT error exception
KVM: PPC: e500: TLB emulation for IND entries
KVM: PPC: e500mc: Advertise E.PT to su
Handle LRAT error exception with support for lrat mapping and invalidation.
Signed-off-by: Mihai Caraman
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/include/asm/kvm_ppc.h| 2 +
arch/powerpc/include/asm/mmu-book3e.h | 3 +
arch/powerpc/include/asm/reg_booke.h | 13 ++
Handle indirect entries (IND) in TLB emulation code. Translation size of IND
entries differ from the size of referred Page Tables (Linux guests now use IND
of 2MB for 4KB PTs) and this require careful tweak of the existing logic.
TLB search emulation requires additional search in HW TLB0 (since th
LRAT (Logical to Real Address Translation) is shared between hw threads.
Add LRAT next and max entries to tlb_core_data structure and initialize them.
Signed-off-by: Mihai Caraman
---
arch/powerpc/include/asm/mmu-book3e.h | 7 +++
arch/powerpc/include/asm/reg_booke.h | 1 +
arch/powerpc/mm/
On 28.06.14 00:49, Mihai Caraman wrote:
On book3e, KVM uses load external pid (lwepx) dedicated instruction to read
guest last instruction on the exit path. lwepx exceptions (DTLB_MISS, DSI
and LRAT), generated by loading a guest address, needs to be handled by KVM.
These exceptions are generate
On 28.06.14 00:49, Mihai Caraman wrote:
On book3e, guest last instruction is read on the exit path using load
external pid (lwepx) dedicated instruction. This load operation may fail
due to TLB eviction and execute-but-not-read entries.
This patch lay down the path for an alternative solution t
On 28.06.14 00:49, Mihai Caraman wrote:
In the context of replacing kvmppc_ld() function calls with a version of
kvmppc_get_last_inst() which allow to fail, Alex Graf suggested this:
"If we get EMULATE_AGAIN, we just have to make sure we go back into the guest.
No need to inject an ISI into th
On 30.06.14 17:34, Mihai Caraman wrote:
Add ONE_REG support for AltiVec on Book3E.
Signed-off-by: Mihai Caraman
Any chance we can handle these in generic code?
Alex
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On 30.06.14 17:34, Mihai Caraman wrote:
Add KVM Book3E AltiVec support. KVM Book3E FPU support gracefully reuse host
infrastructure so follow the same approach for AltiVec.
Signed-off-by: Mihai Caraman
Same comment here - I fail to see how we refetch Altivec state after a
context switch.
On 30.06.14 17:34, Mihai Caraman wrote:
Increase FPU laziness by calling kvmppc_load_guest_fp() just before
returning to guest instead of each sched in. Without this improvement
an interrupt may also claim floting point corrupting guest state.
How do you handle context switching with this patc
On 30.06.14 17:34, Mihai Caraman wrote:
SPE/FP/AltiVec interrupts share the same numbers. Refactor SPE/FP exit handling
to accommodate AltiVec later on the same flow. Add kvmppc_supports_spe() to
detect
suport for the unit at runtime since it can be configured in the kernel but not
featured on
On 30.06.14 17:34, Mihai Caraman wrote:
Use common BOOKE_IRQPRIO and BOOKE_INTERRUPT defines for SPE/FP/AltiVec
which share the same interrupt numbers.
Signed-off-by: Mihai Caraman
---
v2:
- remove outdated definitions
arch/powerpc/include/asm/kvm_asm.h| 8
arch/powerpc/kvm
On 30.06.14 20:18, Scott Wood wrote:
On Mon, 2014-06-30 at 15:54 +0300, Mihai Caraman wrote:
Tlb search operation used for victim hint relies on the default tlb set by the
host. When hardware tablewalk support is enabled in the host, the default tlb is
TLB1 which leads KVM to evict the bolted e
On 30.06.14 20:20, Scott Wood wrote:
On Mon, 2014-06-30 at 15:55 +0300, Mihai Caraman wrote:
For FSL e6500 core the kernel uses power management SPR register (PWRMGTCR0)
to enable idle power down for cores and devices by setting up the idle count
period at boot time. With the host already contr
On 01.07.14 10:41, Madhavan Srinivasan wrote:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the illegal instruction
and accordingly we return to Host or Gu
Some Freescale boards like T1040RDB have on board CPLD connected on
the IFC bus. Add binding for this in board.txt file
Signed-off-by: Priyanka Jain
---
.../devicetree/bindings/powerpc/fsl/board.txt | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/
On 07/03/2014 11:22 AM, Zhao Qiang wrote:
> when flexcan is not physically linked, command 'cantest' will
> trigger an err_irq, add err_irq handler for it.
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v2:
> - use a space instead of tab
> - use flexcan_poll_state instead of print
-Micron n25q512a memory is supported by m25p80 driver.
Add compatible field required to support n25q512a in m25p80.txt
-Add micron to the vendor-prefixes.txt file
Signed-off-by: Priyanka Jain
---
Documentation/devicetree/bindings/mtd/m25p80.txt |1 +
.../devicetree/bindings/vendor-prefixe
when flexcan is not physically linked, command 'cantest' will
trigger an err_irq, add err_irq handler for it.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- use a space instead of tab
- use flexcan_poll_state instead of print
Changes for v3:
- return IRQ_HANDLED if err is
From: Bjorn Helgaas
> On Tue, Jun 10, 2014 at 03:10:30PM +0200, Alexander Gordeev wrote:
> > There are PCI devices that require a particular value written
> > to the Multiple Message Enable (MME) register while aligned on
> > power of 2 boundary value of actually used MSI vectors 'nvec'
> > is a le
On 07/03/2014 04:23 AM, Zhao Qiang wrote:
> when flexcan is not physically linked, command 'cantest' will
> trigger an err_irq, add err_irq handler for it.
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v2:
> - use a space instead of tab
> - use flexcan_poll_state instead of print
Knowing how long we spend in firmware calls is an important part of
minimising OS jitter.
This patch adds tracepoints to each OPAL call. If tracepoints are
enabled we branch out to a common routine that calls an entry and exit
tracepoint.
This allows us to write tools that monitor the frequency a
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