On 03.02.2014 [21:38:36 -0600], Christoph Lameter wrote:
> On Mon, 3 Feb 2014, Nishanth Aravamudan wrote:
>
> > So what's the status of this patch? Christoph, do you think this is fine
> > as it is?
>
> Certainly enabling CONFIG_MEMORYLESS_NODES is the right thing to do and I
> already acked the
On Mon, 3 Feb 2014, Nishanth Aravamudan wrote:
> So what's the status of this patch? Christoph, do you think this is fine
> as it is?
Certainly enabling CONFIG_MEMORYLESS_NODES is the right thing to do and I
already acked the patch.
___
Linuxppc-dev ma
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, February 04, 2014 4:52 AM
> To: Kushwaha Prabhakar-B32579
> Cc: linuxppc-dev@lists.ozlabs.org; Arnd Bergmann
> Subject: Re: [PATCH 1/2][v8] driver/memory:Move Freescale IFC driver to a
> common
> driver
>
> On Fri, 2014-01-
On Fri, Jan 31, 2014 at 03:24:58PM -0200, Thadeu Lima de Souza Cascardo wrote:
>On Fri, Jan 31, 2014 at 08:46:11AM +0800, Gavin Shan wrote:
>> On Thu, Jan 30, 2014 at 11:00:48AM -0200, Thadeu Lima de Souza Cascardo
>> wrote:
>> >Commit f5c57710dd62dd06f176934a8b4b8accbf00f9f8 ("powerpc/eeh: Use
>>
On Fri, 2014-01-31 at 15:09 +0530, Prabhakar Kushwaha wrote:
> Freescale IFC controller has been used for mpc8xxx. It will be used
> for ARM-based SoC as well. This patch moves the driver to driver/memory
> and fix the header file includes.
>
> Also remove module_platform_driver() and instead
On 28.01.2014 [10:29:47 -0800], Nishanth Aravamudan wrote:
> On 27.01.2014 [14:58:05 +0900], Joonsoo Kim wrote:
> > On Fri, Jan 24, 2014 at 05:10:42PM -0800, Nishanth Aravamudan wrote:
> > > On 24.01.2014 [16:25:58 -0800], David Rientjes wrote:
> > > > On Fri, 24 Jan 2014, Nishanth Aravamudan wrote
On 01/31/2014 09:58 PM, Michael Ellerman wrote:
On Thu, 2014-16-01 at 23:53:50 UTC, Cody P Schafer wrote:
"H_GetPerformanceCounterInfo" (refered to as hv_gpci or just gpci from
here on) is an interface to retrieve specific performance counters and
other data from the hypervisor. All outputs have
On 01/31/2014 09:58 PM, Michael Ellerman wrote:
On Thu, 2014-16-01 at 23:53:49 UTC, Cody P Schafer wrote:
Signed-off-by: Cody P Schafer
---
arch/powerpc/include/asm/hvcall.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/hvcall.h
b/arch/pow
On 01/31/2014 09:58 PM, Michael Ellerman wrote:
On Thu, 2014-16-01 at 23:53:47 UTC, Cody P Schafer wrote:
Add PMU_RANGE_ATTR() and PMU_RANGE_RESV() (for reserved areas) which
generate functions to extract the relevent bits from
event->attr.config{,1,2} for use by sw-like pmus where the
'config{,
On 01/31/2014 09:58 PM, Michael Ellerman wrote:
On Thu, 2014-16-01 at 23:53:52 UTC, Cody P Schafer wrote:
This provides a basic link between perf and hv_gpci. Notably, it does
not yet support transactions and does not list any events (they can
still be manually composed).
What are the plans fo
Currently some errors/info to be reported use
printk and the rest pr_fmt(). This patch
makes the complete error logging uniform.
Signed-off-by: Deepthi Dharwar
---
arch/powerpc/platforms/powernv/opal-elog.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch
Correct spell error in opal-elog.c
Signed-off-by: Deepthi Dharwar
---
arch/powerpc/platforms/powernv/opal-elog.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/powernv/opal-elog.c
b/arch/powerpc/platforms/powernv/opal-elog.c
index 0a03b60..13874b1
This patch series defines generic interfaces for error logging to
push down critical errors from powernv platform to FSP.
Also, it contains few minor fixes for the exisiting error logging
framework that retrieves error logs from FSP.
Changes from V3:
* Change memory allocation to GFP_ATOMIC, to g
This patch provides error logging interfaces to report critical
powernv error logs to FSP.
All the required information to dump the error is collected
at POWERNV level through error log interfaces
and then pushed on to FSP.
Signed-off-by: Deepthi Dharwar
---
arch/powerpc/include/asm/opal.h
Hi Michael,
On Fri, Jan 31, 2014 at 03:18:30PM -0800, David Hawkins wrote:
1. Peripheral board DMA (board-to-board)
2. Peripheral board DMA to host memory.
3. Host (root complex) DMA.
As far as "verification" of your custom peripheral board FPGA IP is
concerned, if I was a customer, and you ha
On Tue, Jan 28, 2014 at 05:47:03PM +0530, Aneesh Kumar K.V wrote:
> This patch fix the below crash
>
> NIP [c004cee4] .__hash_page_thp+0x2a4/0x440
> LR [c00439ac] .hash_page+0x18c/0x5e0
> ...
> Call Trace:
> [c00736103c40] [1b00] 0x1b00(unreliable)
> [437908
From: Michael Moese
> On Mon, Feb 03, 2014 at 10:17:43AM +, David Laight wrote:
>
> > We achieved about twice that using the PEX dma controller.
>
> > Your 3MB/s for single word transfers is similar to what we saw.
> > Cycle times that make an ISA bus look fast.
>
> Indeed, this is a really
On Mon, Feb 03, 2014 at 10:17:43AM +, David Laight wrote:
> We achieved about twice that using the PEX dma controller.
> Your 3MB/s for single word transfers is similar to what we saw.
> Cycle times that make an ISA bus look fast.
Indeed, this is a really poor performance. I know we could ac
From: Michael Moese
> Thank you for your help - we might be satisfied with the achieved
> 18 MB/s.
We achieved about twice that using the PEX dma controller.
I found the following comment I wrote:
/* Long transfer requests are cut into smaller DMA requests.
* Each PCIe request can contain a maxi
On Mon, Feb 03, 2014 at 08:16:49AM +0100, Michael Moese wrote:
> Allow for IO memory to be mapped cacheable for performing
> PCI read bursts.
>
> Signed-off-by: Michael Moese
> ---
> arch/powerpc/include/asm/io.h | 3 +++
> arch/powerpc/mm/pgtable_32.c | 8
> 2 files changed, 11 insert
On Fri, Jan 31, 2014 at 03:18:30PM -0800, David Hawkins wrote:
> 1. Peripheral board DMA (board-to-board)
> 2. Peripheral board DMA to host memory.
> 3. Host (root complex) DMA.
>
> As far as "verification" of your custom peripheral board FPGA IP is
> concerned, if I was a customer, and you had da
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