Re: [v3, 3/7] powerpc: enable the relocatable support for the fsl booke 32bit kernel

2014-01-03 Thread Kevin Hao
On Fri, Jan 03, 2014 at 06:49:09PM -0600, Scott Wood wrote: > On Fri, 2013-12-20 at 15:43 +0800, Kevin Hao wrote: > > On Wed, Dec 18, 2013 at 05:48:25PM -0600, Scott Wood wrote: > > > On Wed, Aug 07, 2013 at 09:18:31AM +0800, Kevin Hao wrote: > > > > This is based on the codes in the head_44x.S. Th

Re: [v3, 3/7] powerpc: enable the relocatable support for the fsl booke 32bit kernel

2014-01-03 Thread Scott Wood
On Fri, 2013-12-20 at 15:43 +0800, Kevin Hao wrote: > On Wed, Dec 18, 2013 at 05:48:25PM -0600, Scott Wood wrote: > > On Wed, Aug 07, 2013 at 09:18:31AM +0800, Kevin Hao wrote: > > > This is based on the codes in the head_44x.S. The difference is that > > > the init tlb size we used is 64M. With th

Re: [PATCH 3/4] powerpc/fsl-booke: Add support for T2080/T2081 SoC

2014-01-03 Thread Scott Wood
On Wed, 2013-12-25 at 18:06 +0800, Shengzhou Liu wrote: > +/* controller at 0x27 */ > +&pci3 { > + compatible = "fsl,t208x-pcie", "fsl,qoriq-pcie"; Don't use wildcards in compatible strings. > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > +

Re: [PATCH 01/12][v3] pci: fsl: derive the common PCI driver to drivers/pci/host

2014-01-03 Thread Scott Wood
On Mon, 2013-11-25 at 16:01 -0700, Bjorn Helgaas wrote: > On Wed, Oct 23, 2013 at 06:41:23PM +0800, Minghuan Lian wrote: > > The Freescale's Layerscape series processors will use ARM cores. > > The LS1's PCIe controllers is the same as T4240's. So it's better > > the PCIe controller driver can supp

Re: [03/12,v3] pci: fsl: add PCI indirect access support

2014-01-03 Thread Scott Wood
On Wed, Oct 23, 2013 at 06:41:25PM +0800, Minghuan Lian wrote: > The patch adds PCI indirect read/write functions. The main code > is ported from arch/powerpc/sysdev/indirect_pci.c. We use general > IO API iowrite32be/ioread32be instead of out_be32/in_be32, and > use structure fsl_Pci instead of Po

Re: [02/12,v3] pci: fsl: add structure fsl_pci

2014-01-03 Thread Scott Wood
On Wed, Oct 23, 2013 at 06:41:24PM +0800, Minghuan Lian wrote: > PowerPC uses structure pci_controller to describe PCI controller, > but ARM uses structure pci_sys_data. In order to support PowerPC > and ARM simultaneously, the patch adds a structure fsl_pci that > contains most of the members of t

Re: [11/12,v3] pci: fsl: update PCI EDAC driver

2014-01-03 Thread Scott Wood
On Wed, Oct 23, 2013 at 06:41:33PM +0800, Minghuan Lian wrote: > diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c > index 40d2e1d..4a03e1a 100644 > --- a/arch/powerpc/sysdev/fsl_pci.c > +++ b/arch/powerpc/sysdev/fsl_pci.c > @@ -236,6 +236,7 @@ void fsl_arch_pci_sys_remove(

P1020 implementation crashes with "Data Cache Parity Error" on board derived from Freescale P1020Wlan eval board.

2014-01-03 Thread John Clark
I have a problem when booting the linux kernel using two cores of the P1020 Freescale ppc implementation. I have found on the Freescale site one other person who has a similar problem and we both are using designed driver from the P1020Wlan 'eval' board. I would like to know if others have this

Re: [PATCH RFC v6 4/5] dma: mpc512x: register for device tree channel lookup

2014-01-03 Thread Alexander Popov
Hello Gerhard. Thanks for your review. 2013/12/26 Gerhard Sittig : > [ dropping devicetree, we're DMA specific here ] > > On Tue, Dec 24, 2013 at 16:06 +0400, Alexander Popov wrote: >> >> --- a/drivers/dma/mpc512x_dma.c >> +++ b/drivers/dma/mpc512x_dma.c >> [ ... ] >> @@ -950,6 +951,7 @@ static in

Re: [PATCH v2] mtd: m25p80: Add Power Management support

2014-01-03 Thread Brian Norris
On Thu, Dec 12, 2013 at 01:38:36PM +0800, Hou Zhiqiang wrote: > Add PM support using callback function suspend and resume in > .driver.pm of spi_driver. > > Signed-off-by: Hou Zhiqiang > --- > v2: > - Replace .driver.suspend and .driver.resume with .driver.pm > - Use CONFIG_PM_SLEEP instead of

Re: [PATCH] mtd: m25p80: Add Power Management support

2014-01-03 Thread Brian Norris
On Wed, Dec 11, 2013 at 04:19:30PM +0800, Hou Zhiqiang wrote: > Add PM support using callback function suspend and resume in .driver of > spi_driver. > > Signed-off-by: Hou Zhiqiang > --- > drivers/mtd/devices/m25p80.c | 37 + > 1 file changed, 37 insertions(+

Re: [PATCH v3 REPOST 2/4] i2c: i2c-ibm-iic: perform the transfer in the interrupt handler

2014-01-03 Thread Jean-Jacques Hiblot
2014/1/3 Wolfram Sang : > > Hi, > > thanks for the submission! You're welcome :) Thanks for reviewing this. > >> --- a/drivers/i2c/busses/i2c-ibm_iic.c >> +++ b/drivers/i2c/busses/i2c-ibm_iic.c >> @@ -58,6 +58,8 @@ static bool iic_force_fast; >> module_param(iic_force_fast, bool, 0); >> MODULE_P

Re: [PATCH v3 REPOST 3/4] i2c: i2c-ibm-iic: Implements transfer abortion

2014-01-03 Thread Jean-Jacques Hiblot
2014/1/3 Wolfram Sang : > On Fri, Dec 20, 2013 at 04:12:55PM +0100, jean-jacques hiblot wrote: >> From: jean-jacques hiblot >> >> Clean-up properly when a transfer fails for whatever reason. >> Cancel the transfer when the process is signaled. > > Please describe what you do a little. I wonder how

Re: [PATCH v3 REPOST 3/4] i2c: i2c-ibm-iic: Implements transfer abortion

2014-01-03 Thread Wolfram Sang
On Fri, Dec 20, 2013 at 04:12:55PM +0100, jean-jacques hiblot wrote: > From: jean-jacques hiblot > > Clean-up properly when a transfer fails for whatever reason. > Cancel the transfer when the process is signaled. Please describe what you do a little. I wonder how you can remove so much code whi

Re: [PATCH v3 REPOST 4/4] i2c: i2c-ibm-iic: Implements a polling mode

2014-01-03 Thread Wolfram Sang
On Fri, Dec 20, 2013 at 04:12:56PM +0100, jean-jacques hiblot wrote: > From: jean-jacques hiblot > > When no valid interrupt is defined for the controller, use polling to handle > the transfers. > The polling mode can also be forced with the "iic_force_poll" module > parameter. > > Signed-off-b

Re: [PATCH v3 REPOST 2/4] i2c: i2c-ibm-iic: perform the transfer in the interrupt handler

2014-01-03 Thread Wolfram Sang
Hi, thanks for the submission! > --- a/drivers/i2c/busses/i2c-ibm_iic.c > +++ b/drivers/i2c/busses/i2c-ibm_iic.c > @@ -58,6 +58,8 @@ static bool iic_force_fast; > module_param(iic_force_fast, bool, 0); > MODULE_PARM_DESC(iic_force_fast, "Force fast mode (400 kHz)"); > > +#define FIFO_FLUSH_T

RE: [PATCH] powerpc/fsl-booke: Use SPRN_SPRGn rather than mfsprg/mtsprg

2014-01-03 Thread dongsheng.w...@freescale.com
Looks good. I will test it as soon as possible. BTW, there is only SPRG3 need to save. 32bit: SPRG0-SPRG1, SPRG2-SPRG7, SPRG9 be use to deal with exception, those register not need to save.(SPRG8 not be used) Only SPRG3 be used to save current thread_info pointer. -Dongsheng > -Original Mes

[PATCH v2 1/2] powerpc/eeh: Add restore_config operation

2014-01-03 Thread Gavin Shan
After reset on the specific PE or PHB, we never configure AER correctly on PowerNV platform. We needn't care it on pSeries platform. The patch introduces additional EEH operation eeh_ops:: restore_config() so that we have chance to configure AER correctly for PowerNV platform. Signed-off-by: Gavin

[PATCH v2 2/2] powerpc/eeh: Reinit error reporting

2014-01-03 Thread Gavin Shan
The patch implements the EEH operation backend restore_config() for PowerNV platform. That relies on OPAL API opal_pci_reinit() where we reinitialize the error reporting properly after PE or PHB reset. The patch also extends opal_pci_reinit() to have one additional parameter to carry more informati

[PATCH] powerpc: add SATA_MV to ppc64_defconfig

2014-01-03 Thread Olof Johansson
This makes ppc64_defconfig bootable without initrd on pasemi systems, most of whom have MV SATA controllers. Some have SIL24, but that driver is already enabled. Signed-off-by: Olof Johansson --- arch/powerpc/configs/ppc64_defconfig |1 + 1 file changed, 1 insertion(+) diff --git a/arch/pow

Re: [PATCH] powerpc: Fix alignment of secondary cpu spin vars

2014-01-03 Thread Olof Johansson
On Thu, Jan 02, 2014 at 11:56:04PM -0800, Olof Johansson wrote: > This makes things interesting though. The BE/LE trampoline code > assumes at least 3 consecutive instructions. What was the reasoning > behind entering the kernel LE instead of keeping the old boot protocol > and just switching to L