Alexey Kardashevskiy writes:
> The previous scheme always put 0 as a parent slot#. However it is
> not always the case and QEMU's PCI bridge does not support putting
> device at slot#0 as it claims SHPC support for hotplug.
>
> This modifies the interrups map to let the linux guest resolve XICS
>
On Fri, 2013-09-13 at 15:10 +1000, Michael Ellerman wrote:
> Looks like you merged the version with #define DEBUG.
>
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/setup_64.c#n13
Yes, it looks like I've been distracted, I'll remove it again (or you
can
On Thu, Jul 25, 2013 at 12:49:57PM +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2013-07-25 at 12:12 +1000, Benjamin Herrenschmidt wrote:
> > --- a/arch/powerpc/kernel/setup_64.c
> > +++ b/arch/powerpc/kernel/setup_64.c
> > @@ -10,7 +10,7 @@
> > * 2 of the License, or (at your option) any l
Le 12/09/2013 20:44, Scott Wood a écrit :
On Thu, 2013-09-12 at 20:25 +0200, Christophe Leroy wrote:
This is a reorganisation of the setup of the TLB at kernel startup, in order
to handle the CONFIG_PIN_TLB case in accordance with chapter 8.10.3 of MPC866
and MPC885 reference manuals.
Signed-of
On Sep 13, 2013, at 12:42 AM, Kumar Gala wrote:
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Friday, September 13, 2013 12:42 AM
> To: Liu Shengzhou-B36685
> Cc: Zhao Qiang-B45475; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/p1010rdb:r
Do you have any solutions?
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, September 13, 2013 12:42 AM
To: Liu Shengzhou-B36685
Cc: Zhao Qiang-B45475; linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] powerpc/p1010rdb:remove interrupts of ethernet-phy
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, September 13, 2013 2:07 AM
> To: Wang Dongsheng-B40534
> Cc: Wood Scott-B07421; ga...@kernel.crashing.org; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH v3 4/4] powerpc/85xx: add sysfs for pw20 state and
> altivec id
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2013年9月12日 星期四 22:44
> To: Tang Yuantian-B29983
> Cc: Wood Scott-B07421; ga...@kernel.crashing.org; linuxppc-
> d...@lists.ozlabs.org; devicet...@vger.kernel.org; Li Yang-Leo-R58472
> Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the
On Thu, Sep 12, 2013 at 01:44:46PM -0500, Scott Wood wrote:
> On Thu, 2013-09-12 at 15:13 +0800, Kevin Hao wrote:
> > In the current kernel, the board files for p2041rdb, p3041ds, p4080ds,
> > p5020ds, p5040ds, t4240qds and b4qds are almost the same except the
> > machine name. So this introduces a
On Thursday 12 September 2013 11:13 PM, Luck, Tony wrote:
+ default:
+ cmpr = 60;
+ break;
+ }
Is this the right "default"? It may be a good choice for a backend with a
really
tiny buffer (1 ... 999). But less good for a (theoretical) backend with a
la
On Thu, 2013-09-12 at 15:13 +0800, Kevin Hao wrote:
> In the current kernel, the board files for p2041rdb, p3041ds, p4080ds,
> p5020ds, p5040ds, t4240qds and b4qds are almost the same except the
> machine name. So this introduces a cornet_generic machine to support
> all these boards to avoid the c
On Thu, 2013-09-12 at 20:25 +0200, Christophe Leroy wrote:
> This is a reorganisation of the setup of the TLB at kernel startup, in order
> to handle the CONFIG_PIN_TLB case in accordance with chapter 8.10.3 of MPC866
> and MPC885 reference manuals.
>
> Signed-off-by: Christophe Leroy
>
> diff -u
On Wed, 2013-09-11 at 22:48 -0500, Wang Dongsheng-B40534 wrote:
>
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Thursday, September 12, 2013 7:04 AM
> > To: Wang Dongsheng-B40534
> > Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org
> > Subject: Re: [PATCH v3 4/4]
This is a reorganisation of the setup of the TLB at kernel startup, in order
to handle the CONFIG_PIN_TLB case in accordance with chapter 8.10.3 of MPC866
and MPC885 reference manuals.
Signed-off-by: Christophe Leroy
diff -ur linux-3.11.org/arch/powerpc/kernel/head_8xx.S
linux-3.11/arch/powerpc
On Tue, Sep 03, 2013 at 10:01:50AM +0100, Hongbo Zhang wrote:
> On 09/02/2013 11:58 PM, Mark Rutland wrote:
> > Hi,
> >
> > On Fri, Aug 30, 2013 at 12:26:19PM +0100, hongbo.zh...@freescale.com wrote:
> >> From: Hongbo Zhang
> >>
> >> Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, t
+ default:
+ cmpr = 60;
+ break;
+ }
Is this the right "default"? It may be a good choice for a backend with a
really
tiny buffer (1 ... 999). But less good for a (theoretical) backend with a
larger
buffer (10001 ... infinity and beyond). Which are you
On Sep 12, 2013, at 1:54 AM, Liu Shengzhou-B36685 wrote:
>
>
>> -Original Message-
>> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
>> Sent: Wednesday, September 11, 2013 11:13 PM
>> To: Zhao Qiang-B45475
>> Cc: linuxppc-dev@lists.ozlabs.org; Liu Shengzhou-B36685
>> Subject: Re: [
efivars works fine with this v2 patch.
Tested-by: Seiji Aguchi
> -Original Message-
> From: Aruna Balakrishnaiah [mailto:ar...@linux.vnet.ibm.com]
> Sent: Thursday, September 12, 2013 2:51 AM
> To: linuxppc-...@ozlabs.org; tony.l...@intel.com; Seiji Aguchi;
> linux-ker...@vger.kernel.or
On Wed, 2013-09-11 at 20:31 -0500, Tang Yuantian-B29983 wrote:
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: 2013年9月12日 星期四 9:10
> > To: Tang Yuantian-B29983
> > Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
> > devicet...@vger.kernel.org; Li Yang-Leo-R58472
>
On 10.07.2013, at 02:25, Michael Neuling wrote:
> Alexander Graf wrote:
>
>>
>> On 09.07.2013, at 06:24, Michael Neuling wrote:
>>
>>> Alexander Graf wrote:
>>>
On 04.07.2013, at 08:15, Bharat Bhushan wrote:
> From: Bharat Bhushan
>
> This patchset moves the d
On 09/12/2013 04:03 AM, Srivatsa S. Bhat wrote:
> On 09/11/2013 09:37 PM, Jiang Liu wrote:
>> From: Jiang Liu
>>
>> Commit 9a46ad6d6df3b54 "smp: make smp_call_function_many() use logic
>> similar to smp_call_function_single()" has unified the way to handle
>> single and multiple cross-CPU function
The previous scheme always put 0 as a parent slot#. However it is
not always the case and QEMU's PCI bridge does not support putting
device at slot#0 as it claims SHPC support for hotplug.
This modifies the interrups map to let the linux guest resolve XICS
global interrupt number correctly.
Signe
The Freescale's Layerscape series processors will use the same PCI
controller but change cores from PowerPC to ARM. This patch is to
rework FSL PCI driver to support PowerPC and ARM simultaneously.
PowerPC uses structure pci_controller to describe PCI controller,
but arm uses structure hw_pci and p
The Freescale's Layerscape series processors will use ARM cores.
The LS1's PCIe controllers is the same as T4240's. So it's better
the PCIe controller driver can support PowerPC and ARM
simultaneously. This patch is for this purpose. It derives
the common functions from arch/powerpc/sysdev/fsl_pci.
Christophe Leroy wrote on 2013/09/11 17:50:28:
> From: Christophe Leroy
> To: Benjamin Herrenschmidt , Paul Mackerras
,
> Cc: linux-ker...@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Joakim
Tjernlund
> Date: 2013/09/11 18:43
> Subject: [PATCH] powerpc 8xx: Reverting commit
e0908085fc239
With the patch (powerpc/85xx: introduce cornet_generic machine) this
file becomes useless. Just delete it.
Signed-off-by: Kevin Hao
---
arch/powerpc/platforms/85xx/corenet_ds.h | 19 ---
1 file changed, 19 deletions(-)
delete mode 100644 arch/powerpc/platforms/85xx/corenet_ds.h
In the current kernel, the board files for p2041rdb, p3041ds, p4080ds,
p5020ds, p5040ds, t4240qds and b4qds are almost the same except the
machine name. So this introduces a cornet_generic machine to support
all these boards to avoid the code duplication.
Signed-off-by: Kevin Hao
---
This patch i
This patch series introduces a common machine to support p2041rdb, p3041ds,
p4080ds, p5020ds, p5040ds, t4240qds and b4qds to avoid the code duplication.
Boot test on p5020ds and p4080ds.
Kevin Hao (2):
powerpc/85xx: introduce cornet_generic machine
powerpc/85xx: remove the unneeded corenet_ds.
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