Add support for T104x board in board file t104x_qds.c, It is common for
both T1040 and T1042 as they share same QDS board.
T1040QDS board Overview
---
- SERDES Connections, 8 lanes supporting:
— PCI Express: supporting Gen 1 and Gen 2;
— SGMII
— QSGMII
The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking & telecommunications.
T1042 personality is a reduced personality of T1040 without Integrated 8
On 09/10/2013 10:08 PM, Vladimir Murzin wrote:
While cross-building for PPC64 I've got
Vladimir,
Below commit ID fixes this issue.
commit 256588fda10f2a712631f8a4e72641a66adebdb8
Author: Guenter Roeck
Date: Mon Sep 9 18:37:56 2013 -0700
powerpc: Export cpu_to_chip_id() to fix build er
On 09/11/2013 04:20 AM, Guenter Roeck wrote:
On Wed, Sep 11, 2013 at 08:02:49AM +1000, Benjamin Herrenschmidt wrote:
On Mon, 2013-09-09 at 16:55 -0700, Asai Thambi S P wrote:
On 09/08/2013 5:28 PM, Guenter Roeck wrote:
Hi all,
Guenter, Ben,
Sorry for the inconvenience. I never realized my
From: Wang Dongsheng
Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.
From: Wang Dongsheng
Add a sys interface to enable/diable pw20 state or altivec idle, and
control the wait entry time.
Enable/Disable interface:
0, disable. 1, enable.
/sys/devices/system/cpu/cpuX/pw20_state
/sys/devices/system/cpu/cpuX/altivec_idle
Set wait entry bit interface:
bit value range
From: Wang Dongsheng
E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec
idle patches.
Signed-off-by: Wang Dongsheng
---
*v3:
Add bit definitions for PWRMGTCR0.
arch/powerpc/include/asm/reg.h | 2 ++
arch/powerpc/include/asm/reg_booke.h | 9 +
2 files changed, 1
From: Wang Dongsheng
Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.
Signed
On Mon, Sep 09, 2013 at 03:20:58PM -0500, Tom Musta wrote:
> > > Isn't that code occasionally used with uprobes too nowadays ?
> >
> > Yes. I believe so.
>
> I'm going to back-pedal a little. I reread code and can connect
> single step code to kprobes but not necessarily to uprobes. So
> I am n
Since P1010RDB-PA and P1010RDB-PB boards use different external PHY
interrupt signals.
And actually the PHY interrupt is not used effectively with
corresponding interrupt handler.
So we can remove the interrupts node without side-effect to comply
with both P1010RDB-PA and P1010RDB-PB.
Signed-off-b
OK, will update per your suggestions.
Thanks,
Yuantian
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2013年9月11日 星期三 5:47
> To: Tang Yuantian-B29983
> Cc: Wood Scott-B07421; ga...@kernel.crashing.org;
> devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Mike Turquette
> S
Hi Linus !
Here are a handful of small powerpc fixes. A couple of section mismatches
(always worth fixing), a missing export of a new symbol causing build
failures of modules, a page fault deadlock fix (interestingly that
bug has been around for a LONG time, though it seems to be more easily
trigg
Now that we have the basic infrastructure setup to make use of the broadcast
framework, introduce the deep idle state in which cpus need to avail the
functionality provided by this infrastructure to wake them up at their
expired timer events. On ppc this deep idle state is called sleep.
In
On hotplug of the broadcast cpu, cancel the hrtimer queued to do
broadcast and nominate a new broadcast cpu to be the first cpu in the
broadcast mask which includes all the cpus that have notified the broadcast
framework about entering deep idle state.
Since the new broadcast cpu is one of the cpu
The broadcast framework in the kernel expects an external clock device which
will
continue functioning in deep idle states also. This ability is specified by
the "non-existence" of the feature C3STOP . This is the device that it relies
upon to wakup cpus in deep idle states whose local timers/cloc
From: Srivatsa S. Bhat
For scalability and performance reasons, we want the broadcast IPIs
to be handled as efficiently as possible. Fixed IPI messages
are one of the most efficient mechanisms available - they are faster
than the smp_call_function mechanism because the IPI handlers are fixed
and
On PowerPC, when CPUs enter deep idle states, their local timers get
switched off. The local timer is called the decrementer. An external clock
device needs to programmed to wake them up at their next timer event.
On PowerPC, we do not have an external device equivalent to HPET,
which is cu
On PowerPC, when CPUs enter deep idle states, their local timers get
switched off. An external clock device needs to programmed to wake them
up at their next timer event.
On PowerPC, we do not have an external device equivalent to HPET,
which is currently used on architectures like x86 unde
From: Srivatsa S. Bhat
The IPI handlers for both PPC_MSG_CALL_FUNC and PPC_MSG_CALL_FUNC_SINGLE map to
a common implementation - generic_smp_call_function_single_interrupt(). So, we
can consolidate them and save one of the IPI message slots, (which are precious,
since only 4 of those slots are av
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, September 11, 2013 7:33 AM
> To: Hu Mingkai-B21284
> Cc: linuxppc-...@ozlabs.org
> Subject: Re: [PATCH] powerpc/85xx: DTS - re-organize the SPI partitions
> property
>
> On Fri, 2013-09-06 at 16:05 +0800, Mingkai Hu wrote:
On Tue, 2013-09-10 at 18:47 -0500, Scott Wood wrote:
> No blank line before }
>
> > +CONFIG_CMDLINE_BOOL=y
> > +CONFIG_CMDLINE="console=ttyS0,9600 ip=dhcp root=/dev/nfs"
>
> I take it there's no way to pass a command line in from whatever loader
> this board uses... but you could put it in the d
Scott Wood wrote on 09/11/2013 09:47:27 AM:
> From: Scott Wood
> To: Stephen N Chivers/AUS/CSC@CSC
> Cc: Chris Proctor/AUS/CSC@CSC, ,
> ,
> Date: 09/11/2013 09:47 AM
> Subject: Re: [RFC PATCH v2 1/1] powerpc/embedded6xx: Add support for
> Motorola/Emerson MVME5100.
>
> On Thu, 2013-09-05 at 1
On Thu, 2013-09-05 at 15:51 +1000, Stephen Chivers wrote:
> Add support for the Motorola/Emerson MVME5100 Single Board Computer.
>
> The MVME5100 is a 6U form factor VME64 computer with:
>
> - A single MPC7410 or MPC750 CPU
> - A HAWK Processor Host Bridge (CPU to PCI) and
> M
On Wed, 2013-08-28 at 18:42 +0800, Minghuan Lian wrote:
> The Freescale's Layerscape series processors will use ARM cores.
> The LS1's PCIe controllers is the same as T4240's. So it's better
> the PCIe controller driver can support PowerPC and ARM
> simultaneously. This patch is for this purpose. I
On Tue, Sep 10, 2013 at 12:12:47PM -0500, Alexander Graf wrote:
>
> On 10.09.2013, at 05:21, Paul Mackerras wrote:
>
> > @@ -212,6 +212,7 @@ struct thread_struct {
> > #endif
> > #endif
> > struct thread_fp_state fp_state;
> > + struct thread_fp_state *fp_save_area;
>
> Why do you need t
On Tue, Sep 10, 2013 at 12:07:46PM -0500, Alexander Graf wrote:
>
> On 10.09.2013, at 05:20, Paul Mackerras wrote:
> > @@ -897,7 +897,7 @@ int fix_alignment(struct pt_regs *regs)
> > return -EFAULT;
> > }
> > } else if (flags & F) {
> > - data.
On Fri, 2013-09-06 at 16:05 +0800, Mingkai Hu wrote:
> Re-organize the SPI partitions and use the same SPI flash memory
> map for most of the platforms which have 16MB SPI flash mounted.
[snip]
> Based on 'next' branch on git tree:
> git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git
On Wed, Sep 11, 2013 at 08:02:49AM +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2013-09-09 at 16:55 -0700, Asai Thambi S P wrote:
> > On 09/08/2013 5:28 PM, Guenter Roeck wrote:
> > > Hi all,
> > >
> > > powerpc allmodconfig build on the latest upstream kernel results in:
> > >
> > > ERROR: ".cpu
On Wed, 2013-09-04 at 13:07 +1000, Jason Rennie wrote:
> But when I try building it with the latest buildroot (2013.08) and I
> configure the kernel (3.10.10) I get one of two things. If I don't
> include specific settings for physmap compat support (Device Drivers
> -> MTD Support -> Mapping drive
On Fri, 2013-09-06 at 08:43 -0700, York Sun wrote:
> B4860EMU is a emualtor target with minimum peripherals. It is based on
> B4860QDS and trimmed down most peripherals due to either not modeled or
> lack of board level connections. The main purpose of this minimum dts is
> to speed up booting on e
On Fri, 2013-09-06 at 08:43 -0700, York Sun wrote:
> Driver shouldn't request irq when irq = 0. It is returned from parsing
> device tree. 0 means no interrupt.
>
> Signed-off-by: York Sun
> Reviewed-by: Zang Tiefei-R61911
> Reviewed-by: Fleming Andrew-AFLEMING
> Tested-by: Fleming Andrew-AFLEM
On Fri, 2013-09-06 at 08:43 -0700, York Sun wrote:
> Extend err_addr to cover 64 bits for DDR errors.
>
> Signed-off-by: York Sun
> Reviewed-by: Fleming Andrew-AFLEMING
> Tested-by: Fleming Andrew-AFLEMING
> ---
> drivers/edac/mpc85xx_edac.c | 10 +++---
> drivers/edac/mpc85xx_edac.h |
On Mon, 2013-08-26 at 21:49 -0500, Tang Yuantian-B29983 wrote:
> > > > > + };
> > > > > + pll1: pll1@820 {
> > > > > + #clock-cells = <1>;
> > > > > + reg = <0x820>;
> > > > > + compatible = "fsl,core-pll-clock";
>
On Mon, 2013-09-09 at 16:55 -0700, Asai Thambi S P wrote:
> On 09/08/2013 5:28 PM, Guenter Roeck wrote:
> > Hi all,
> >
> > powerpc allmodconfig build on the latest upstream kernel results in:
> >
> > ERROR: ".cpu_to_chip_id" [drivers/block/mtip32xx/mtip32xx.ko] undefined!
> >
> > This is due to co
On Mon, 2013-09-09 at 18:37 -0700, Guenter Roeck wrote:
> powerpc allmodconfig build fails with:
>
> ERROR: ".cpu_to_chip_id" [drivers/block/mtip32xx/mtip32xx.ko] undefined!
>
> The problem was introduced with commit 15863ff3b (powerpc: Make chip-id
> information available to userspace).
Thanks,
On 10.09.2013, at 05:22, Paul Mackerras wrote:
> This modifies kvmppc_load_fp and kvmppc_save_fp to use the generic
> FP/VSX and VMX load/store functions instead of open-coding the
> FP/VSX/VMX load/store instructions. Since kvmppc_load/save_fp don't
> follow C calling conventions, we make them
On 10.09.2013, at 05:22, Paul Mackerras wrote:
> Now that we have the vcpu floating-point and vector state stored in
> the same type of struct as the main kernel uses, we can load that
> state directly from the vcpu struct instead of having extra copies
> to/from the thread_struct. Similarly, wh
While cross-building for PPC64 I've got
WARNING: drivers/video/built-in.o(.text+0x9f9ca): Section mismatch in
reference from the function .ps3fb_probe() to th e variable
.init.data:ps3fb_fix The function .ps3fb_probe() references the
variable __initdata ps3fb_fix. This is often because .ps3fb_pro
While cross-building for PPC64 I've got
WARNING: vmlinux.o(.text.unlikely+0x1ba): Section mismatch in
reference from the function .prom_rtas_call() to the variable
.init.data:dt_string_start The function .prom_rtas_call() references
the variable __initdata dt_string_start. This is often because
.
On 10.09.2013, at 05:21, Paul Mackerras wrote:
> This provides a facility which is intended for use by KVM, where the
> contents of the FP/VSX and VMX (Altivec) registers can be saved away
> to somewhere other than the thread_struct when kernel code wants to
> use floating point or VMX instructio
On 10.09.2013, at 05:20, Paul Mackerras wrote:
> This creates new 'thread_fp_state' and 'thread_vr_state' structures
> to store FP/VSX state (including FPSCR) and Altivec/VSX state
> (including VSCR), and uses them in the thread_struct. In the
> thread_fp_state, the FPRs and VSRs are represented
While cross-building for PPC64 I've got
ERROR: ".cpu_to_chip_id" [drivers/block/mtip32xx/mtip32xx.ko] undefined!
mtip32xx refer to topology_physical_package_id, which stands for
cpu_to_chip-id.
Make cpu_to_chip-id (and topology_physical_package_id) available for
external users.
Signed-off-by: V
On Tue, Sep 10, 2013 at 06:56:33PM +0200, Geert Uytterhoeven wrote:
> On Tue, Sep 10, 2013 at 6:46 PM, Vladimir Murzin wrote:
> > diff --git a/drivers/video/ps3fb.c b/drivers/video/ps3fb.c
> > index dbfe2c1..b269abd 100644
> > --- a/drivers/video/ps3fb.c
> > +++ b/drivers/video/ps3fb.c
> > @@ -952
On Tue, Sep 10, 2013 at 6:46 PM, Vladimir Murzin wrote:
> diff --git a/drivers/video/ps3fb.c b/drivers/video/ps3fb.c
> index dbfe2c1..b269abd 100644
> --- a/drivers/video/ps3fb.c
> +++ b/drivers/video/ps3fb.c
> @@ -952,7 +952,7 @@ static struct fb_ops ps3fb_ops = {
> .fb_compat_ioctl = ps3
On Sep 10, 2013, at 12:50 AM, Zhao Qiang wrote:
> Update phy node according to new P1010RDB-PB board.
>
> Signed-off-by: Shengzhou Liu
> Signed-off-by: Zhao Qiang
> ---
> arch/powerpc/boot/dts/p1010rdb.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
What about the old boards?
From: "Aneesh Kumar K.V"
stack_grow_into/14082 is trying to acquire lock:
(&mm->mmap_sem){++}, at: [] .might_fault+0x78/0xe0
but task is already holding lock:
(&mm->mmap_sem){++}, at: [] .do_page_fault+0x24c/0x910
other info that might help us debug this:
Possible unsafe lockin
On Tue, Sep 10, 2013 at 11:56:17AM +0100, Sudeep KarkadaNagesha wrote:
> > So we only need to change all clkdev registration to use "cpu0" as
> > dev_id intstead of "cpufreq-cpu0.0", something like below.
> >
> > And for imx, it should work even without the changes, because we have
> > device tree
On 10/09/13 03:44, Shawn Guo wrote:
> On Mon, Sep 09, 2013 at 04:24:18PM +0100, Sudeep KarkadaNagesha wrote:
>> Hi Shawn,
>>
>> Ok. But I am bit suspicious about devm_clk_get(cpu_dev, NULL).
>> I don't understand completely as how the clock are registered(whether
>> with dev_id or with connection_i
This modifies kvmppc_load_fp and kvmppc_save_fp to use the generic
FP/VSX and VMX load/store functions instead of open-coding the
FP/VSX/VMX load/store instructions. Since kvmppc_load/save_fp don't
follow C calling conventions, we make them private symbols within
book3s_hv_rmhandlers.S.
Signed-of
The load_up_fpu and load_up_altivec functions were never intended to
be called from C, and do things like modifying the MSR value in their
callers' stack frames, which are assumed to be interrupt frames. In
addition, on 32-bit Book S they require the MMU to be off.
This makes KVM use the new load
Now that we have the vcpu floating-point and vector state stored in
the same type of struct as the main kernel uses, we can load that
state directly from the vcpu struct instead of having extra copies
to/from the thread_struct. Similarly, when the guest state needs to
be saved, we can have it save
This provides a facility which is intended for use by KVM, where the
contents of the FP/VSX and VMX (Altivec) registers can be saved away
to somewhere other than the thread_struct when kernel code wants to
use floating point or VMX instructions. This is done by providing a
pointer in the thread_st
This creates new 'thread_fp_state' and 'thread_vr_state' structures
to store FP/VSX state (including FPSCR) and Altivec/VSX state
(including VSCR), and uses them in the thread_struct. In the
thread_fp_state, the FPRs and VSRs are represented as u64 rather
than double, since we rarely perform float
Currently on powerpc we store and access floating-point and vector
state in various ad-hoc arrays in places such as the thread_struct and
the kvm_vcpu_arch struct. This leads to code duplication for the code
that transfers this state between CPU registers and memory, and leads
to double-copying in
This uses struct thread_fp_state and struct thread_vr_state to store
the floating-point, VMX/Altivec and VSX state, rather than flat arrays.
This makes transferring the state to/from the thread_struct simpler
and allows us to unify the get/set_one_reg implementations for the
VSX registers.
Signed-
Hi Scott,
I discuss it with Liu Shengzhou again. I tried interrupts = <1 1 0 0> instead
of interrupts = <1 1> on P1025TWR, and it's OK. So I will add 2 cells for the
interrupts property. Thank you.
Best Regards
Xie Xiaobo
-Original Message-
From: Wood Scott-B07421
Sent: Friday, Septemb
Hi,
Just to be on the same page, are you using the Freescale Embedded
Hypervisor provided with the Freescale SDK or other embedded hypervisor?
Anyway, the question is not much related with the Linux kernel, so you
should probably redirect your question to Freescale support. You can
reach Fre
Hi,
Thank you very much. I will submit updated patch soon.
Best Regards
Xie Xiaobo
-Original Message-
From: Wood Scott-B07421
Sent: Friday, September 06, 2013 11:25 PM
To: Xie Xiaobo-R63061
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org
Subject: Re: [PATC
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