Due to different controller issue of PHY_CLK_VALID in ULPI mode,
in some cases, after set PHY_CLK_SEL, we should set
USB_CTRL_USB_EN before checking PHY_CLK_VALID, otherwise
PHY_CLK_VALID doesn't work.
But in other cases USB_CTRL_USB_EN is already set previously and
PHY_CLK_VALID is not valid once
On 04/24/2013 01:55 PM, Anatolij Gustschin wrote:
On Wed, 24 Apr 2013 10:55:10 +0800
Tiejun Chen wrote:
commit 761bbcb7, "usb: ehci-fsl: set INCR8 mode for system bus interface
on MPC512x", introduced to fix one MPC5121e (M36P) Errata by setting
INCR8 mode for system bus interface on MPC512x,
On 04/23/2013 08:42 AM, Chen Gang wrote:
need set '\0' for 'local_buffer'.
SPLPAR_MAXLENGTH is 1026, RTAS_DATA_BUF_SIZE is 4096. so the contents of
rtas_data_buf may truncated in memcpy.
if contents are really truncated.
the splpar_strlen is more than 1026. the next while loop checking will
On Mon, Apr 22, 2013 at 03:30:39PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
[snip]
> /*
> - * Use the top bit of the higher-level page table entries to indicate whether
> - * the entries we point to contain hugepages. This works because we know
> that
> - * the page tables li
Based on benh's proposal at
https://lists.ozlabs.org/pipermail/linuxppc-dev/2012-September/101237.html,
this change provides support for reserving memory from the
reserved-ranges node at the root of the device tree.
We just call memblock_reserve on these ranges for now.
Signed-off-by: Jeremy Kerr
This patch exploits pstore subsystem to read details of common partition
in NVRAM to a separate file in /dev/pstore. For instance, common partition
details will be stored in a file named [common-nvram-6].
Signed-off-by: Aruna Balakrishnaiah
Reviewed-by: Jim Keniston
---
arch/powerpc/platforms/p
This patch set exploits the pstore subsystem to read details of
of-config partition in NVRAM to a separate file in /dev/pstore.
For instance, of-config partition details will be stored in a
file named [of-nvram-5].
Signed-off-by: Aruna Balakrishnaiah
Reviewed-by: Jim Keniston
---
arch/powerpc/p
Introduce os_partition member in nvram_os_partition structure to identify
if the partition is an os partition or not. This will be useful to handle
non-os partitions of-config and common.
Signed-off-by: Aruna Balakrishnaiah
Reviewed-by: Jim Keniston
---
arch/powerpc/platforms/pseries/nvram.c |
This patch set exploits the pstore subsystem to read details of rtas partition
in NVRAM to a separate file in /dev/pstore. For instance, rtas details will be
stored in a file named [rtas-nvram-4].
Signed-off-by: Aruna Balakrishnaiah
Reviewed-by: Jim Keniston
---
arch/powerpc/platforms/pseries/n
IBM's p series machines provide persistent storage for LPARs through NVRAM.
NVRAM's lnx,oops-log partition is used to log oops messages.
Currently the kernel provides the contents of p-series NVRAM only as a
simple stream of bytes via /dev/nvram, which must be interpreted in user
space by the nvram
Introduce generic read function to read nvram partitions other than rtas.
nvram_read_error_log will be retained which is used to read rtas partition
from rtasd. nvram_read_partition is the generic read function to read from
any nvram partition.
Signed-off-by: Aruna Balakrishnaiah
Reviewed-by: Jim
Introduce version and timestamp information in the oops header.
oops_log_info (oops header) holds version (to distinguish between old
and new format oops header), length of the oops text
(compressed or uncompressed) and timestamp.
The version field will sit in the same place as the length in old
h
Removal of syslog prefix in the uncompressed oops text will
help in capturing more oops data.
Signed-off-by: Aruna Balakrishnaiah
Reviewed-by: Jim Keniston
---
arch/powerpc/platforms/pseries/nvram.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/ps
Currently the kernel provides the contents of p-series NVRAM only as a
simple stream of bytes via /dev/nvram, which must be interpreted in user
space by the nvram command in the powerpc-utils package. This patch set
exploits the pstore subsystem to expose each partition in NVRAM as a
separate file
On Wed, 24 Apr 2013 10:55:10 +0800
Tiejun Chen wrote:
> commit 761bbcb7, "usb: ehci-fsl: set INCR8 mode for system bus interface
> on MPC512x", introduced to fix one MPC5121e (M36P) Errata by setting
> INCR8 mode for system bus interface on MPC512x, but we should make sure
> this is only valid fo
On Tue, 2013-04-23 at 06:36 +, Jia Hongtao-B38951 wrote:
> These definitions are firstly used by KVM defined like OP_31_XOP_TRAP.
> Two ways to extract these definitions for public use:
>
> 1. Like this patch did. For keeping the KVM code that using these
>definitions unchanged we do not u
Based on benh's proposal at
https://lists.ozlabs.org/pipermail/linuxppc-dev/2012-September/101237.html,
this change provides support for reserving memory from the
reserved-ranges node at the root of the device tree.
We just call memblock_reserve on these ranges for now.
Signed-off-by: Jeremy Kerr
Sorry, please ignore this temporarily since looks this is already covered in
tree.
I will look further into this to send another version.
Tiejun
On 04/24/2013 10:55 AM, Tiejun Chen wrote:
commit 761bbcb7, "usb: ehci-fsl: set INCR8 mode for system bus interface
on MPC512x", introduced to fix o
commit 761bbcb7, "usb: ehci-fsl: set INCR8 mode for system bus interface
on MPC512x", introduced to fix one MPC5121e (M36P) Errata by setting
INCR8 mode for system bus interface on MPC512x, but we should make sure
this is only valid for MPC512x like other parts of this commit. Otherwise
this would
This patch makes the kernel configuration option "Support for early boot text
console (BootX or OpenFirmware only)" an exclusive choice under the "Early
debugging" menu. This prevents selection of two early debug consoles
simultaneously which does not appear to be supported by the code in
arch/pow
Looks good.
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
On Wed, Apr 24, 2013 at 01:25:08AM +1000, Benjamin Herrenschmidt wrote:
>On Tue, 2013-04-23 at 19:03 +0800, Gavin Shan wrote:
>> * of flags if that becomes the case
>> */
>> if (tbl->it_type & TCE_PCI_SWINV_CREATE)
>> - pnv_tce_invalidate(tbl, tces, tcep - 1)
On Wed, Apr 24, 2013 at 01:21:53AM +1000, Benjamin Herrenschmidt wrote:
>On Tue, 2013-04-23 at 19:03 +0800, Gavin Shan wrote:
>>
>> +static int pnv_pci_ioda_msi_eoi(struct pnv_phb *phb, unsigned int hw_irq)
>> +{
>> + u8 p_bit = 1, q_bit = 1;
>> + long rc;
>> +
>> + while (p_bit
On Wed, Apr 24, 2013 at 01:19:00AM +1000, Benjamin Herrenschmidt wrote:
>On Tue, 2013-04-23 at 19:03 +0800, Gavin Shan wrote:
>> -/* Fixup wrong class code in p7ioc root complex */
>> +/* Fixup wrong class code in p7ioc and p8 root complex */
>> static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
On Wed, 2013-04-24 at 11:13 +1000, Michael Ellerman wrote:
> In commit 85fe402 (fs: do not assign default i_ino in new_inode), the
> initialisation of i_ino was removed from new_inode() and pushed down
> into the callers. However spufs_new_inode() was not updated.
>
> This exhibits as no files app
In commit 85fe402 (fs: do not assign default i_ino in new_inode), the
initialisation of i_ino was removed from new_inode() and pushed down
into the callers. However spufs_new_inode() was not updated.
This exhibits as no files appearing in /spu, because all our dirents
have a zero inode, which read
There appears to be no good reason to keep this as 64bit only. It works
on 32bit also, and has checks so that it can work correctly with 32bit
binaries on 64bit hardware which is why I think this works.
I tested this on qemu using the virtex-ml507 machine type.
Before,
/bin2 # ./test & cat /pr
On 04/19/2013 05:47:45 AM, Zhao Chenhui wrote:
From: Chen-Hui Zhao
For e6500, two threads in one core share one time base. Just need
to do time base sync on first thread of one core, and skip it on
the other thread.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
Signed-off-by: Andy Flemi
On 04/19/2013 05:47:46 AM, Zhao Chenhui wrote:
From: Chen-Hui Zhao
The L1 Data Cache of e6500 contains no modified data, no flush
is required.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
Signed-off-by: Andy Fleming
---
arch/powerpc/kernel/fsl_booke_cache.S | 11 ++-
1 file
On 04/19/2013 05:47:40 AM, Zhao Chenhui wrote:
From: Chen-Hui Zhao
In the case of SMP, during the time base sync period, all time bases
of
online cores must stop, then start simultaneously.
There is a RCPM (Run Control/Power Management) module in CoreNet
based SoCs.
Define a struct ccsr_
On 04/19/2013 05:47:35 AM, Zhao Chenhui wrote:
static int pmc_suspend_enter(suspend_state_t state)
{
- int ret;
+ int ret = 0;
+
+ switch (state) {
+#ifdef CONFIG_PPC_85xx
+ case PM_SUSPEND_MEM:
+#ifdef CONFIG_SPE
+ enable_kernel_spe();
+#endif
+
On 04/19/2013 05:47:34 AM, Zhao Chenhui wrote:
These cache operations support Freescale SoCs based on BOOK3E.
Move L1 cache operations to fsl_booke_cache.S in order to maintain
easily. And, add cache operations for backside L2 cache and platform
cache.
The backside L2 cache appears on e500mc
On Tue, 2013-04-23 at 13:46 -0500, Nathan Fontenot wrote:
> ok, good. I was not crazy about using ppc_md to do this and if you're fine
> with putting the pseries specific stuff in ifdef CONFIG_PPC_PSERIES I'll
> update the code to do that.
>
> Question concerning rtas code. There is quite a bit of
On 04/22/2013 09:49 PM, Michael Ellerman wrote:
> On Tue, Apr 23, 2013 at 12:00:26PM +1000, Stephen Rothwell wrote:
>> Hi Nathan,
>>
>> On Mon, 22 Apr 2013 13:47:55 -0500 Nathan Fontenot
>> wrote:
>>>
>>> #if defined(CONFIG_NUMA) && defined(CONFIG_PPC_SPLPAR)
>>> extern int start_topology_updat
On 04/22/2013 07:24 PM, Benjamin Herrenschmidt wrote:
> On Mon, 2013-04-22 at 13:41 -0500, Nathan Fontenot wrote:
>> From: Jesse Larrew
>>
>> Platform events such as partition migration or the new PRRN firmware
>> feature can cause the NUMA characteristics of a CPU to change, and these
>> changes
On 04/22/2013 08:50 PM, Stephen Rothwell wrote:
> Hi Nathan,
>
> On Mon, 22 Apr 2013 13:38:47 -0500 Nathan Fontenot
> wrote:
>>
>> -/* Option vector 5: PAPR/OF options supported */
>> -#define OV5_LPAR0x80/* logical partitioning supported */
>> -#define OV5_SPLPAR 0x40
On 04/22/2013 07:15 PM, Benjamin Herrenschmidt wrote:
> On Mon, 2013-04-22 at 13:30 -0500, Nathan Fontenot wrote:
>
>> This patch exposes a method for updating the device tree via
>> ppc_md.update_devicetree that takes a single 32-bit value as a parameter.
>> For pseries platforms this is the exis
Am Dienstag, 23. April 2013, 23:24:36 schrieb Michael Ellerman:
> On Mon, Apr 22, 2013 at 06:44:13PM +0200, Dennis Schridde wrote:
> > [1.] One line summary of the problem:
> > .. no threads shown in spufs
>
> So I think I've got this one fixed, this works for me, can you test it
> please?
Patch w
On Tue, 2013-04-23 at 19:03 +0800, Gavin Shan wrote:
> * of flags if that becomes the case
> */
> if (tbl->it_type & TCE_PCI_SWINV_CREATE)
> - pnv_tce_invalidate(tbl, tces, tcep - 1);
> + phb->dma_tce_invalidate(tbl, tces, tcep - 1);
>
>
> -Original Message-
> From: Joerg Roedel [mailto:j...@8bytes.org]
> Sent: Tuesday, April 23, 2013 8:39 AM
> To: Sethi Varun-B16395
> Cc: io...@lists.linux-foundation.org; linuxppc-dev@lists.ozlabs.org;
> linux-ker...@vger.kernel.org;
> ga...@kernel.crashing.org; b...@kernel.crashing.org
On Tue, 2013-04-23 at 19:03 +0800, Gavin Shan wrote:
>
> +static int pnv_pci_ioda_msi_eoi(struct pnv_phb *phb, unsigned int hw_irq)
> +{
> + u8 p_bit = 1, q_bit = 1;
> + long rc;
> +
> + while (p_bit || q_bit) {
> + rc = opal_pci_get_xive_reissue(phb->opal_id,
> +
On Tue, 2013-04-23 at 19:03 +0800, Gavin Shan wrote:
> -/* Fixup wrong class code in p7ioc root complex */
> +/* Fixup wrong class code in p7ioc and p8 root complex */
> static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
> {
> dev->class = PCI_CLASS_BRIDGE_PCI << 8;
> }
> DECLARE_PCI_F
Hi all,
I was looking at this file, and it looks like it could be used on 32bit
systems. There's patches in the history to add stuff accounting for both
32bits and 64bits .. My assumption was that it's not used because there
are many people who want it on 32bits, and so it hasn't been tested..
C
> -Original Message-
> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
> fei.zang=freescale@lists.ozlabs.org] On Behalf Of Kumar Gala
> Sent: Tuesday, April 23, 2013 10:29 PM
> To: Zang Roy-R61911
> Cc: linuxppc-dev@lists.ozlabs.org; Chen Yuanquan-B41889
> Subject: Re: [PATCH] po
On Apr 23, 2013, at 12:44 AM, Zang Roy-R61911 wrote:
>
>
>> -Original Message-
>> From: Zang Roy-R61911
>> Sent: Tuesday, April 23, 2013 2:36 AM
>> To: linuxppc-dev@lists.ozlabs.org
>> Cc: ga...@kernel.crashing.org; Zang Roy-R61911; Chen Yuanquan-B41889
>> Subject: [PATCH] powerpc/fsl-p
Add new return code to rtas_flash to indicate firmware entitlement
expiry. Strictly we don't need this update. But to keep it in sync
with PAPR, this was added.
Signed-off-by: Ananth N Mavinakayanahalli
Signed-off-by: Vasant Hegde
---
arch/powerpc/kernel/rtas_flash.c |5 +
1 file change
Add proper comment to ibm,validate-flash-image RTAS call
update result tokens.
Note: Only comment section is modified, no code change.
Signed-off-by: Vasant Hegde
Signed-off-by: Ananth N Mavinakayanahalli
---
arch/powerpc/kernel/rtas_flash.c | 27 ---
1 file changed,
Based on benh's proposal at
https://lists.ozlabs.org/pipermail/linuxppc-dev/2012-September/101237.html,
this change provides support for reserving memory from the
reserved-ranges node at the root of the device tree.
We just call memblock_reserve on these ranges for now.
Signed-off-by: Jeremy Kerr
> -Original Message-
> From: Joerg Roedel [mailto:j...@8bytes.org]
> Sent: Tuesday, April 23, 2013 7:09 PM
> To: Sethi Varun-B16395
> Cc: io...@lists.linux-foundation.org; linuxppc-dev@lists.ozlabs.org;
> linux-ker...@vger.kernel.org; ga...@kernel.crashing.org;
> b...@kernel.crashing.org;
On Tue, Apr 23, 2013 at 10:05:25AM +0530, Varun Sethi wrote:
> Added the following domain attributes for the FSL PAMU driver:
> 1. Added new iommu stash attribute, which allows setting of the
>LIODN specific stash id parameter through IOMMU API.
> 2. Added an attribute for enabling/disabling DM
Hello!
Please find an up-to-date dmesg log attached. It was created from a Linux
3.8.8 kernel with these two patches applied:
- for_each_node(node) {
+ for_each_online_node(node) {
- return distance;
+ return ((a == b) ? LOCAL_DISTANCE : REMOTE_DISTANCE);
On Mon, Apr 22, 2013 at 06:44:13PM +0200, Dennis Schridde wrote:
> Hello!
>
>
> [1.] One line summary of the problem:
> .. no threads shown in spufs
So I think I've got this one fixed, this works for me, can you test it
please?
I'll send a proper patch in the morning.
cheers
diff --git a/arch
On Tue, Apr 23, 2013 at 03:16:53PM +0200, Dennis Schridde wrote:
> Hello!
>
> Am Dienstag, 23. April 2013, 13:51:55 schrieb Dennis Schridde:
> > Am Tue, 23 Apr 2013 19:12:47 +1000
> > schrieb Michael Ellerman :
> > > On Mon, Apr 22, 2013 at 06:44:13PM +0200, Dennis Schridde wrote:
> > > For me it
Hello!
Am Dienstag, 23. April 2013, 13:51:55 schrieb Dennis Schridde:
> Am Tue, 23 Apr 2013 19:12:47 +1000
> schrieb Michael Ellerman :
> > On Mon, Apr 22, 2013 at 06:44:13PM +0200, Dennis Schridde wrote:
> > For me it is fixed by applying the following patch, it should be in
> > v3.10:
> I am cur
Thanks.
> -Original Message-
> From: iommu-boun...@lists.linux-foundation.org [mailto:iommu-
> boun...@lists.linux-foundation.org] On Behalf Of Joerg Roedel
> Sent: Tuesday, April 23, 2013 6:32 PM
> To: Sethi Varun-B16395
> Cc: ga...@kernel.crashing.org; b...@kernel.crashing.org; Yoder Stu
On Tue, Apr 23, 2013 at 02:45:50PM +0200, Dennis Schridde wrote:
> Hello everyone!
>
> I have been testing this patch (given to me by Grant Likely
> ) with various kernel versions (3.6.2, 3.6.11,
> 3.8.6, 3.8.8) since November and can confirm that it solves part of the IRQ
> mapping issue on Ce
On Tue, Apr 23, 2013 at 10:05:24AM +0530, Varun Sethi wrote:
> +#ifndef __PCI_H
> +#define __PCI_H
Using __PCI_H is not a wise choice, it has certainly a high risk of a
collision. Anyway, I changed it to __IOMMU_PCI_H and applied the patch.
Joerg
___
On Tue, Apr 23, 2013 at 02:41:18PM +0200, Dennis Schridde wrote:
> Am Dienstag, 23. April 2013, 22:16:21 schrieb Michael Ellerman:
> > On Tue, Apr 23, 2013 at 02:01:16PM +0200, Dennis Schridde wrote:
> > > I applied following patch by Grant Likely
> > > to fix some IRQ mapping problems:
> > Ah yes
Am Dienstag, 23. April 2013, 22:16:21 schrieb Michael Ellerman:
> On Tue, Apr 23, 2013 at 02:01:16PM +0200, Dennis Schridde wrote:
> > I applied following patch by Grant Likely
> > to fix some IRQ mapping problems:
> Ah yes, I forgot I also have basically the same patch. I've just sent it
> to the
On Tue, Apr 23, 2013 at 02:01:16PM +0200, Dennis Schridde wrote:
> Am Mon, 22 Apr 2013 18:44:13 +0200
> schrieb Dennis Schridde :
> > [4.] Kernel information
> >
> > [4.1.] Kernel version (from /proc/version):
> > I am using the Linux 3.8.8 kernel (vanilla-sources-3.8.8 on
> > Gentoo/Linux): # cat
None of the cell platforms support CPU hotplug, so we should iterate
only over online nodes when setting PMU interrupts.
This also fixes a warning during boot when NODES_SHIFT is large enough:
WARNING: at /scratch/michael/src/kmk/linus/kernel/irq/irqdomain.c:766
...
NIP [c00db278] .irq_li
Am Mon, 22 Apr 2013 18:44:13 +0200
schrieb Dennis Schridde :
> [4.] Kernel information
>
> [4.1.] Kernel version (from /proc/version):
> I am using the Linux 3.8.8 kernel (vanilla-sources-3.8.8 on
> Gentoo/Linux): # cat /proc/version
> Linux version 3.8.8 (root@blade00) (gcc version 4.7.2 (Gentoo
Hello Michael!
Am Tue, 23 Apr 2013 19:12:47 +1000
schrieb Michael Ellerman :
> On Mon, Apr 22, 2013 at 06:44:13PM +0200, Dennis Schridde wrote:
> For me it is fixed by applying the following patch, it should be in
> v3.10:
I am currently compiling the patched kernel. Will report back with the
res
On Tue, Apr 23, 2013 at 06:51:09PM +0800, Chen Yuanquan-B41889 wrote:
> On 04/23/2013 06:05 PM, Benjamin Herrenschmidt wrote:
> >On Tue, 2013-04-23 at 17:26 +0800, Chen Yuanquan-B41889 wrote:
> >>There's no response from Ben. How do you think about this patch?
> >>What's
> >>your advice?
> >Didn't
The TCE should be invalidated while it's created or free'd. The
approach to do that for IODA1 and IODA2 compliant PHBs are different.
So the patch differentiate them with virtualized interface hooked
to the PHB. It's notable that the PCI address is used to invalidate
the corresponding TCE on IODA2
As Michael Ellerman suggested, to add CONFIG_POWERNV_MSI for PowerNV
platform. That's similar to CONFIG_PSERIES_MSI for pSeries platform.
For now, we don't make it dependent on CONFIG_EEH since it's not ready
to enable that yet.
Apart from that, we also enable CONFIG_PPC_MSI_BITMAP on selecting
CO
The patch intends to initialize PHB3 during system boot stage. The
flag "PNV_PHB_MODEL_PHB3" is introduced to differentiate IODA2
compatible PHB3 from other types of PHBs.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/platforms/powernv/pci-ioda.c | 62 +++--
ar
The PHB3, which is compatible with IODA2, have lots of tables (RTT/
PETLV/PEST/IVT/RBA) in system memory and have corresponding BARs to
trace the system memory address. The tables have been allocated in
firmware and exported through device-tree. The patch retrieves the
tables explicitly.
Signed-of
The EOI handler of MSI/MSI-X interrupts for P8 (PHB3) need additional
steps to handle the P/Q bits in IVE before EOIing the corresponding
interrupt. The patch changes the EOI handler to cover that.
Signed-off-by: Gavin Shan
---
arch/powerpc/include/asm/xics.h |3 ++
arch/powerpc/pl
The patchset includes minimal support for PHB3. Initially, flag "PNV_PHB_IODA2"
is introduced to differentiate IODA2 compliant PHB3 from other types of PHBs and
do initialization accordingly for PHB3. Besides, variable IODA2 tables reside in
system memory and we allocate them in kernel, then pass t
On 04/23/2013 06:05 PM, Benjamin Herrenschmidt wrote:
On Tue, 2013-04-23 at 17:26 +0800, Chen Yuanquan-B41889 wrote:
There's no response from Ben. How do you think about this patch?
What's
your advice?
Didn't Michael put your patch in -next while I was on vacation ? I'll
check tomorrow.
Cheers
Hi Kumar,
Could you apply these patches?
Thanks.
[v3,1/4] powerpc/mpic: add irq_set_wake support
http://patchwork.ozlabs.org/patch/234934/
[v3,2/4] powerpc/mpic: add global timer support
http://patchwork.ozlabs.org/patch/234935/
[v3,3/4] powerpc/mpic: create mpic subsystem object
http://patchw
On Tue, 2013-04-23 at 17:26 +0800, Chen Yuanquan-B41889 wrote:
> There's no response from Ben. How do you think about this patch?
> What's
> your advice?
Didn't Michael put your patch in -next while I was on vacation ? I'll
check tomorrow.
Cheers,
Ben.
_
Hi Kumar, Scott,
Do you have any comments on this set of patches?
Best Regards,
-Chenhui
On Fri, Apr 19, 2013 at 06:47:34PM +0800, Zhao Chenhui wrote:
> These cache operations support Freescale SoCs based on BOOK3E.
> Move L1 cache operations to fsl_booke_cache.S in order to maintain
> easily. A
On 04/13/2013 03:14 PM, Kevin Hao wrote:
In patch 34642bbb (powerpc/fsl-pci: Keep PCI SoC controller registers in
pci_controller) we choose to keep the map of the PCI SoC controller
registers. But we missed to delete the unmap in setup_pci_atmu
function. This will cause the following call trace o
On 04/23/2013 05:13 PM, Kevin Hao wrote:
On Tue, Apr 23, 2013 at 11:18:03PM +0800, Roy Zang wrote:
pci hose->private_data will be used by other function, for example,
fsl_pcie_check_link(), so do not iounmap it.
I already sent out a same patch ten days ago. :-)
http://patchwork.ozlabs.org/patc
On 04/10/2013 05:08 PM, Chen Yuanquan-B41889 wrote:
On 04/03/2013 12:08 PM, Chen Yuanquan-B41889 wrote:
On 04/02/2013 11:10 PM, Benjamin Herrenschmidt wrote:
On Tue, 2013-04-02 at 19:26 +0800, Yuanquan Chen wrote:
So we move the DMA & IRQ initialization code from
pcibios_setup_devices() and
co
On Tue, Apr 23, 2013 at 11:18:03PM +0800, Roy Zang wrote:
> pci hose->private_data will be used by other function, for example,
> fsl_pcie_check_link(), so do not iounmap it.
I already sent out a same patch ten days ago. :-)
http://patchwork.ozlabs.org/patch/236293/
Thanks,
Kevin
>
> fix the k
On Mon, Apr 22, 2013 at 06:44:13PM +0200, Dennis Schridde wrote:
> Hello!
Hi Dennis,
> [1.] One line summary of the problem:
> Only 2 of 4 cores used on IBM Cell blades and no threads shown in spufs
>
>
> [2.] Full description of the problem/report:
> On my IBM Cell blades, only 2 out of the 4
Paul Mackerras writes:
> On Mon, Apr 22, 2013 at 03:30:39PM +0530, Aneesh Kumar K.V wrote:
>
>> Instead of storing shift value in hugepd pointer we use mmu_psize_def index
>> so that we can fit all the supported hugepage size in 4 bits
>
> That works, but does mean that we have to scan the mmu_ps
pci hose->private_data will be used by other function, for example,
fsl_pcie_check_link(), so do not iounmap it.
fix the kerenl crash on T4240:
Unable to handle kernel paging request for data at address
0x880080060f14
Faulting instruction address: 0xc0032554
Oops: Kernel access of bad
On Mon, Apr 22, 2013 at 03:30:39PM +0530, Aneesh Kumar K.V wrote:
> Instead of storing shift value in hugepd pointer we use mmu_psize_def index
> so that we can fit all the supported hugepage size in 4 bits
That works, but does mean that we have to scan the mmu_psize_defs[]
array to work out the
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