On Thu, Aug 16, 2012 at 07:41:53AM +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2012-08-15 at 18:59 +0200, Oleg Nesterov wrote:
> > On 07/26, Ananth N Mavinakayanahalli wrote:
> > >
> > > From: Ananth N Mavinakayanahalli
> > >
> > > This is the port of uprobes to powerpc. Usage is similar to x86
Hi,
I've been trying to get hardware breakpoints with perf to work on POWER7
but I'm getting the following:
% perf record -e mem:0x1000 true
Error: sys_perf_event_open() syscall returned with 28 (No space left on
device). /bin/dmesg may provide additional information.
Fatal: No
Freescale's Integrated Flash controller(IFC) v1.1.0 supports 40 bit
address bus width.
In case more than 32 bit address is used, the EXT registers should be set.
Add support of ext registers.
Signed-off-by: Kumar Gala
Signed-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha
---
Base upon git
> -Original Message-
> From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org]
> Sent: Thursday, August 16, 2012 6:43 AM
> To: Wood Scott-B07421
> Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org;
> ga...@kernel.crashing.org; Li Yang-R58472; Wood Scott-B07421
> Subject: Re: [P
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, August 16, 2012 1:29 AM
> To: Jia Hongtao-B38951
> Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org;
> b...@kernel.crashing.org; Li Yang-R58472; Wood Scott-B07421
> Subject: Re: [PATCH V7 1/3] powerpc/pci: Make s
On Wed, 2012-08-15 at 16:57 -0500, Scott Wood wrote:
> Is there no lasting remnant of that temporary wrong isa_io_base? We
> won't have I/O resources that were calculated relative to that, which
> stop working once isa_io_base changes? Or does that happen later, after
> this function has been cal
On 08/15/2012 04:32 PM, Benjamin Herrenschmidt wrote:
> On Wed, 2012-08-15 at 12:29 -0500, Scott Wood wrote:
>>> ---
>>> arch/powerpc/kernel/pci-common.c |2 +-
>>> 1 files changed, 1 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/arch/powerpc/kernel/pci-common.c
>>> b/arch/powerpc/kernel
On Wed, 2012-08-15 at 18:59 +0200, Oleg Nesterov wrote:
> On 07/26, Ananth N Mavinakayanahalli wrote:
> >
> > From: Ananth N Mavinakayanahalli
> >
> > This is the port of uprobes to powerpc. Usage is similar to x86.
>
> I am just curious why this series was ignored by powerpc maintainers...
Beca
About a week ago, an XServe G5 of mine started powering off more or less
randomly (after 1 hour, chances were good it for it to occur). A
problematic UPS has already been cut from the loop, and today I cleaned
the machine inside out with pressurized air. So far it runs, for now at
least, with
BTW... On a somewhat related note ... if you happen to have a spare
Xserve G5 PSU I'm interested :-) Mine died (well I -think- it's the
PSU ... it just won't power up) which means I can't test on these things
anymore (the new Windfarm RackMac driver is totally untested for
example).
Cheers,
Ben.
On Wed, 2012-08-15 at 19:53 +0200, Jan Engelhardt wrote:
> About a week ago, an XServe G5 of mine started powering off more or less
> randomly (after 1 hour, chances were good it for it to occur). A
> problematic UPS has already been cut from the loop, and today I cleaned
> the machine inside ou
On Wed, 2012-08-15 at 12:29 -0500, Scott Wood wrote:
> > ---
> > arch/powerpc/kernel/pci-common.c |2 +-
> > 1 files changed, 1 insertions(+), 1 deletions(-)
> >
> > diff --git a/arch/powerpc/kernel/pci-common.c
> > b/arch/powerpc/kernel/pci-common.c
> > index 0f75bd5..2a09aa5 100644
> > ---
Martyn,
Do you know why ge_imp3a.c has 0x9000 as the 'primary' PCIe bus on the board?
- k
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
On 08/15/2012 04:01 PM, Kumar Gala wrote:
>
> On Aug 15, 2012, at 12:31 PM, Scott Wood wrote:
>
>> On 08/15/2012 03:57 AM, Jia Hongtao wrote:
>>> PCI primary bus will be determined by looking for ISA node in device tree.
>>> Also for board ge_imp3a primary bus is the second PCI controller detecte
On Aug 15, 2012, at 12:31 PM, Scott Wood wrote:
> On 08/15/2012 03:57 AM, Jia Hongtao wrote:
>> PCI primary bus will be determined by looking for ISA node in device tree.
>> Also for board ge_imp3a primary bus is the second PCI controller detected.
>> So we add ISA node to ge_imp3a's device tree
Fix unused variable compiler warning when built with CONFIG_RAPIDIO_DEBUG
option off.
This patch is applicable to kernel versions starting from v3.2
Signed-off-by: Alexandre Bounine
Cc: Matt Porter
---
drivers/rapidio/devices/tsi721.c |5 -
1 files changed, 4 insertions(+), 1 deletions
Make sure that there is no doorbell messages left behind due to disabled
interrupts during inbound doorbell processing.
The most common case for this bug is loss of rionet JOIN messages in
systems with three or more rionet participants and MSI or MSI-X enabled.
As result, requests for packet trans
On Tue, Aug 14, 2012 at 06:23:58PM -0500, Ashley Lai wrote:
> Change log V3:
> - Replaced TPM_NO_EVENT_LOG macro with stubs
> - Removed tpm_noeventlog.c file
> - Called of_node_put() before return in tpm_of.c
>
> Change log V2:
> - Removed unnecessary tpm_bios_log_setup and tpm_bios_log_teardown
On 08/15/2012 04:22 AM, Jia Hongtao-B38951 wrote:
>
>
>> -Original Message-
>> From: Wood Scott-B07421
>> Sent: Saturday, August 11, 2012 12:00 AM
>> To: Jia Hongtao-B38951
>> Cc: Gala Kumar-B11780; Wood Scott-B07421; Li Yang-R58472; linuxppc-
>> d...@lists.ozlabs.org
>> Subject: Re: [PAT
On 08/15/2012 03:57 AM, Jia Hongtao wrote:
> We unified the Freescale pci/pcie initialization by changing the fsl_pci
> to a platform driver. In previous PCI code architecture the initialization
> routine is called at board_setup_arch stage. Now the initialization is done
> in probe function which
On 08/15/2012 03:57 AM, Jia Hongtao wrote:
> PCI primary bus will be determined by looking for ISA node in device tree.
> Also for board ge_imp3a primary bus is the second PCI controller detected.
> So we add ISA node to ge_imp3a's device tree to fit the new determination.
>
> Adding ISA node to o
On 08/15/2012 03:57 AM, Jia Hongtao wrote:
> From: Benjamin Herrenschmidt
>
> Some platforms like QEMU treat 0 as an invalid address for ISA IO base.
> So we make sure that ISA IO base will never be zero. By functionality this
> is equivalent to assgin the first pci bus detected as a primary bus.
On 07/26, Ananth N Mavinakayanahalli wrote:
>
> From: Ananth N Mavinakayanahalli
>
> This is the port of uprobes to powerpc. Usage is similar to x86.
I am just curious why this series was ignored by powerpc maintainers...
Of course I can not review this code, I know nothing about powerpc,
but th
Freescale's Integrated Flash controller (IFC) may have one or two
interrupts. In case of single interrupt line, it will cover all IFC
interrupts.
Update this information in IFC device tree bindings
Signed-off-by: Prabhakar Kushwaha
---
Base upon git://git.kernel.org/pub/scm/linux/kernel/git/gala
Just as Artem suggested:
"Both UBI and JFFS2 are able to read verify what they wrote already.
There are also MTD tests which do this verification. So I think there
is no reason to keep this in the NAND layer, let alone wasting RAM in
the driver to support this feature."
So kill MTD_NAND_VERIFY_WR
On Aug 14, 2012, at 10:56 PM, "Jia Hongtao-B38951" wrote:
>>
>>>
>>> +EXPORT_SYMBOL_GPL(mpc85xx_pci_err_probe);
>>
>> Make this EXPORT_SYMBOL.
>>
>
> Hi Timur and Kumar:
>
> I'm a little confused.
> Should we remove _GPL for upstream version too?
Yes.
>
> -Hongtao.
___
From: Benjamin Herrenschmidt
Some platforms like QEMU treat 0 as an invalid address for ISA IO base.
So we make sure that ISA IO base will never be zero. By functionality this
is equivalent to assgin the first pci bus detected as a primary bus.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-b
PCI primary bus will be determined by looking for ISA node in device tree.
Also for board ge_imp3a primary bus is the second PCI controller detected.
So we add ISA node to ge_imp3a's device tree to fit the new determination.
Adding ISA node to other boards' device tree is not necessary. The situat
We unified the Freescale pci/pcie initialization by changing the fsl_pci
to a platform driver. In previous PCI code architecture the initialization
routine is called at board_setup_arch stage. Now the initialization is done
in probe function which is architectural better. Also It's convenient for
a
From: Benjamin Herrenschmidt
In this patch set we unified the Freescale pci/pcie initialization by
changing the fsl_pci to a platform driver.
We also change the way of determining primary bus for fitting platform
driver. The first two patches are the preparation for this.
Thanks to Ben. For th
> -Original Message-
> From: Wood Scott-B07421
> Sent: Saturday, August 11, 2012 12:00 AM
> To: Jia Hongtao-B38951
> Cc: Gala Kumar-B11780; Wood Scott-B07421; Li Yang-R58472; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH V5 3/3] powerpc/fsl-pci: Unify pci/pcie
> initialization c
> -Original Message-
> From: dan.j.willi...@gmail.com [mailto:dan.j.willi...@gmail.com] On
> Behalf Of Dan Williams
> Sent: Wednesday, August 15, 2012 4:02 AM
> To: Liu Qiang-B32616
> Cc: dan.j.willi...@intel.com; vinod.k...@intel.com; a...@arndb.de;
> herb...@gondor.apana.org.au; gre...@li
32 matches
Mail list logo
