Freescale's Integrated Flash controller (IFC) may have one or two
interrupts. In case of single interrupt line, it will cover all IFC
interrupts.
Update this information in IFC device tree bindings
Signed-off-by: Prabhakar Kushwaha <prabha...@freescale.com>
---
Base upon git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
Branch next
.../devicetree/bindings/powerpc/fsl/ifc.txt | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
index 939a26d..88c7a26 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
@@ -12,9 +12,12 @@ Properties:
- #size-cells : Either one or two, depending on how large each chipselect
can be.
- reg : Offset and length of the register set for the device
-- interrupts : IFC has two interrupts. The first one is the "common"
- interrupt(CM_EVTER_STAT), and second is the NAND interrupt
- (NAND_EVTER_STAT).
+- interrupts: IFC may have one or two interrupts. If two interrupt
+ specifiers are present, the first is the "common"
+ interrupt (CM_EVTER_STAT), and the second is the NAND
+ interrupt (NAND_EVTER_STAT). If there is only one,
+ that interrupt reports both types of event.
+
- ranges : Each range corresponds to a single chipselect, and covers
the entire access window as configured.
--
1.7.9.5
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