> -Original Message-
> From: Ira W. Snyder [mailto:i...@ovro.caltech.edu]
> Sent: Thursday, August 02, 2012 1:31 AM
> To: Liu Qiang-B32616
> Cc: linux-cry...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; linux-
> ker...@vger.kernel.org; dan.j.willi...@gmail.com; Vinod Koul; Tabi Timur-
>
> -Original Message-
> From: Ira W. Snyder [mailto:i...@ovro.caltech.edu]
> Sent: Thursday, August 02, 2012 12:31 AM
> To: Liu Qiang-B32616
> Cc: linux-cry...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; linux-
> ker...@vger.kernel.org; dan.j.willi...@gmail.com; Vinod Koul;
> herb...@gon
> -Original Message-
> From: Ira W. Snyder [mailto:i...@ovro.caltech.edu]
> Sent: Thursday, August 02, 2012 12:36 AM
> To: Liu Qiang-B32616
> Cc: linux-cry...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; linux-
> ker...@vger.kernel.org; dan.j.willi...@gmail.com; Vinod Koul;
> herb...@gon
On Wed, Aug 01, 2012 at 09:43:32PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> To clarify the meaning for future readers, replace the open coded
> 19 with CONTEXT_BITS
>
> Signed-off-by: Aneesh Kumar K.V
Reviewed-by: Paul Mackerras
___
Jiri Kosina writes:
> if (personality(current->personality) == PER_LINUX32
> - && personality == PER_LINUX)
> - personality = PER_LINUX32;
> + && personality(personality) == PER_LINUX)
> + personality &= ~PER_LINUX | PER_LINUX32;
That doesn't work.
Directly comparing current->personality against PER_LINUX32 doesn't work
in cases when any of the personality flags stored in the top three bytes
are used.
Directly forcefully setting personality to PER_LINUX32 or PER_LINUX
discards any flags stored in the top three bytes
Use personality() macr
Hi all,
during testing i encountered a problem with setting up a 5200B
controller with a MICREL phy at static 100MBit full duplex - without
autonegotiation.
I performed this as usual with ethtool and was succesful when i had my
link partner up, providing a link.
When kepping the link partne
>
>
> On Jul 26, 2012, at 7:30 AM, Jia Hongtao wrote:
>
> > We unified the Freescale pci/pcie initialization by changing the fsl_pci
> > to a platform driver. In previous PCI code architecture the initialization
> > routine is called at board_setup_arch stage. Now the initialization is done
> > in
On Wed, Aug 01, 2012 at 04:50:09PM +0800, qiang@freescale.com wrote:
> From: Qiang Liu
>
> - use spin_lock_bh() is the right way to use async_tx api,
> dma_run_dependencies() should not be protected by spin_lock_irqsave();
> - use spin_lock_bh to instead of spin_lock_irqsave for improving per
On Wed, Aug 01, 2012 at 04:50:27PM +0800, qiang@freescale.com wrote:
> From: Qiang Liu
>
> Fix a warning of unitialized value when compile with -Wuninitialized.
>
Looks good to me.
Acked-by: Ira W. Snyder
> Cc: Dan Williams
> Cc: Vinod Koul
> Cc: Li Yang
> Signed-off-by: Qiang Liu
>
On Wed, Aug 01, 2012 at 04:49:17PM +0800, qiang@freescale.com wrote:
> From: Qiang Liu
>
> Fix the potential risk when enable config NET_DMA and ASYNC_TX.
> Async_tx is lack of support in current release process of dma descriptor,
> all descriptors will be released whatever is acked or no-ack
On Wed, Aug 01, 2012 at 04:49:08PM +0800, qiang@freescale.com wrote:
> From: Qiang Liu
>
> Delete attribute DMA_INTERRUPT because fsl-dma doesn't support this function,
> exception will be thrown if talitos is used to offload xor at the same time.
>
I have no problem with this patch.
Howev
On Wed, Aug 01, 2012 at 04:49:43PM +0800, qiang@freescale.com wrote:
> From: Qiang Liu
>
> Move the function fsldma_cleanup_descriptor() and fsl_chan_xfer_ld_queue()
> ahead of its invoke function for avoiding redundant definition.
>
> Cc: Dan Williams
> Cc: Vinod Koul
> Cc: Li Yang
> Sig
From: "Aneesh Kumar K.V"
This update the proto-VSID and VSID scramble related information
to be more generic by using names instead of current values.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h | 40 ++---
arch/powerpc/mm/mmu_context
From: "Aneesh Kumar K.V"
Increase max addressable range to 64TB. This is not tested on
real hardware yet.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h| 42 --
arch/powerpc/include/asm/pgtable-ppc64-4k.h |2 +-
arch/powerpc/inc
From: "Aneesh Kumar K.V"
With larger vsid we need to track more bits of ESID in slb cache
for slb invalidate.
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/paca.h |2 +-
arch/powerpc/mm/slb_low.S |8
2 files changed, 5 insertio
From: "Aneesh Kumar K.V"
This patch simplify hpte_decode for easy switching of virtual address to
virtual page number in the later patch
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_native_64.c | 49 ++
1 file chang
From: "Aneesh Kumar K.V"
slice array size and slice mask size depend on PGTABLE_RANGE. We
can't directly include pgtable.h in these header because there is
a circular dependency. So add compile time check for these values.
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/p
From: "Aneesh Kumar K.V"
Rename the variable to better reflect the values. No functional change
in this patch.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s.h |2 +-
arch/powerpc/include/asm/machdep.h |6 +--
arch/powerpc/include/asm/mmu-hash64.h |
From: "Aneesh Kumar K.V"
Don't open code the same
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/cell/beat_htab.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/cell/beat_htab.c
b/arch/powerpc/platforms/ce
From: "Aneesh Kumar K.V"
ASM_VSID_SCRAMBLE can leave non-zero bits in the high 28 bits of the result
for 256MB segment (40 bits for 1T segment). Properly mask them before using
the values in slbmte
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/slb_low.S | 1
From: "Aneesh Kumar K.V"
This patch makes the high psizes mask as an unsigned char array
so that we can have more than 16TB. Currently we support upto
64TB
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h |6 +-
arch/powerpc/include/asm/page_64.h|6 +-
arch
From: "Aneesh Kumar K.V"
As we keep increasing PGTABLE_RANGE we need not increase the virual
map area for kernel.
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable-ppc64.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arc
From: "Aneesh Kumar K.V"
This patch convert different functions to take virtual page number
instead of virtual address. Virtual page number is virtual address
shifted right by VPN_SHIFT (12) bits. This enable us to have an
address range of upto 76 bits.
Signed-off-by: Aneesh Kumar K.V
---
arch
From: "Aneesh Kumar K.V"
To clarify the meaning for future readers, replace the open coded
19 with CONTEXT_BITS
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/mmu_context_hash64.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/mmu_context_hash64.c
Hi,
This patchset include patches for supporting 64TB with ppc64. I haven't booted
this on hardware with 64TB memory yet. But they boot fine on real hardware with
less memory. Changes extend VSID bits to 38 bits for a 256MB segment
and 26 bits for 1TB segments.
Changes from v5:
* Address review
On Wed, Aug 01, 2012 at 12:13:19PM +, Singh Sandeep-B37400 wrote:
> > On Mon, Jul 30, 2012 at 09:50:57AM +, Singh Sandeep-B37400 wrote:
> > > 1. You should send some kernel mode TDM clients. Without those the
> > framework
> > >is pretty useless.
> > > [Sandeep] We do have a test client
> -Original Message-
> From: Greg KH [mailto:g...@kroah.com]
> Sent: Monday, July 30, 2012 9:32 PM
> To: Singh Sandeep-B37400
> Cc: Francois Romieu; de...@driverdev.osuosl.org; linuxppc-
> d...@lists.ozlabs.org; ga...@kernel.crashing.org; linux-arm-
> ker...@lists.infradead.org; linux-ke
Paul Mackerras writes:
> On Mon, Jul 30, 2012 at 04:52:19PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V"
>>
>> This update the proto-VSID and VSID scramble related information
>> to be more generic by using names instead of current values.
>
> Comments below...
>
>> - * VSID alloc
Paul Mackerras writes:
> On Mon, Jul 30, 2012 at 04:52:18PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V"
>>
>> To clarify the meaning for future readers, replace the open coded
>> 19 with CONTEXT_BITS
>>
>> Signed-off-by: Aneesh Kumar K.V
>> ---
>> arch/powerpc/mm/mmu_context_h
Hi Ira,
I hope we can discuss fsl-dma in this thread. In this patch I give a simple
case to illustrate why I must correct the release process of finished
descriptors.
There is potential risk in current fsl-dma, the finished cookie value and
finished async_tx descriptor should be judged by hardw
On Wed, Aug 01, 2012 at 05:04:46AM -0400, Richard Yang wrote:
>On Wed, Aug 01, 2012 at 04:26:54PM +0800, Gavin Shan wrote:
>>On Wed, Aug 01, 2012 at 03:49:41AM -0400, Richard Yang wrote:
>>>On Mon, Jun 25, 2012 at 11:43:14PM +0800, Gavin Shan wrote:
Basically, there're 2 types of PCI bus sensit
From: Qiang Liu
Fix a warning of unitialized value when compile with -Wuninitialized.
Cc: Dan Williams
Cc: Vinod Koul
Cc: Li Yang
Signed-off-by: Qiang Liu
Reported-by: Kim Phillips
---
drivers/dma/fsldma.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/dm
From: Qiang Liu
- use spin_lock_bh() is the right way to use async_tx api,
dma_run_dependencies() should not be protected by spin_lock_irqsave();
- use spin_lock_bh to instead of spin_lock_irqsave for improving performance,
There is not any place to access descriptor queues in fsl-dma ISR except
From: Qiang Liu
Move the function fsldma_cleanup_descriptor() and fsl_chan_xfer_ld_queue()
ahead of its invoke function for avoiding redundant definition.
Cc: Dan Williams
Cc: Vinod Koul
Cc: Li Yang
Signed-off-by: Qiang Liu
---
drivers/dma/fsldma.c | 252 +--
From: Qiang Liu
Fix the potential risk when enable config NET_DMA and ASYNC_TX.
Async_tx is lack of support in current release process of dma descriptor,
all descriptors will be released whatever is acked or no-acked by async_tx,
so there is a potential race condition when dma engine is uesd by o
From: Qiang Liu
Delete attribute DMA_INTERRUPT because fsl-dma doesn't support this function,
exception will be thrown if talitos is used to offload xor at the same time.
Cc: Dan Williams
Cc: Vinod Koul
Cc: Li Yang
Signed-off-by: Qiang Liu
Acked-by: Ira W. Snyder
---
drivers/dma/fsldma.c |
From: Qiang Liu
Expose Talitos's XOR functionality to be used for RAID parity
calculation via the Async_tx layer.
Cc: Herbert Xu
Cc: David S. Miller
Signed-off-by: Dipen Dudhat
Signed-off-by: Maneesh Gupta
Signed-off-by: Kim Phillips
Signed-off-by: Vishnu Suresh
Signed-off-by: Qiang Liu
-
Hi,
The following 6 patches enabling fsl-dma and talitos offload raid
operations for improving raid performance and balancing CPU load.
Write performance will be improved by 25-30% tested by iozone.
Write performance is improved about 2% after using spin_lock_bh replace
spin_lock_irqsave.
CPU loa
On Wed, Aug 01, 2012 at 04:26:54PM +0800, Gavin Shan wrote:
>On Wed, Aug 01, 2012 at 03:49:41AM -0400, Richard Yang wrote:
>>On Mon, Jun 25, 2012 at 11:43:14PM +0800, Gavin Shan wrote:
>>>Basically, there're 2 types of PCI bus sensitive PEs: (A) The PE
>>>includes single PCI bus. (B) The PE include
On Wed, Aug 01, 2012 at 03:49:41AM -0400, Richard Yang wrote:
>On Mon, Jun 25, 2012 at 11:43:14PM +0800, Gavin Shan wrote:
>>Basically, there're 2 types of PCI bus sensitive PEs: (A) The PE
>>includes single PCI bus. (B) The PE includes the PCI bus and all
>>the subordinate PCI buses. At present, w
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Tuesday, July 31, 2012 10:31 PM
> To: Wang Dongsheng-B40534
> Cc: b...@kernel.crashing.org; pau...@samba.org; Wood Scott-B07421;
> linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/fsl: mpic time
Paul Mackerras writes:
> On Mon, Jul 30, 2012 at 04:52:17PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V"
>>
>> The proto-VSID space is divided into two class
>> User: 0 to 2^(CONTEXT_BITS + USER_ESID_BITS) -1
>> kernel: 2^(CONTEXT_BITS + USER_ESID_BITS) to 2^(VSID_BITS) - 1
>>
On Mon, Jun 25, 2012 at 11:43:14PM +0800, Gavin Shan wrote:
>Basically, there're 2 types of PCI bus sensitive PEs: (A) The PE
>includes single PCI bus. (B) The PE includes the PCI bus and all
>the subordinate PCI buses. At present, we'd like to put PCI bus
>originated by PCI-e link to form PE that
Paul Mackerras writes:
> On Mon, Jul 30, 2012 at 04:52:13PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V"
>>
>> slice array size and slice mask size depend on PGTABLE_RANGE. We
>> can't directly include pgtable.h in these header because there is
>> a circular dependency. So add com
Paul Mackerras writes:
> On Mon, Jul 30, 2012 at 04:52:12PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V"
>>
>> This patch makes the high psizes mask as an unsigned char array
>> so that we can have more than 16TB. Currently we support upto
>> 64TB
>
> Comments below...
>
>> diff -
On Wed, 1 Aug 2012 at 12:02, Tony Breeds wrote:
> 1) can you also upload you vmlinux so we can poke at it.
I've uploaded the vmlinx (and System.map) to the same location:
http://nerdbynature.de/bits/3.5.0/yaboot/
> 2) What is the dmseg.txt file there? If you're unable to boot 3.5 how
> did yo
Paul Mackerras writes:
> On Mon, Jul 30, 2012 at 04:52:09PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V"
>>
>> This patch convert different functions to take virtual page number
>> instead of virtual address. Virtual page number is virtual address
>> shifted right by VPN_SHIFT (12
>From 5dfd547532fca61462dc17fd0bb8e533002c4bc5 Mon Sep 17 00:00:00 2001
From: Jesse Larrew
Date: Thu, 7 Jun 2012 16:04:34 -0500
arch_update_cpu_topology() should only return 1 when the topology has
actually changed, and should return 0 otherwise.
This patch fixes a potential bug where rebuild_sc
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