Hi Wen,
2012/07/11 15:25, Wen Congyang wrote:
> At 07/11/2012 01:52 PM, Yasuaki Ishimatsu Wrote:
>> 2012/07/11 14:06, Wen Congyang wrote:
>> Hi Wen,
>>
>>> At 07/09/2012 06:33 PM, Yasuaki Ishimatsu Wrote:
I don't think that all pages of virtual mapping in removed memory can be
freed, sin
At 07/11/2012 01:52 PM, Yasuaki Ishimatsu Wrote:
> 2012/07/11 14:06, Wen Congyang wrote:
> Hi Wen,
>
>> At 07/09/2012 06:33 PM, Yasuaki Ishimatsu Wrote:
>>> I don't think that all pages of virtual mapping in removed memory can be
>>> freed, since page which type is MIX_SECTION_INFO is difficult to
2012/07/11 14:06, Wen Congyang wrote:
Hi Wen,
> At 07/09/2012 06:33 PM, Yasuaki Ishimatsu Wrote:
>> I don't think that all pages of virtual mapping in removed memory can be
>> freed, since page which type is MIX_SECTION_INFO is difficult to free.
>> So, the patch only frees page which type is SECT
> diff --git a/arch/powerpc/kernel/machine_kexec.c
> b/arch/powerpc/kernel/machine_kexec.c
> index c957b12..0c9695d 100644
> --- a/arch/powerpc/kernel/machine_kexec.c
> +++ b/arch/powerpc/kernel/machine_kexec.c
> @@ -207,6 +207,12 @@ static struct property crashk_size_prop = {
> .value = &cr
At 07/09/2012 06:33 PM, Yasuaki Ishimatsu Wrote:
> I don't think that all pages of virtual mapping in removed memory can be
> freed, since page which type is MIX_SECTION_INFO is difficult to free.
> So, the patch only frees page which type is SECTION_INFO at first.
>
> CC: David Rientjes
> CC: Ji
On Wed, Jun 27, 2012 at 07:34:11PM +, Kim Phillips wrote:
> On Wed, 27 Jun 2012 10:58:32 +0530
> Bharat Bhushan wrote:
>
> > This resolves the Linux boot crash issue when "swiotlb=force" is set
> > in bootargs on systems which have memory more than 4G.
>
> Acked-by: Kim Phillips
Patch appl
> -Original Message-
> From: Phillips Kim-R1AAHA
> Sent: Wednesday, July 11, 2012 8:11 AM
> To: Liu Qiang-B32616
> Cc: linux-cry...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Li Yang-
> R58472; Herbert Xu; David S. Miller; Geanta Neag Horia Ioan-B05471
> Subject: Re: [PATCH 1/4] Talito
At 07/11/2012 09:52 AM, Wen Congyang Wrote:
> At 07/09/2012 06:21 PM, Yasuaki Ishimatsu Wrote:
>> This patch series aims to support physical memory hot-remove.
>>
>> [RFC PATCH v3 1/13] memory-hotplug : rename remove_memory to offline_memory
>> [RFC PATCH v3 2/13] memory-hotplug : add physical
> -Original Message-
> From: Tabi Timur-B04825
> Sent: Wednesday, July 11, 2012 5:26 AM
> To: Liu Qiang-B32616
> Cc: linux-cry...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Herbert
> Xu; Li Yang-R58472; David S. Miller
> Subject: Re: [linuxppc-release] [PATCH 4/4] Talitos: fix the issu
> -Original Message-
> From: Dan Williams [mailto:dan.j.willi...@intel.com]
> Sent: Wednesday, July 11, 2012 3:39 AM
> To: Liu Qiang-B32616
> Cc: linux-cry...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Li Yang-
> R58472; Phillips Kim-R1AAHA; Vinod Koul
> Subject: Re: [PATCH 3/4] fsl-dm
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, July 11, 2012 2:15 AM
> To: Jia Hongtao-B38951
> Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org
> Subject: Re: [PATCH 1/2] powerpc/mpc8572ds: Fix eTSEC is not available on
> core1 of AMP boot issue
>
> On 07/
At 07/09/2012 06:21 PM, Yasuaki Ishimatsu Wrote:
> This patch series aims to support physical memory hot-remove.
>
> [RFC PATCH v3 1/13] memory-hotplug : rename remove_memory to offline_memory
> [RFC PATCH v3 2/13] memory-hotplug : add physical memory hotplug code to
> acpi_memory_device_remo
Hi Jiang,
2012/07/11 9:21, Jiang Liu wrote:
On 07/11/2012 08:09 AM, Yasuaki Ishimatsu wrote:
Hi Jiang,
2012/07/11 1:50, Jiang Liu wrote:
On 07/10/2012 05:58 PM, Yasuaki Ishimatsu wrote:
Hi Christoph,
2012/07/10 0:18, Christoph Lameter wrote:
On Mon, 9 Jul 2012, Yasuaki Ishimatsu wrote:
On Tue, 2012-07-10 at 19:47 -0500, Scott Wood wrote:
> On 07/10/2012 07:44 PM, Alexander Graf wrote:
> >
> > On 11.07.2012, at 02:34, Scott Wood wrote:
> >> +#ifdef CONFIG_BOOKE
> >> + /*
> >> + * We're not changing address space on Book E, and the extra rfi
> >> + * can hurt when virtualized
On Tue, 2012-07-10 at 19:41 -0500, Scott Wood wrote:
> On 07/10/2012 07:36 PM, Benjamin Herrenschmidt wrote:
> > On Tue, 2012-07-10 at 19:34 -0500, Scott Wood wrote:
> >> Unlike classic, we don't really need the MSR change to be atomic with the
> >> branch. This eliminates a trap as a KVM guest (i
On 07/10/2012 07:44 PM, Alexander Graf wrote:
>
> On 11.07.2012, at 02:34, Scott Wood wrote:
>> +#ifdef CONFIG_BOOKE
>> +/*
>> + * We're not changing address space on Book E, and the extra rfi
>> + * can hurt when virtualized without hardware support -- whereas
>> + * mtmsr can be
On 11.07.2012, at 02:34, Scott Wood wrote:
> Unlike classic, we don't really need the MSR change to be atomic with the
> branch. This eliminates a trap as a KVM guest (in the absence of
> hardware hypervisor extensions), where mtmsr is paravirtualized but rfi
> is not. For a virtualized guest w
On 07/10/2012 07:36 PM, Benjamin Herrenschmidt wrote:
> On Tue, 2012-07-10 at 19:34 -0500, Scott Wood wrote:
>> Unlike classic, we don't really need the MSR change to be atomic with the
>> branch. This eliminates a trap as a KVM guest (in the absence of
>> hardware hypervisor extensions), where mt
On Tue, 2012-07-10 at 19:34 -0500, Scott Wood wrote:
> Unlike classic, we don't really need the MSR change to be atomic with the
> branch. This eliminates a trap as a KVM guest (in the absence of
> hardware hypervisor extensions), where mtmsr is paravirtualized but rfi
> is not. For a virtualized
Unlike classic, we don't really need the MSR change to be atomic with the
branch. This eliminates a trap as a KVM guest (in the absence of
hardware hypervisor extensions), where mtmsr is paravirtualized but rfi
is not. For a virtualized guest without any paravirtualization, this
eliminates an add
Similar to how the primary PCI bridge is identified by looking
for an isa subnode, we determine whether to apply uli exclusions
by looking for a uli subnode.
Signed-off-by: Scott Wood
---
v2: Rebased on Kumar's next
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 97 +-
As an alternative incremental starting point to Jia Hongtao's patchset,
get the FSL PCI init out of the board files, but do not yet convert to a
platform driver.
Rather than having each board supply a magic register offset for
determining the "primary" bus, we look for which PCI host bridge
contai
This gives the kernel a paravirtualized machine to target, without
requiring both sides to pretend to be targeting a specific board
that likely has little to do with the host in KVM scenarios. This
avoids the need to add new boards to QEMU just to be able to
run KVM on new CPUs.
As this is the fi
The QEMU stuff is related to the PCI refactoring because currently
we have a hard time selecting a primary bus under QEMU, and also because
the generic qemu e500 platform wants a full list of FSL PCI compatibles
to check.
Patchset rebased on Kumar's next branch.
Scott Wood (3):
powerpc/fsl-pci:
On 07/11/2012 08:09 AM, Yasuaki Ishimatsu wrote:
> Hi Jiang,
>
> 2012/07/11 1:50, Jiang Liu wrote:
>> On 07/10/2012 05:58 PM, Yasuaki Ishimatsu wrote:
>>> Hi Christoph,
>>>
>>> 2012/07/10 0:18, Christoph Lameter wrote:
On Mon, 9 Jul 2012, Yasuaki Ishimatsu wrote:
> Even if you a
On Tue, 10 Jul 2012 13:56:46 +0800
Qiang Liu wrote:
> Move the declaration of talitos data structure into talitos.h.
>
> Cc: Herbert Xu
> Cc: David S. Miller
> Signed-off-by: Qiang Liu
> ---
this patch has already been submitted [1].
Subsequent patches in this series also don't apply cleanl
Hi Jiang,
2012/07/11 1:50, Jiang Liu wrote:
On 07/10/2012 05:58 PM, Yasuaki Ishimatsu wrote:
Hi Christoph,
2012/07/10 0:18, Christoph Lameter wrote:
On Mon, 9 Jul 2012, Yasuaki Ishimatsu wrote:
Even if you apply these patches, you cannot remove the physical memory
completely since these pa
On 05.07.2012, at 16:41, Stuart Yoder wrote:
> From: Stuart Yoder
>
> Signed-off-by: Stuart Yoder
Ben, ping?
Alex
> ---
> -v4: fixed build issues in exception-64s.h and exceptions-64s.S
>
> arch/powerpc/include/asm/exception-64s.h |4 ++--
> arch/powerpc/include/asm/thread_info.h |
Qiang Liu wrote:
> An error will be happened when test with mass data:
Please don't use the phrase "fix the issue" in patch summaries. It's
redundant.
This patch should be titled,
"drivers/crypto: fix memory leak in Talitos driver"
> diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talit
On Mon, Jul 9, 2012 at 10:59 PM, Qiang Liu wrote:
> - delete attribute of DMA_INTERRUPT because fsl-dma doesn't support
> this function, exception will be thrown if talitos is used to compute xor
> at the same time;
> - change the release process of dma descriptor for avoiding exception when
> ena
Hi Ben,
On Tue, 2012-07-10 at 13:20 +1000, Benjamin Herrenschmidt wrote:
> regarding the precise semantics of lv1_pause() ?
Here's what's in PS3's setup.c:
static void ps3_power_save(void)
{
/*
* lv1_pause() puts the PPE thread into inactive state until an
* irq on an u
--- On Mon, 7/2/12, Benjamin Herrenschmidt wrote:
> From: Benjamin Herrenschmidt
> Subject: Re: [git pull] Please pull powerpc.git merge branch
> To: "Gerhard Pircher"
> Cc: "linuxppc-dev list"
> Date: Monday, July 2, 2012, 3:20 PM
> On Mon, 2012-07-02 at 23:38 +0200,
> Gerhard Pircher wrote:
On Jun 27, 2012, at 6:50 PM, Scott Wood wrote:
> Similar to how the primary PCI bridge is identified by looking
> for an isa subnode, we determine whether to apply uli exclusions
> by looking for a uli subnode.
>
> Signed-off-by: Scott Wood
> ---
> Besides being an example of a real-hardware bo
On 07/10/2012 01:08 AM, Jia Hongtao wrote:
> The issue log on core1 is:
> root@mpc8572ds:~# ifconfig eth0 10.192.208.244
> net eth0: could not attach to PHY
> SIOCSIFFLAGS: No such device
>
> To attach PHY node mdio@24520 should not be disabled in dts of core1.
> Because all PHYs are controlled th
On 07/10/2012 05:58 PM, Yasuaki Ishimatsu wrote:
> Hi Christoph,
>
> 2012/07/10 0:18, Christoph Lameter wrote:
>>
>> On Mon, 9 Jul 2012, Yasuaki Ishimatsu wrote:
>>
>>> Even if you apply these patches, you cannot remove the physical memory
>>> completely since these patches are still under develop
On 07/10/2012 03:39 AM, Xu Jiucheng wrote:
> + crypto@3 {
> +status = "disabled";
> +};
Whitespace.
> +
> + mpic: pic@4 {
> + protected-sources = <
> + 16 /* ecm, mem, L2,
On Jul 10, 2012, at 10:31 AM, Scott Wood wrote:
> On 07/10/2012 01:13 AM, Liu Shengzhou-B36685 wrote:
>>
>>
>>> -Original Message-
>>> From: Wood Scott-B07421
>>> Sent: Tuesday, July 10, 2012 12:39 AM
>>> To: Liu Shengzhou-B36685
>>> Cc: bhelg...@google.com; linux-...@vger.kernel.org; l
On 07/10/2012 01:13 AM, Liu Shengzhou-B36685 wrote:
>
>
>> -Original Message-
>> From: Wood Scott-B07421
>> Sent: Tuesday, July 10, 2012 12:39 AM
>> To: Liu Shengzhou-B36685
>> Cc: bhelg...@google.com; linux-...@vger.kernel.org; linuxppc-
>> d...@lists.ozlabs.org
>> Subject: Re: [PATCH] P
On Mar 30, 2012, at 12:38 AM, Shawn Guo wrote:
> Freescale PowerPC SoCs share a number of IP blocks with Freescale
> ARM/IMX SoCs, FlexCAN, SSI, FEC, eSDHC, USB, etc. There are some
> effort consolidating those drivers to make them work for both
> architectures.
>
> One outstanding difference b
On Jul 10, 2012, at 2:52 AM, Zhicheng wrote:
> From: Zhicheng Fan
>
> Signed-off-by: Zhicheng Fan
> ---
> arch/powerpc/boot/dts/fsl/p1021si-post.dtsi | 16 ++-
> arch/powerpc/boot/dts/p1025rdb.dtsi | 40 +++
> 2 files changed, 55 insertions(+), 1 delet
On Tue, Jul 10, 2012 at 3:39 AM, Xu Jiucheng wrote:
> Create the dts files for each core and splits the devices between
> the two cores for P1021RDB-PC.
>
> Core0 has l2, serial0, i2c, spi, gpio, tdm,dma, usb, eth0, eth1,
> sdhc, crypto, global-util, message, pci0, pci1, msi, crypto.
> Core1 has l
On Nov 11, 2011, at 10:05 AM, Kokoris, Ioannis wrote:
> Hi,
>
> QE Microcode Initialization using qe_upload_microcode() does not work on
> P1021 if the IRAM-Ready register is not set after the microcode upload. This
> patch adds a definition for the "I-RAM Ready" register and sets it uppon
>
On Jul 10, 2012, at 1:08 AM, Jia Hongtao wrote:
> With 2-cell format interrupts of MSI PCIe ethernet card can not work.
>
> Signed-off-by: Li Yang
> Signed-off-by: Jia Hongtao
> ---
> arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts |8
> arch/powerpc/boot/dts/mpc8572ds_camp_core1.dt
On Jul 10, 2012, at 1:08 AM, Jia Hongtao wrote:
> The issue log on core1 is:
> root@mpc8572ds:~# ifconfig eth0 10.192.208.244
> net eth0: could not attach to PHY
> SIOCSIFFLAGS: No such device
>
> To attach PHY node mdio@24520 should not be disabled in dts of core1.
> Because all PHYs are contro
On May 11, 2012, at 12:33 AM, Shaohui Xie wrote:
> CONFIG_FSL_BOOKE is only defined in 32-bit, CONFIG_PPC_FSL_BOOK3E is
> defined in both 32-bit and 64-bit, so use CONFIG_PPC_FSL_BOOK3E to make
> driver work in 32-bit & 64-bit.
>
> Signed-off-by: Shaohui Xie
> ---
> changes for v2:
> use PPC_FS
On Jul 9, 2012, at 3:46 AM, Varun Sethi wrote:
> We should use the MPIC_LARG_VECTORS flag while intializing the MPIC.
> This prevents us from eating in to hardware vector number space (MSIs)
> while setting up internal sources.
>
> Signed-off-by: Varun Sethi
> ---
> arch/powerpc/sysdev/mpic.c
On Feb 29, 2012, at 7:20 PM, Olivia Yin wrote:
> From: Liu Yu
>
> So that we can call it when improving SPE switch like book3e did for fp
> switch.
>
> Signed-off-by: Liu Yu
> Signed-off-by: Olivia Yin
> ---
> v2: add Signed-off-by
>
> arch/powerpc/kernel/head_fsl_booke.S | 23 ++--
We need to use CONFIG_FSL_SOC_BOOKE instead of CONFIG_PPC_85xx as
CONFIG_PPC_85xx isn't defined when we build support for 64-bit embedded
FSL PPC SoCs.
Signed-off-by: Kumar Gala
---
drivers/usb/host/ehci-fsl.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/
On Jul 10, 2012, at 3:39 AM, Xu Jiucheng wrote:
> P1021RDB-PC Overview
> -
> 1Gbyte DDR3 (on board DDR)
> 16Mbyte NOR flash
> 32Mbyte eSLC NAND Flash
> 256 Kbit M24256 I2C EEPROM
> 128 Mbit SPI Flash memory
> Real-time clock on I2C bus
> SD/MMC connector to interface with the SD m
On Jul 10, 2012, at 4:39 AM, Sethi Varun-B16395 wrote:
>
>
>> -Original Message-
>> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
>> Sent: Tuesday, July 10, 2012 7:17 AM
>> To: Wood Scott-B07421
>> Cc: Sethi Varun-B16395; Hamciuc Bogdan-BHAMCIU1; linuxppc-
>> d...@lists.ozlabs.org
On Jul 10, 2012, at 5:40 AM, Shengzhou Liu wrote:
> * Enable USB, MMC, SATA, MTD, NAND, PAMU, RTC
> * Enable FSL RAID on P5020
> * Enable general RAID features (MD + async-tx)
> * Enable RTC on P2041RDB
> * Enable UIO SRIO & UIO DMA
> * Enable USDPAA SHMEM driver
> * Enable ePAPR HV support
> * E
On Jul 10, 2012, at 5:40 AM, Shengzhou Liu wrote:
> * Enable NAND, MSI, PAMU,
> * Enable FSL RAID on P5020
> * Enable general RAID features (MD + async-tx)
> * Enable RTC on P2041RDB
> * Enable UIO SRIO & UIO DMA
>
> Signed-off-by: Harninder Rai
> Signed-off-by: Shaohui Xie
> Signed-off-by: Mi
On Jul 10, 2012, at 6:40 AM, Kumar Gala wrote:
>
> On Jul 10, 2012, at 5:22 AM, Xie Shaohui-B21989 wrote:
>
>> Hi, All,
>>
>> Is there any concern for this patch, it's been a long time.
>> Thanks!
>>
>>
>> Best Regards,
>> Shaohui Xie
>
> As commented, we should use PPC_FSL_BOOK3E, not CO
On Jul 10, 2012, at 5:22 AM, Xie Shaohui-B21989 wrote:
> Hi, All,
>
> Is there any concern for this patch, it's been a long time.
> Thanks!
>
>
> Best Regards,
> Shaohui Xie
As commented, we should use PPC_FSL_BOOK3E, not CONFIG_PPC_FSL_BOOK3E.
- k
>
>
>> -Original Message-
>> F
On May 8, 2012, at 10:46 PM, Bhushan Bharat-R65777 wrote:
>> .org] On Behalf Of Shaohui Xie
>> Sent: Tuesday, May 08, 2012 11:37 AM
>> To: linux-watch...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
>> Cc: Xie Shaohui-B21989
>> Subject: [PATCH 1/2] powerpc/watchdog: move boo
Create the dts files for each core and splits the devices between
the two cores for P1021RDB-PC.
Core0 has l2, serial0, i2c, spi, gpio, tdm,dma, usb, eth0, eth1,
sdhc, crypto, global-util, message, pci0, pci1, msi, crypto.
Core1 has l2, serial1, eth2.
Signed-off-by: Xu Jiucheng
Signed-off-by: Ma
P1021RDB-PC Overview
-
1Gbyte DDR3 (on board DDR)
16Mbyte NOR flash
32Mbyte eSLC NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
Real-time clock on I2C bus
SD/MMC connector to interface with the SD memory card
PCIex
- x1 PCIe slot or x1 PCIe to dual SATA cont
* Enable USB, MMC, SATA, MTD, NAND, PAMU, RTC
* Enable FSL RAID on P5020
* Enable general RAID features (MD + async-tx)
* Enable RTC on P2041RDB
* Enable UIO SRIO & UIO DMA
* Enable USDPAA SHMEM driver
* Enable ePAPR HV support
* Enable PCI-E support
Signed-off-by: Haiying Wang
Signed-off
* Enable NAND, MSI, PAMU,
* Enable FSL RAID on P5020
* Enable general RAID features (MD + async-tx)
* Enable RTC on P2041RDB
* Enable UIO SRIO & UIO DMA
Signed-off-by: Harninder Rai
Signed-off-by: Shaohui Xie
Signed-off-by: Minghuan Lian
Signed-off-by: Kumar Gala
Signed-off-by: Shengzhou Liu
* Enable NAND, MSI, PAMU,
* Enable FSL RAID on P5020
* Enable general RAID features (MD + async-tx)
* Enable RTC on P2041RDB
* Enable UIO SRIO & UIO DMA
Signed-off-by: Harninder Rai
Signed-off-by: Shaohui Xie
Signed-off-by: Minghuan Lian
Signed-off-by: Kumar Gala
Signed-off-by: Shengzhou Liu
Hi, All,
Is there any concern for this patch, it's been a long time.
Thanks!
Best Regards,
Shaohui Xie
>-Original Message-
>From: Xie Shaohui-B21989
>Sent: Friday, May 11, 2012 1:34 PM
>To: linux-watch...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
>Cc: Xie Shaohui-B21989
>Subject
Hi, All,
Is there any concern for this patch, it's been a long time.
Thanks!
Best Regards,
Shaohui Xie
>-Original Message-
>From: Xie Shaohui-B21989
>Sent: Tuesday, May 08, 2012 2:07 PM
>To: linux-watch...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
>Cc: Xie Shaohui-B21989
>Subjec
Hi Christoph,
2012/07/10 0:18, Christoph Lameter wrote:
On Mon, 9 Jul 2012, Yasuaki Ishimatsu wrote:
Even if you apply these patches, you cannot remove the physical memory
completely since these patches are still under development. I want you to
cooperate to improve the physical memory hot-re
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Tuesday, July 10, 2012 7:17 AM
> To: Wood Scott-B07421
> Cc: Sethi Varun-B16395; Hamciuc Bogdan-BHAMCIU1; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH 3/3 v2] powerpc/mpic: FSL MPIC error interru
>
> > + u32 eisr, eimr;
> > + int errint;
> > + unsigned int cascade_irq;
> > +
> > + eisr = fsl_mpic_err_read(mpic->err_regs, eisr_offset);
> > + eimr = fsl_mpic_err_read(mpic->err_regs, eimr_offset);
> > +
> > + if (!(eisr & ~eimr))
> > + return IRQ_NONE;
> > +
> > + wh
Hi Linus !
It looks like my rewrite of our lazy irq scheme is still exposing
"interesting" issues left and right. The previous fixes are now
causing an occasional BUG_ON to trigger (which this patch turns
into a WARN_ON while at it), due to another issue of disconnect
of the lazy irq state vs. the
On 07/10/2012 04:22 PM, tiejun.chen wrote:
> On 07/10/2012 04:19 PM, Benjamin Herrenschmidt wrote:
>> On Tue, 2012-07-10 at 15:59 +0800, Tiejun Chen wrote:
>>> Add "memory" attribute in inline assembly language as a compiler
>>> barrier to make sure 4.6.x GCC don't reorder mfmsr().
>>
>> Out of cur
On 07/10/2012 04:19 PM, Benjamin Herrenschmidt wrote:
> On Tue, 2012-07-10 at 15:59 +0800, Tiejun Chen wrote:
>> Add "memory" attribute in inline assembly language as a compiler
>> barrier to make sure 4.6.x GCC don't reorder mfmsr().
>
> Out of curiosity, did you see a case where it was re-ordere
> - hard_irq_disable();
> - if (!lazy_irq_pending())
> + if (prep_irq_for_idle()) {
> cede_processor();
> +#ifdef CONFIG_TRACE_IRQFLAG
this is IRQFLAGS (missing "S"). I'll fix it while I commit, the same
typo is in another place in irq.c as well, I'll commit a fix for th
On Tue, 2012-07-10 at 15:59 +0800, Tiejun Chen wrote:
> Add "memory" attribute in inline assembly language as a compiler
> barrier to make sure 4.6.x GCC don't reorder mfmsr().
Out of curiosity, did you see a case where it was re-ordered
improperly ?
Cheers,
Ben.
> Signed-off-by: Tiejun Chen
>
From: Zhicheng Fan
Signed-off-by: Zhicheng Fan
---
arch/powerpc/boot/dts/fsl/p1021si-post.dtsi | 16 ++-
arch/powerpc/boot/dts/p1025rdb.dtsi | 40 +++
2 files changed, 55 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-po
Add "memory" attribute in inline assembly language as a compiler
barrier to make sure 4.6.x GCC don't reorder mfmsr().
Signed-off-by: Tiejun Chen
---
arch/powerpc/include/asm/reg.h |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/po
On Tue, 2012-07-10 at 16:10 +1000, Michael Neuling wrote:
> Benjamin Herrenschmidt wrote:
>
> > Looks like we still have issues with pSeries and Cell idle code
> > vs. the lazy irq state. In fact, the reset fixes that went upstream
> > are exposing the problem more by causing BUG_ON() to trigger
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