On Jul 10, 2012, at 3:39 AM, Xu Jiucheng wrote: > P1021RDB-PC Overview > ----------------- > 1Gbyte DDR3 (on board DDR) > 16Mbyte NOR flash > 32Mbyte eSLC NAND Flash > 256 Kbit M24256 I2C EEPROM > 128 Mbit SPI Flash memory > Real-time clock on I2C bus > SD/MMC connector to interface with the SD memory card > PCIex > - x1 PCIe slot or x1 PCIe to dual SATA controller > - x1 mini-PCIe slot > USB 2.0 > - ULPI PHY interface: SMSC USB3300 USB PHY and Genesys Logic’s GL850A > - Two USB2.0 Type A receptacles > - One USB2.0 signal to Mini PCIe slot > eTSEC1: Connected to RGMII PHY VSC7385 > eTSEC2: Connected to SGMII PHY VSC8221 > eTSEC3: Connected to SGMII PHY AR8021 > DUART interface: supports two UARTs up to 115200 bps for console display > > Signed-off-by: Xu Jiucheng <jiucheng...@freescale.com> > Signed-off-by: Matthew McClintock <m...@freescale.com> > --- > arch/powerpc/boot/dts/p1021rdb-pc.dtsi | 236 +++++++++++++++++++++++++++++ > arch/powerpc/boot/dts/p1021rdb-pc_32b.dts | 96 ++++++++++++ > arch/powerpc/boot/dts/p1021rdb-pc_36b.dts | 96 ++++++++++++ > arch/powerpc/boot/dts/p1021rdb.dts | 96 ------------ > arch/powerpc/boot/dts/p1021rdb.dtsi | 236 ----------------------------- > arch/powerpc/boot/dts/p1021rdb_36b.dts | 96 ------------ > 6 files changed, 428 insertions(+), 428 deletions(-) > create mode 100644 arch/powerpc/boot/dts/p1021rdb-pc.dtsi > create mode 100644 arch/powerpc/boot/dts/p1021rdb-pc_32b.dts > create mode 100644 arch/powerpc/boot/dts/p1021rdb-pc_36b.dts > delete mode 100644 arch/powerpc/boot/dts/p1021rdb.dts > delete mode 100644 arch/powerpc/boot/dts/p1021rdb.dtsi > delete mode 100644 arch/powerpc/boot/dts/p1021rdb_36b.dts
Do we really need a 32 & 36 bit device tree for this board? Isnt the memory fixed so why not just have 32b? Also, why are you removing the dts for the older P1021RDB?? - k _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
