From: Liu Shuo
Fix the compatible string of sec 4.0 to match with CAMM driver according
to Documentation/devicetree/bindings/crypto/fsl-sec4.txt
Signed-off-by: Liu Shuo
Signed-off-by: Shengzhou Liu
---
v2: refine description.
arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi | 10 +-
1 f
Seth,
> Thanks for the help! I was wondering if you could take a look at something
> for me.
>
> I've been working on this staging driver (zsmalloc memory allocator)
> that does virtual mapping of two pages.
>
> I have a github repo with the driver and the unsubmitted changes. I'm
> trying to
On Wed, 2012-03-07 at 14:49 +1100, Benjamin Herrenschmidt wrote:
> On Tue, 2012-03-06 at 10:26 +0100, masterzorag wrote:
> > I'm running my test program, it uses all available spus to compute via
> > OpenCL
> > kernel 3.2.5 on a ps3
> > even on testing spu directly, it crashes
>
> I think the pat
On Tue, 2012-03-06 at 10:26 +0100, masterzorag wrote:
> I'm running my test program, it uses all available spus to compute via
> OpenCL
> kernel 3.2.5 on a ps3
> even on testing spu directly, it crashes
I think the patch is not 100% right yet. Looking at the code, we
have a real mess of who gets
On Tuesday, March 06, 2012 3:35 PM, Russell King wrote:
>
> Now that we have the completed cookie in the dma_chan structure, we
> can consolidate the tx_status functions by providing a function to set
> the txstate structure and returning the DMA status. We also provide
> a separate helper to set
Normal PCI enumeration via PCI config space uses __pci_read_base(), where
the PCI core applies any bus-to-resource offset. But powerpc doesn't use
that path when enumerating via the device tree.
This adds the corresponding bus-to-resource conversion in the paths that
read BAR values from the OF d
Make sure we compute CPU addresses (resource start/end) the same way both
when we set up the I/O aperture (hose->io_resource) and when we use
pcibios_bus_to_resource() to convert BAR values into resources.
CC: Benjamin Herrenschmidt
CC: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Bjorn Helgaas
On Tuesday, March 06, 2012 3:35 PM, Russell King wrote:
>
> Provide a common function to do the cookie mechanics for completing
> a DMA descriptor.
>
> Signed-off-by: Russell King
> ---
> drivers/dma/dmaengine.h | 18 ++
> drivers/dma/ep93xx_dma.c|2 +-
> dif
On Tuesday, March 06, 2012 3:35 PM, Russell King wrote:
>
> Everyone deals with assigning DMA cookies in the same way (it's part of
> the API so they should be), so lets consolidate the common code into a
> helper function to avoid this duplication.
>
> Signed-off-by: Russell King
> ---
> driv
On Tuesday, March 06, 2012 3:34 PM, Russell King wrote:
>
> Add a local private header file to contain definitions and declarations
> which should only be used by DMA engine drivers.
>
> We also fix linux/dmaengine.h to use LINUX_DMAENGINE_H to guard against
> multiple inclusion.
>
> Signed-off-by:
On Tuesday, March 06, 2012 3:34 PM, Russell King wrote:
>
> Every DMA engine implementation declares a last completed dma cookie
> in their private dma channel structures. This is pointless, and
> forces driver specific code. Move this out into the common dma_chan
> structure.
>
> Signed-off-by:
Add a local private header file to contain definitions and declarations
which should only be used by DMA engine drivers.
We also fix linux/dmaengine.h to use LINUX_DMAENGINE_H to guard against
multiple inclusion.
Signed-off-by: Russell King
---
drivers/dma/amba-pl08x.c|2 ++
drivers/dma
Ensure all DMA engine drivers initialize their cookies in the same way,
so that they all behave in a similar fashion. This means their first
issued cookie will be 2 rather than 1, and will increment to INT_MAX
before returning 1 and starting over.
In connection with this, Dan Williams said:
> Rus
Now that we have the completed cookie in the dma_chan structure, we
can consolidate the tx_status functions by providing a function to set
the txstate structure and returning the DMA status. We also provide
a separate helper to set the residue for cookies which are still in
progress.
Signed-off-b
Provide a common function to do the cookie mechanics for completing
a DMA descriptor.
Signed-off-by: Russell King
---
drivers/dma/amba-pl08x.c|2 +-
drivers/dma/at_hdmac.c |2 +-
drivers/dma/coh901318.c |2 +-
drivers/dma/dmaengine.h | 18 ++
driver
Everyone deals with assigning DMA cookies in the same way (it's part of
the API so they should be), so lets consolidate the common code into a
helper function to avoid this duplication.
Signed-off-by: Russell King
---
drivers/dma/amba-pl08x.c|9 +++--
drivers/dma/at_hdmac.c |
Every DMA engine implementation declares a last completed dma cookie
in their private dma channel structures. This is pointless, and
forces driver specific code. Move this out into the common dma_chan
structure.
Signed-off-by: Russell King
---
arch/arm/include/asm/hardware/iop_adma.h |2 --
[v2 - more or less same description. Including lakml in cc for the full
set]
This patch series cleans up the handling of cookies in DMA engine drivers.
This is done by providing a set of inline library functions for common
tasks:
- moving the 'last completed cookie' into struct dma_chan - everyo
On Tue, Mar 6, 2012 at 5:08 PM, David Miller wrote:
> From: Duc Dang
> Date: Mon, 5 Mar 2012 17:57:42 +0700
>
>> This compatible value will be used to distinguish some special features of
>> APM821XX EMAC: no half duplex mode support, configuring jumbo frame.
>>
>> Signed-off-by: Duc Dang
>
>
From: Duc Dang
Date: Mon, 5 Mar 2012 17:58:22 +0700
> This patch includes:
>
> Configure EMAC PHY clock source (clock from PHY or internal clock).
>
> Do not advertise PHY half duplex capability as APM821XX EMAC does not
> support half duplex mode.
>
> Add changes to support configuri
From: Duc Dang
Date: Mon, 5 Mar 2012 17:57:42 +0700
> This compatible value will be used to distinguish some special features of
> APM821XX EMAC: no half duplex mode support, configuring jumbo frame.
>
> Signed-off-by: Duc Dang
Applied.
___
Linuxpp
On Mar 5, 2012, at 8:20 AM, Liu Gang wrote:
> Hi, Kumar,
>
> On Fri, 2012-03-02 at 09:11 -0600, Kumar Gala wrote:
>>> diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
>>> index 1548578..468011e 100644
>>> --- a/arch/powerpc/sysdev/fsl_rmu.c
>>> +++ b/arch/powerpc/sysdev
On Tue, 6 Mar 2012 15:21:16 +0800
Shengzhou Liu wrote:
> From: Liu Shuo
>
> Fix the compatible string of sec 4.0 to match with CAMM driver according
> to the documentation file
> Documentation/devicetree/bindings/crypto/fsl-sec4.txt.
s/the documentation file//, since it's pretty obvious from
On Tue, Mar 06, 2012 at 05:05:07PM +0800, Zhao Chenhui wrote:
> Signed-off-by: Zhao Chenhui
> ---
> include/linux/pci_ids.h |1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 31d77af..8f026c0 100644
> --- a/incl
On Mon, March 05, 2012 9:58 PM, Liu Gang wrote:
> Subject: [PATCH] powerpc/srio: Fix the relocation errors when building
> with 64bit
>
> For the file "arch/powerpc/sysdev/fsl_rio.c", there will be some
> relocation errors while using the corenet64_smp_defconfig:
>
> WARNING: modpost: Found 6 sec
On Tue, Mar 6, 2012 at 1:19 PM, Kumar Gala wrote:
> On Feb 28, 2012, at 4:22 AM, Martyn Welch wrote:
>
>> Move the GE GPIO and PIC drivers to allow these to be used by non-86xx
>> boards.
>
> gpio driver should be in drivers/gpio. Please split that move out as a
> separate patch for Grant & Linu
On Feb 28, 2012, at 4:22 AM, Martyn Welch wrote:
> Move the GE GPIO and PIC drivers to allow these to be used by non-86xx
> boards.
>
> Signed-off-by: Martyn Welch
> ---
>
> v2: Move GPIO and PIC drivers to sysdev/ge/ rather than platforms/.
>
> arch/powerpc/platforms/86xx/Kconfig
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao
>
> Remove FPGA(CADMUS) macros in code. Move it to dts.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
Timur,
Do you mind reviewing & ack'ing.
- k
> arch/powerpc/boot/dts/mpc8548cds.dts |8 -
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao
>
> There is a PCI bridge(Tsi310) between the MPC8548 and a VIA
> southbridge chip.
>
> The bootloader sets the PCI bridge to open a window from 0x
> to 0x1fff on the PCI I/O space. But the kernel can't set the I/O
> reso
On Mar 6, 2012, at 3:05 AM, Zhao Chenhui wrote:
> Signed-off-by: Zhao Chenhui
> ---
> include/linux/pci_ids.h |1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
Just merge this with the 2nd patch that actually uses the ID.
- k
___
Linuxppc-d
On Mar 6, 2012, at 3:10 AM, Zhao Chenhui wrote:
> + if ((fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E)) &&
Should this also have 8547, 8547E, 8545, 8545E, 8543, & 8543E?
> + !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
> + early_read_co
On Mar 6, 2012, at 1:21 AM, Shengzhou Liu wrote:
> From: Liu Shuo
>
> Fix the compatible string of sec 4.0 to match with CAMM driver according
> to the documentation file
> Documentation/devicetree/bindings/crypto/fsl-sec4.txt.
>
> Signed-off-by: Liu Shuo
> Signed-off-by: Shengzhou Liu
> --
I'm running my test program, it uses all available spus to compute via
OpenCL
kernel 3.2.5 on a ps3
even on testing spu directly, it crashes
=
[ BUG: bad unlock balance detected! ]
-
test/1067 is trying to release lock (&sb
> Issue:
> Applications using lwarx/stwcx instructions in the core to
> compete for a software lock or semaphore with a device on
> RapidIO using read atomic set, clr, inc, or dec in a similar
> manner may falsely result in both masters seeing the lock
> as "available". This could result in data
From: chenhui zhao
Issue:
Applications using lwarx/stwcx instructions in the core to
compete for a software lock or semaphore with a device on
RapidIO using read atomic set, clr, inc, or dec in a similar
manner may falsely result in both masters seeing the lock
as "available". This could result i
From: chenhui zhao
Issue:
The register bits ERR_DR[OWMSV] and ERR_DR[ORMSV] can erroneously set and
may trigger an interrupt if capturing and reporting of these events are enabled.
Workaround:
Disable OWMSV, ORMSV error capture and disable OWMSV, ORMSV error reporting.
Do not affect the function
From: chenhui zhao
Issue:
As a master, the PCI IP block can combine a memory write to the last PCI double
word (4 bytes) of a cacheline with a 4 byte memory write to the first PCI double
word of the subsequent cacheline. This affects 32-bit PCI target devices that
blindly assert STOP on memory-wr
From: chenhui zhao
The workarounds need to detect the cpu type. Add these macros
and inline routines to help cpu type detection in runtime.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
---
arch/powerpc/include/asm/mpc85xx.h | 72
1 files changed, 7
Create mpc8548cds_36b.dts. Support 36-bit mode.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
---
arch/powerpc/boot/dts/mpc8548cds_36b.dts | 86 ++
1 files changed, 86 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mpc8548cds_36b.dts
* Create mpc8548cds.dtsi.
* Move lbc, soc and pci0 nodes to mpc8548cds_32b.dtsi.
* Change cuImage.mpc8548cds to cuImage.mpc8548cds_32b.
* Rename mpc8548cds.dts to mpc8548cds_32b.dts.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
Signed-off-by: Timur Tabi
---
arch/powerpc/boot/Makefile
Correct ethernet1 and add ethernet2 and ethernet3.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
---
arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
b/arch/powerpc/boot/dt
From: chenhui zhao
Enable RapidIO and add rapidio and rmu nodes to dts.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
---
arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi | 16
arch/powerpc/boot/dts/mpc8548cds.dts |7 +++
arch/powerpc/platforms/85xx/Kconf
From: chenhui zhao
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
---
arch/powerpc/boot/dts/mpc8548cds.dts | 40 +-
1 files changed, 39 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts
b/arch/powerpc/boot/dts/mpc8548cds.dts
From: chenhui zhao
Remove FPGA(CADMUS) macros in code. Move it to dts.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
---
arch/powerpc/boot/dts/mpc8548cds.dts |8 -
arch/powerpc/platforms/85xx/mpc85xx_cds.c | 50 +++-
2 files changed, 41 insertions(+
From: chenhui zhao
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
---
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index 5f88797..2503cef 10064
From: chenhui zhao
There is a PCI bridge(Tsi310) between the MPC8548 and a VIA
southbridge chip.
The bootloader sets the PCI bridge to open a window from 0x
to 0x1fff on the PCI I/O space. But the kernel can't set the I/O
resource. In the routine pci_read_bridge_io(), if the base which
is re
Signed-off-by: Zhao Chenhui
---
include/linux/pci_ids.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 31d77af..8f026c0 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -484,6 +484,7 @@
#define
On Mon, Mar 05, 2012 at 06:12:50PM -0600, H Hartley Sweeten wrote:
> On Monday, March 05, 2012 1:17 PM, Russell King wrote:
> > diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
> > index 47e0997..244a2c5 100644
> > --- a/drivers/dma/dmaengine.h
> > +++ b/drivers/dma/dmaengine.h
> > @@
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