On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao <chenhui.z...@freescale.com>
>
> There is a PCI bridge(Tsi310) between the MPC8548 and a VIA
> southbridge chip.
>
> The bootloader sets the PCI bridge to open a window from 0x0000
> to 0x1fff on the PCI I/O space. But the kernel can't set the I/O
> resource. In the routine pci_read_bridge_io(), if the base which
> is read from PCI_IO_BASE is equal to zero, the routine don't set
> the I/O resource of the child bus.
>
> To allow the legacy I/O space on the VIA southbridge to be accessed,
> use the fixup to fix the PCI I/O space of the PCI bridge.
>
> Signed-off-by: Zhao Chenhui <chenhui.z...@freescale.com>
> Signed-off-by: Li Yang <le...@freescale.com>
> ---
> arch/powerpc/platforms/85xx/mpc85xx_cds.c | 29 +++++++++++++++++++++++++++--
> 1 files changed, 27 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
> b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
> index 40f03da..c009c5b 100644
> --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
> @@ -3,7 +3,7 @@
> *
> * Maintained by Kumar Gala (see MAINTAINERS for contact information)
> *
> - * Copyright 2005 Freescale Semiconductor Inc.
> + * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
> *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms of the GNU General Public License as published by the
> @@ -158,6 +158,31 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff,
> skip_fake_bridge);
> DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
> DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
>
> +/*
> + * Fix Tsi310 PCI-X bridge resource.
> + * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O space.
> + * This allows legacy I/O(i8259, etc) on the VIA southbridge to be accessed.
> + */
This comment and the code don't make sense. Why is the bridge described as
Tsi310 in comments but the vendor ID is IBM ?
> +void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
> +{
> + struct pci_dev *dev = bus->self;
> + struct resource *res = bus->resource[0];
> +
> + if (dev != NULL &&
> + dev->vendor == PCI_VENDOR_ID_IBM &&
> + dev->device == PCI_DEVICE_ID_IBM_PCIX_BRIDGE) {
> + if (res) {
> + res->start = 0;
> + res->end = 0x1fff;
> + res->flags = IORESOURCE_IO;
> + pr_info("mpc85xx_cds: PCI bridge resource fixup
> applied\n");
> + pr_info("mpc85xx_cds: %pR\n", res);
> + }
> + }
> +
> + fsl_pcibios_fixup_bus(bus);
> +}
> +
> #ifdef CONFIG_PPC_I8259
> static void mpc85xx_8259_cascade_handler(unsigned int irq,
> struct irq_desc *desc)
> @@ -323,7 +348,7 @@ define_machine(mpc85xx_cds) {
> .get_irq = mpic_get_irq,
> #ifdef CONFIG_PCI
> .restart = mpc85xx_cds_restart,
> - .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
> + .pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
> #else
> .restart = fsl_rstcr_restart,
> #endif
> --
> 1.6.4.1
>
>
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