[PATCH 27/29] powerpc/85xx: Rework P3060QDS device tree

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p3060-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-ep

[PATCH 25/29] powerpc/85xx: Rework P2041RDB device tree

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p2041-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-ep

[PATCH 24/29] powerpc/85xx: Rework P2020RDB device tree

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes

[PATCH 23/29] powerpc/85xx: Rework P2020DS device tree

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes

[PATCH 22/29] powerpc/85xx: Rework P1023RDS device tree

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Dropping "fsl,p1023-

[PATCH 21/29] powerpc/85xx: Rework P1022DS device tree

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Changed GP

[PATCH 20/29] powerpc/85xx: Rework P1021MDS device tree

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes

[PATCH 19/29] powerpc/85xx: Add P1020RDB 36-bit address map device tree

Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/p1020rdb_36b.dts | 66 1 files changed, 66 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/p1020rdb_36b.dts diff --git a/arch/powerpc/boot/dts/p1020rdb_36b.dts b/arch/powerpc/boot/dts/

[PATCH 18/29] powerpc/85xx: Rework P1020RDB device tree

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio no

[PATCH 17/29] powerpc/85xx: Add a P1010RDB 36-bit address map device tree

Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/p1010rdb_36b.dts | 89 1 files changed, 89 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/p1010rdb_36b.dts diff --git a/arch/powerpc/boot/dts/p1010rdb_36b.dts b/arch/powerpc/boot/dts/

[PATCH 14/29] powerpc/85xx: Rework P1010RDB and P1010 device tree

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Dropping "fsl,p1010-

[PATCH 16/29] powerpc/85xx: Add crypto engine to P1010 SoC device tree

Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/fsl/p1010si-post.dtsi |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi index 75eb921..bd9e163 100644 --- a/arch/powerpc/boot/dts/f

[PATCH 15/29] powerpc/85xx: Add RTC to P1010RDB device tree

Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/p1010rdb.dtsi |7 +++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/boot/dts/p1010rdb.dtsi b/arch/powerpc/boot/dts/p1010rdb.dtsi index 149d196..3aa2b82 100644 --- a/arch/powerpc/boot/dts/p1010rdb.dtsi +++ b

[PATCH 12/29] powerpc/85xx: Rework MPC8569MDS device tree

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell

[PATCH 11/29] powerpc/85xx: Rework MPC8568MDS device tree

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell

[PATCH 10/29] powerpc/85xx: Rework MPC8548CDS device trees

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell

[PATCH 09/29] powerpc/85xx: Rework MPC8544DS device tree

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell

[PATCH 08/29] powerpc/85xx: Rework MPC8536DS device trees

Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Added localbus node,

[PATCH 04/29] powerpc/85xx: Update P1020 SEC3.3 node to match actual SoC HW

Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/p1020si.dtsi |9 + 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi index 25e10cf..5514e1d 100644 --- a/arch/powerpc/boot/dts/p1020si.dtsi +++ b/a

[PATCH 06/29] powerpc/85xx: p1020si.dtsi update interrupt handling

* set interrupt-parent at root so its not duplicate in every node * Add mpic timers * Move to 4-prop cells for mpic timer Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/p1020si.dtsi | 117 +--- 1 files changed, 56 insertions(+), 61 deletions(-) diff --git a

[PATCH 05/29] powerpc/85xx: Add ethernet magic packet property to P1020 device tree

All eTSEC2 controllers support waking on magic packet so fixup device tree to report that. Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/p1020si.dtsi |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020

[PATCH 01/29] powerpc/85xx: Simplify P1020RDB CAMP dts using includes

If we include the p1020rdb.dts instead of p1020si.dts we greatly reduce duplication and maintenance. We can just list which devices are disabled for the given core and mpic protected sources. Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/p1020rdb_camp_core0.dts | 154 +---

[PATCH 03/29] powerpc/85xx: Update SPI binding to match binding spec for P1020RDB

The SPI node is out of date with regards to the binding for fsl-espi and driver support. Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/p1020rdb.dts | 30 +- arch/powerpc/boot/dts/p1020si.dtsi |5 ++--- 2 files changed, 15 insertions(+), 20 deletions(-) di

[PATCH 02/29] powerpc/85xx: Rework PCI nodes on P1020RDB

* Move SoC specific details like irq mapping to SoC dtsi * Update interrupt property to cover both error interrupt and PCIe runtime interrupts Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/p1020rdb.dts | 26 +- arch/powerpc/boot/dts/p1020si.dtsi | 40 +

[PATCH][v2] powerpc/p1023: set IRQ[4:6, 11] to active-high level sensitive for PCIe

From: Roy Zang P1023 external IRQ[4:6, 11] are not pin out, but the interrupts are utilized by the PCIe controllers. As they are not exposed as pins we need to set them as active-high (internal to the SoC these interrupts are pulled down). IRQs[0:3,7:10] are pulled up on the board so we have th

[stable] [PATCH] powerpc/ptrace: Fix build with gcc 4.6

From: Benjamin Herrenschmidt powerpc/ptrace: Fix build with gcc 4.6 gcc (rightfully) complains that we are accessing beyond the end of the fpr array (we do, to access the fpscr). The only sane thing to do (whether anything in that code can be called remotely sane is debatable) is to special cas

Re: [PATCH net-next 0/5] Use ETH_ALEN

From: Joe Perches Date: Wed, 16 Nov 2011 11:38:01 -0800 > Remove other #defines and uses in favor of ETH_ALEN > > Joe Perches (5): > ethernet: Convert MAC_ADDR_LEN uses to ETH_ALEN > ethernet: Convert ETHER_ADDR_LEN uses to ETH_ALEN > bna: Convert MAC_ADDRLEN uses to ETH_ALEN > amd8111e:

[PATCH 4/5] crypto: talitos - support for channel remap and 2nd IRQ

Some later SEC v3.x are equipped with a second IRQ line. By correctly assigning IRQ affinity, this feature can be used to increase performance on dual core parts, like the MPC8572E and P2020E. The existence of the 2nd IRQ is determined from the device node's interrupt property. If present, the dr

Re: [PATCH v2 4/7] powerpc/85xx: add support to JOG feature using cpufreq interface

On 11/16/2011 03:55 AM, Zhao Chenhui wrote: > From: Li Yang > > Some 85xx silicons like MPC8536 and P1022 has the JOG PM feature. P1023 as well -- any plan to support? I see this in the p1022 and mpc8536 manuals: > The system operates as if a request to enter sleep mode has occurred, with > t

[PATCH 01/11] KVM: PPC: Add memory-mapping support for PCI passthrough and emulation

From: Benjamin Herrenschmidt This adds support for adding PCI device I/O regions to the guest memory map, and for trapping guest accesses to emulated MMIO regions and delivering them to qemu for MMIO emulation. To trap guest accesses to emulated MMIO regions, we reserve key 31 for the hypervisor

[RFC PATCH 09/11] KVM: PPC: Maintain a doubly-linked list of guest HPTEs for each gfn

This expands the reverse mapping array to contain two links for each HPTE which are used to link together HPTEs that correspond to the same guest logical page. Each circular list of HPTEs is pointed to by the rmap array entry for the guest logical page, pointed to by the relevant memslot. Links a

[RFC PATCH 0/11] KVM: PPC: Update Book3S HV memory handling

This series of patches updates the Book3S-HV KVM code that manages the guest hashed page table (HPT) to enable several things: * MMIO emulation and MMIO pass-through * Use of small pages (4kB or 64kB, depending on config) to back the guest memory * Pageable guest memory - i.e. backing pages ca

[PATCH 02/11] KVM: PPC: Keep a record of HV guest view of hashed page table entries

This adds an array that parallels the guest hashed page table (HPT), that is, it has one entry per HPTE, used to store the guest's view of the second doubleword of the corresponding HPTE. The first doubleword in the HPTE is the same as the guest's idea of it, so we don't need to store a copy, but

[PATCH 03/11] KVM: PPC: Allow use of small pages to back guest memory

From: Nishanth Aravamudan This puts the page frame numbers for the memory backing the guest in the slot->rmap array for each slot, rather than using the ram_pginfo array. Since the rmap array is vmalloc'd, we use real_vmalloc_addr() to access it when we access it in real mode in kvmppc_h_enter()

[RFC PATCH 06/11] KVM: PPC: Use Linux page tables in h_enter and map_vrma

This changes kvmppc_h_enter() and kvmppc_map_vrma to get the real page numbers that they put into the guest HPT from the Linux page tables for our userspace as an alternative to getting them from the slot_pfns arrays. In future this will enable us to avoid pinning all of guest memory on POWER7, bu

[RFC PATCH 07/11] KVM: PPC: Convert do_h_register_vpa to use Linux page tables

This makes do_h_register_vpa use a new helper function, kvmppc_pin_guest_page, to pin the page containing the virtual processor area that the guest wants to register. The logic of whether to use the userspace Linux page tables or the slot_pfns array is thus hidden in kvmppc_pin_guest_page. There

[RFC PATCH 08/11] KVM: PPC: Add a page fault handler function

This adds a kvmppc_book3s_hv_page_fault function that is capable of handling the fault we get if the guest tries to access a non-present page (one that we have marked with storage key 31 and no-execute), and either doing MMIO emulation, or making the page resident and rewriting the guest HPTE to po

[PATCH 05/11] KVM: PPC: Use a separate vmalloc'd array to store pfns

This changes the book3s_hv code to store the page frame numbers in a separate vmalloc'd array, pointed to by an array in struct kvm_arch, rather than the memslot->rmap arrays. This frees up the rmap arrays to be used later to store reverse mapping information. For large page regions, we now store

[RFC PATCH 10/11] KVM: PPC: Implement MMU notifiers

This implements the low-level functions called by the MMU notifiers in the generic KVM code, and defines KVM_ARCH_WANT_MMU_NOTIFIER if CONFIG_KVM_BOOK3S_64_HV so that the generic KVM MMU notifiers get included. That means we also have to take notice of when PTE invalidations are in progress, as in

[PATCH 04/11] KVM: PPC: Remove io_slot_pfn array

This stores the PFNs for I/O mappings in the slot->rmap array, as is now done for system RAM. This simplifies the h_enter code and allows us to remove the io_slot_pfn array. Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/kvm_host.h |2 -- arch/powerpc/kvm/book3s_hv.c|

[RFC PATCH 11/11] KVM: PPC: Eliminate global spinlock in kvmppc_h_enter

>From dfd5bcfac841f8a36593edf60d9fb15e0d633287 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Mon, 14 Nov 2011 13:30:38 +1100 Subject: Currently, kvmppc_h_enter takes a spinlock that is global to the guest, kvm->mmu_lock, in order to check for pending PTE invalidations safely. On some workl

Re: [RFC][PATCH 15/30] powerpc/85xx: Rework P1022DS device tree

On Nov 16, 2011, at 3:47 PM, Timur Tabi wrote: > wrote: >> I just noticed this bug in the original p1022ds.dts, and I see you're >> carrying it over here. The reg property should look like this: >> >> reg = <0xf 0xffe05000 0 0x1000>; >> ^^^ > > It looks like there's also a problem with t

Re: [RFC][PATCH 15/30] powerpc/85xx: Rework P1022DS device tree

wrote: > I just noticed this bug in the original p1022ds.dts, and I see you're > carrying it over here. The reg property should look like this: > > reg = <0xf 0xffe05000 0 0x1000>; >^^^ It looks like there's also a problem with the 'ranges' property: ranges = <0x0 0x0 0xf 0xe80

Re: [PATCH v2 3/7] powerpc/85xx: add sleep and deep sleep support

On 11/16/2011 03:55 AM, Zhao Chenhui wrote: > diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile > index ce4f7f1..d5cc385 100644 > --- a/arch/powerpc/kernel/Makefile > +++ b/arch/powerpc/kernel/Makefile > @@ -63,6 +63,7 @@ obj-$(CONFIG_CRASH_DUMP)+= crash_dump.o > ifeq ($

P4080: attempting to use the uio_pdrv to attach FPGA on localbus ...

I have succeeded in using the i2c bus with GPIO expander to access the programming pins of my FPGA devices, but the data port uses the localbus. I had initially thought that the uio platform driver would be the ideal approach to creating a device which would allow configuration from userland vi

Re: [RFC PATCH 0/2] powerpc: CPU cache op cleanup

On Nov 15, 2011, at 23:40, Paul Mackerras wrote: > On Tue, Nov 15, 2011 at 04:45:18PM -0600, Moffett, Kyle D wrote: >> >> I guess that's doable, although I have to admit that idea almost gives >> me more of a headache than trying to fix up the 32-bit ASM. >> >> One thing that bothers me in partic

Re: [PATCH v2 2/7] powerpc/85xx: add HOTPLUG_CPU support

On 11/16/2011 03:55 AM, Zhao Chenhui wrote: > +static void __cpuinit smp_85xx_mach_cpu_die(void) > +{ > + unsigned int cpu = smp_processor_id(); > + register u32 tmp; > + > + local_irq_disable(); > + idle_task_exit(); > + generic_set_cpu_dead(cpu); > + mb(); > + > + mtsp

Re: [PATCH v2 1/7] powerpc/85xx: re-enable timebase sync disabled by KEXEC patch

On 11/16/2011 03:55 AM, Zhao Chenhui wrote: > From: Li Yang > > The timebase sync is not only necessary when using KEXEC. It should also > be used by normal boot up and cpu hotplug. Remove the ifdef added by > the KEXEC patch. Again, no it should not be used by normal boot up (whether KEXEC supp

Re: [PATCH 4/5, v3] powerpc/8xxx: Update device tree bus probe for new RapidIO node binding

On Nov 16, 2011, at 7:48 AM, Bounine, Alexandre wrote: >> -Original Message- >> From: Liu Gang [mailto:gang@freescale.com] >> Sent: Saturday, November 12, 2011 7:03 AM >> To: linuxppc-dev@lists.ozlabs.org; Bounine, Alexandre >> Cc: a...@linux-foundation.org; linux-ker...@vger.kernel.o

Re: [PATCH 3/5,v3] powerpc/85xx: Update SRIO device tree nodes

On Nov 12, 2011, at 6:02 AM, Liu Gang wrote: > From: Kumar Gala > > Update all dts files that support SRIO controllers to match the new > fsl,srio device tree binding. > > Signed-off-by: Kumar Gala > --- > arch/powerpc/boot/dts/mpc8568mds.dts | 66 ++--- > arch/powe

Re: [PATCH 2/5, v3] fsl-rio: Add two ports and rapidio message units support

On Nov 16, 2011, at 7:39 AM, Bounine, Alexandre wrote: >> -Original Message- >> From: linuxppc-dev-bounces+alexandre.bounine=idt@lists.ozlabs.org >> [mailto:linuxppc-dev- >> bounces+alexandre.bounine=idt@lists.ozlabs.org] On Behalf Of Liu >> Gang >> Sent: Saturday, November 12, 20

Re: [PATCH 1/5, v3] fsl-rio: Split rio driver into two parts, RapidIO endpoint and message unit

On Nov 16, 2011, at 7:36 AM, Bounine, Alexandre wrote: >> -Original Message- >> From: Liu Gang [mailto:gang@freescale.com] >> Sent: Saturday, November 12, 2011 7:02 AM >> To: linuxppc-dev@lists.ozlabs.org; Bounine, Alexandre >> Cc: a...@linux-foundation.org; linux-ker...@vger.kernel.o

Re: [PATCH 5/5, v3] powerpc/fsl: Document rapidio node binding-information

On Nov 16, 2011, at 7:49 AM, Bounine, Alexandre wrote: >> -Original Message- >> From: Liu Gang [mailto:gang@freescale.com] >> Sent: Saturday, November 12, 2011 7:03 AM >> To: linuxppc-dev@lists.ozlabs.org; Bounine, Alexandre >> Cc: a...@linux-foundation.org; linux-ker...@vger.kernel.o

RE: [PATCH 5/5, v3] powerpc/fsl: Document rapidio node binding-information

> -Original Message- > From: Liu Gang [mailto:gang@freescale.com] > Sent: Saturday, November 12, 2011 7:03 AM > To: linuxppc-dev@lists.ozlabs.org; Bounine, Alexandre > Cc: a...@linux-foundation.org; linux-ker...@vger.kernel.org; > r58...@freescale.com; b11...@freescale.com; r61...@frees

RE: [PATCH 4/5, v3] powerpc/8xxx: Update device tree bus probe for new RapidIO node binding

> -Original Message- > From: Liu Gang [mailto:gang@freescale.com] > Sent: Saturday, November 12, 2011 7:03 AM > To: linuxppc-dev@lists.ozlabs.org; Bounine, Alexandre > Cc: a...@linux-foundation.org; linux-ker...@vger.kernel.org; > r58...@freescale.com; b11...@freescale.com; r61...@frees

Re: [PATCH] powerpc: Fix atomic_xxx_return barrier semantics

On Wed, Nov 16, 2011 at 02:11:27PM +1100, Benjamin Herrenschmidt wrote: > The Documentation/memory-barriers.txt document requires that atomic > operations that return a value act as a memory barrier both before > and after the actual atomic operation. > > Our current implementation doesn't guarant

RE: [PATCH 3/5,v3] powerpc/85xx: Update SRIO device tree nodes

> -Original Message- > From: Liu Gang [mailto:gang@freescale.com] > Sent: Saturday, November 12, 2011 7:03 AM > To: linuxppc-dev@lists.ozlabs.org; Bounine, Alexandre > Cc: a...@linux-foundation.org; linux-ker...@vger.kernel.org; > r58...@freescale.com; b11...@freescale.com; r61...@frees

RE: [PATCH 2/5, v3] fsl-rio: Add two ports and rapidio message units support

> -Original Message- > From: linuxppc-dev-bounces+alexandre.bounine=idt@lists.ozlabs.org > [mailto:linuxppc-dev- > bounces+alexandre.bounine=idt@lists.ozlabs.org] On Behalf Of Liu > Gang > Sent: Saturday, November 12, 2011 7:02 AM > To: linuxppc-dev@lists.ozlabs.org; Bounine, Alexan

RE: [PATCH 1/5, v3] fsl-rio: Split rio driver into two parts, RapidIO endpoint and message unit

> -Original Message- > From: Liu Gang [mailto:gang@freescale.com] > Sent: Saturday, November 12, 2011 7:02 AM > To: linuxppc-dev@lists.ozlabs.org; Bounine, Alexandre > Cc: a...@linux-foundation.org; linux-ker...@vger.kernel.org; > r58...@freescale.com; b11...@freescale.com; r61...@frees

[PATCH v2 5/7] fsl_pmc: update device bindings

From: Li Yang Signed-off-by: Li Yang --- .../devicetree/bindings/powerpc/fsl/pmc.txt| 63 +++ 1 files changed, 36 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt

[PATCH v2 4/7] powerpc/85xx: add support to JOG feature using cpufreq interface

From: Li Yang Some 85xx silicons like MPC8536 and P1022 has the JOG PM feature. The patch adds the support to change CPU frequency using the standard cpufreq interface. Add the all PLL ratio core support. The ratio CORE to CCB can 1:1(except MPC8536), 3:2, 2:1, 5:2, 3:1, 7:2 and 4:1. Signed-off

[PATCH v2 6/7] fsl_pmc: Add API to enable device as wakeup event source

Add APIs for setting wakeup source and lossless Ethernet in low power modes. These APIs can be used by wake-on-packet feature. Signed-off-by: Dave Liu Signed-off-by: Li Yang Signed-off-by: Jin Qing Signed-off-by: Zhao Chenhui --- Changes for v2: - rename functions - add pmc_flag arch/power

[PATCH v2 3/7] powerpc/85xx: add sleep and deep sleep support

From: Li Yang Some Freescale chips like MPC8536 and P1022 has deep sleep PM mode in addtion to the sleep PM mode. In sleep PM mode, the clocks of e500 core and unused IP blocks is turned off. IP blocks which are allowed to wake up the processor are still running While in deep sleep PM mode, add

[PATCH v2 2/7] powerpc/85xx: add HOTPLUG_CPU support

From: Li Yang Add support to disable and re-enable individual cores at runtime on MPC85xx/QorIQ SMP machines. Currently support e500v2 core. MPC85xx machines use ePAPR spin-table in boot page for CPU kick-off. This patch uses the boot page from bootloader to boot core at runtime. It supports 32-

[PATCH v2 1/7] powerpc/85xx: re-enable timebase sync disabled by KEXEC patch

From: Li Yang The timebase sync is not only necessary when using KEXEC. It should also be used by normal boot up and cpu hotplug. Remove the ifdef added by the KEXEC patch. Signed-off-by: Jin Qing Signed-off-by: Li Yang --- arch/powerpc/platforms/85xx/smp.c |2 -- 1 files changed, 0 inser