Only 32-bit SoCs have a QUICC Engine so limit the config option to PPC32.
Signed-off-by: Kumar Gala
---
arch/powerpc/platforms/Kconfig |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index f970ca2..546ceea
Signed-off-by: Kumar Gala
---
arch/powerpc/platforms/85xx/corenet_ds.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c
b/arch/powerpc/platforms/85xx/corenet_ds.c
index 10af3c7..338e6dc 100644
--- a/arch/powerpc/platforms/85xx/
From: Roy Zang
The P1023 processor is an e500v2 based SoC that utilizes the DPAA
networking architecture. This adds basic board support for non-DPAA
functionality (device tree, board file, etc).
Signed-off-by: Roy Zang
Signed-off-by: Haiying Wang
Signed-off-by: Kumar Gala
---
arch/powerpc/b
We need the FSL specific header fixup code on both 32-bit and 64-bit
platforms so just move the code into pci-common.c.
Signed-off-by: Kumar Gala
---
arch/powerpc/kernel/pci-common.c | 18 ++
arch/powerpc/kernel/pci_32.c | 19 ---
2 files changed, 18 inser
From: Ashish Kalra
We expect this is actually faster, and we end up needing more space than we
can get from the SPRGs in some instances. This is also useful when running
as a guest OS - SPRGs4-7 do not have guest versions.
8 slots are allocated in thread_info for this even though we only actual
From: Scott Wood
In cases like when the platform is used under hypervisor we will NOT
have an MPIC controller but still want doorbells setup.
Signed-off-by: Scott Wood
Signed-off-by: Kumar Gala
---
arch/powerpc/platforms/85xx/smp.c | 21 -
1 files changed, 12 insertions(
Before if we didn't support or enable HW table walk we'd get a messaage
like:
MMU: Book3E Page Tables Disabled
Which is a bit misleading. Now it will say:
MMU: Book3E HW tablewalk not supported
Signed-off-by: Kumar Gala
---
arch/powerpc/mm/tlb_nohash.c |4 ++--
1 files changed, 2 inserti
We fixup every FSL PCIe Root Complex we need to fixup a few things.
Rather than adding every device under the sun we move to just matching
only on the vendor (PCI_VENDOR_ID_FREESCALE) and than check that we are
a PCIe controller in host mode in the fixup.
Signed-off-by: Kumar Gala
---
arch/power
* Added BSD dual-license
* Moved mpic-parent to root so we dont need to duplicate everywhere
* Added next level cache from L2 to CPC
* Moved to 4-cell MPIC interrupt properties
* Added 3 MSI banks
* Added numerous missing nodes: soc-sram-error, guts, pins, clockgen,
rcpm, sfp, serdes, etc.
* Rewo
Several changes on PCIe support on P3041DS/P4080DS/P5020DS boards:
* Add support for "fsl,qoriq-pcie-v2.2" needed by P3041 & P5020
* Removed support for setting primary_phb_addr as we have no ISA need
* Add PCI controller to of_platform_bus_probe (for EDAC)
* Cleanup building w/SWIOTLB off on P4080
Add basic device tree for P3041DS board. This device tree excludes
support for DPAA and RapidIO nodes.
Signed-off-by: Kumar Gala
---
arch/powerpc/boot/dts/p3041ds.dts | 752 +
1 files changed, 752 insertions(+), 0 deletions(-)
create mode 100644 arch/powerp
Add basic device tree for P5020DS board. This device tree excludes
support for DPAA and RapidIO nodes.
Signed-off-by: Kumar Gala
---
arch/powerpc/boot/dts/p5020ds.dts | 745 +
1 files changed, 745 insertions(+), 0 deletions(-)
create mode 100644 arch/powerp
Rather than trying to use the core name we use corenet to distinquish
the platform/core combo. corenet64 will be a 64-bit kernel build and
we'll add a new defconfig for corenet32 for a 32-bit platforms.
Signed-off-by: Kumar Gala
---
arch/powerpc/configs/corenet64_smp_defconfig | 104 ++
The e500mc and e5500 based cores are only available on corenet based
SoCs. We use this name for the P204x, P3040, P4040, P4080, P50x0 SoCs
and any future processors in these families.
Signed-off-by: Kumar Gala
---
arch/powerpc/configs/corenet32_smp_defconfig | 183 ++
1
On Fri, 2011-05-20 at 14:14 +1000, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the tip tree got a conflict in
> arch/powerpc/kernel/smp.c between commit 23d72bfd8f9f ("powerpc:
> Consolidate ipi message mux and demux") from the powerpc tree and commit
> 184748cc50b2 ("sched:
On 05/19/2011 08:54 PM, Benjamin Herrenschmidt wrote:
On Thu, 2011-05-19 at 20:21 -0500, Eric Van Hensbergen wrote:
On Thu, May 19, 2011 at 7:39 PM, Benjamin Herrenschmidt
wrote:
On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
BG/P maps firmware with an early
On 05/19/2011 09:13 PM, Benjamin Herrenschmidt wrote:
On Fri, 2011-05-20 at 12:08 +1000, Benjamin Herrenschmidt wrote:
On Thu, 2011-05-19 at 20:32 -0500, Kazutomo Yoshii wrote:
Actually DMA sends invalidate requests to the snoop unit(L2 level).
BGP SoC is a bit different from other 4x
On May 20, 2011, at 12:01 AM, Kushwaha Prabhakar-B32579 wrote:
>
>
>> -Original Message-
>> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
>> Sent: Friday, May 20, 2011 10:19 AM
>> To: Kushwaha Prabhakar-B32579
>> Cc: linuxppc-dev@lists.ozlabs.org; meet2pra...@gmail.com; Jiang Yuta
Hi all,
After merging the final tree, today's linux-next build (powerpc allnoconfig)
produced these warnings:
kernel/time/clocksource.c: In function '__clocksource_updatefreq_scale':
kernel/time/clocksource.c:655: warning: comparison of distinct pointer types
lacks a cast
kernel/time/clocksource
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Friday, May 20, 2011 10:19 AM
> To: Kushwaha Prabhakar-B32579
> Cc: linuxppc-dev@lists.ozlabs.org; meet2pra...@gmail.com; Jiang Yutang-
> B14898
> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie AT
On May 19, 2011, at 5:48 AM, Shengzhou Liu wrote:
> Simultaneous FCM and GPCM or UPM operation may erroneously trigger
> bus monitor timeout.
>
> Set the local bus monitor timeout value to the maximum by setting
> LBCR[BMT] = 0 and LBCR[BMTPS] = 0xF.
>
> Signed-off-by: Shengzhou Liu
> Signed-o
On May 19, 2011, at 11:41 PM, Kushwaha Prabhakar-B32579 wrote:
>
>
>> -Original Message-
>> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
>> Sent: Thursday, May 19, 2011 6:53 PM
>> To: Kushwaha Prabhakar-B32579
>> Cc: linuxppc-dev@lists.ozlabs.org; meet2pra...@gmail.com; Jiang Yut
On May 19, 2011, at 11:41 PM, Kushwaha Prabhakar-B32579 wrote:
>
>
>> -Original Message-
>> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
>> Sent: Thursday, May 19, 2011 6:53 PM
>> To: Kushwaha Prabhakar-B32579
>> Cc: linuxppc-dev@lists.ozlabs.org; meet2pra...@gmail.com; Jiang Yut
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Thursday, May 19, 2011 6:53 PM
> To: Kushwaha Prabhakar-B32579
> Cc: linuxppc-dev@lists.ozlabs.org; meet2pra...@gmail.com; Jiang Yutang-
> B14898
> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie A
On May 19, 2011, at 10:31 PM, Kumar Gala wrote:
> The following changes since commit f38aa708776aefd9e3ba7ec1211c07efe9fa3227:
>
> powerpc: Remove last piece of GEMINI (2011-05-19 17:32:29 +1000)
>
> are available in the git repository at:
> git://git.kernel.org/pub/scm/linux/kernel/git/galak
Alex,
What are we doing with this patch?
- k
On Dec 3, 2010, at 12:04 PM, Bounine, Alexandre wrote:
> I think they should follow the previous two that are in Kumar’s tree.
> Probably Kumar may give you a better timeline estimate for this.
>
> Alex.
>
> From: linuxppc-dev-bounces+alexandre.
Hi all,
Today's linux-next merge of the tip tree got a conflict in
arch/powerpc/kernel/smp.c between commit 23d72bfd8f9f ("powerpc:
Consolidate ipi message mux and demux") from the powerpc tree and commit
184748cc50b2 ("sched: Provide scheduler_ipi() callback in response to
smp_send_reschedule()")
> Unfortunately, the firmware is also required:
> - to configure Blue Gene Interrupt Controller(BIC)
Can't we just write bare metal code for that ?
> - to configure Torus DMA unit. e.g. fifo
Same
> - to configure global interrupt (even we don't use, we need to disable
> some channel correctly)
The following changes since commit f38aa708776aefd9e3ba7ec1211c07efe9fa3227:
powerpc: Remove last piece of GEMINI (2011-05-19 17:32:29 +1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
Bhaskar Upadhaya (1):
powerpc: Addi
On Thu, 2011-05-19 at 22:02 -0500, Kazutomo Yoshii wrote:
> On 05/19/2011 09:13 PM, Benjamin Herrenschmidt wrote:
> > On Fri, 2011-05-20 at 12:08 +1000, Benjamin Herrenschmidt wrote:
> >
> >> On Thu, 2011-05-19 at 20:32 -0500, Kazutomo Yoshii wrote:
> >>
> >>> Actually DMA sends invalidat
On Fri, 2011-05-20 at 12:08 +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2011-05-19 at 20:32 -0500, Kazutomo Yoshii wrote:
> >
> > Actually DMA sends invalidate requests to the snoop unit(L2 level).
> > BGP SoC is a bit different from other 4xx base.
>
> Well, some other 44x also have a snoopi
On Thu, 2011-05-19 at 20:32 -0500, Kazutomo Yoshii wrote:
>
> Actually DMA sends invalidate requests to the snoop unit(L2 level).
> BGP SoC is a bit different from other 4xx base.
Well, some other 44x also have a snooping L2 (more or less), but L1 is
usually the problem.
Cheers,
Ben.
On 05/19/2011 07:36 PM, Benjamin Herrenschmidt wrote:
On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
For BGP, it is convenient for 'kmalloc' to come back with 32-byte
aligned units for torus DMA
Signed-off-by: Eric Van Hensbergen
---
arch/powerpc/include/asm/page_32.h |
On Thu, 2011-05-19 at 20:21 -0500, Eric Van Hensbergen wrote:
> On Thu, May 19, 2011 at 7:39 PM, Benjamin Herrenschmidt
> wrote:
> > On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
> >> BG/P maps firmware with an early TLB
> >
> > That's a bit gross. How often do you call that firmwa
On Thu, 2011-05-19 at 20:08 -0500, Eric Van Hensbergen wrote:
> On Thu, May 19, 2011 at 7:35 PM, Benjamin Herrenschmidt
> wrote:
> > On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
> >> + .dcache_bsize = 32,
> >> + .cpu_setup = __setup_c
On Thu, 2011-05-19 at 19:47 -0500, Eric Van Hensbergen wrote:
> On Thu, May 19, 2011 at 7:36 PM, Benjamin Herrenschmidt
> wrote:
> > On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
> >>
> >> -#ifdef CONFIG_NOT_COHERENT_CACHE
> >> +#if defined(CONFIG_NOT_COHERENT_CACHE) || defined(CON
On Thu, May 19, 2011 at 7:39 PM, Benjamin Herrenschmidt
wrote:
> On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
>> BG/P maps firmware with an early TLB
>
> That's a bit gross. How often do you call that firmware in practice ?
> Aren't you better off instead inserting a TLB entry for
On Thu, 2011-05-19 at 16:08 +0200, Michel Dänzer wrote:
> From: Michel Dänzer
>
> This was based on a description by Ben Herrenschmidt:
>
> > I've removed that SBA reset from the normal TLB invalidation path and
> > left it only once after turning AGP on.
>
> About six months ago, he said:
>
>
On Thu, May 19, 2011 at 7:35 PM, Benjamin Herrenschmidt
wrote:
> On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
>> + .dcache_bsize = 32,
>> + .cpu_setup = __setup_cpu_460gt,
> ^
On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
> +#ifdef CONFIG_BGP
> +/*
> + * The icbi instruction does not broadcast to all cpus in the ppc450
> + * processor used by Blue Gene/P. It is unlikely this problem will
> + * be exhibited in other processors so this remains ifdef'ed fo
On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
> BG/P nodes need to be configured for writethrough to work in SMP
> configurations. This patch adds the right hooks in the MMU code
> to make sure L1_WRITETHROUGH configurations are setup for BG/P.
> /* Storage attribute and access c
On Thu, 2011-05-19 at 08:53 -0500, Eric Van Hensbergen wrote:
> On Thu, May 19, 2011 at 12:58 AM, Michael Neuling wrote:
> > Eric,
> >
> >> This patch adds save/restore register support for the BlueGene/P
> >> double hummer FPU.
> >
> > What does this mean? Needs more details here.
> >
>
> Hi Mi
On Thu, 2011-05-19 at 15:58 +1000, Michael Neuling wrote:
> > +
> > #define SAVE_2GPRS(n, base)SAVE_GPR(n, base); SAVE_GPR(n+1, base)
> > #define SAVE_4GPRS(n, base)SAVE_2GPRS(n, base); SAVE_2GPRS(n+2,
> > base)
> > #define SAVE_8GPRS(n, base)SAVE_4GPRS(n, base); SAVE_4
On Thu, May 19, 2011 at 7:36 PM, Benjamin Herrenschmidt
wrote:
> On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
>>
>> -#ifdef CONFIG_NOT_COHERENT_CACHE
>> +#if defined(CONFIG_NOT_COHERENT_CACHE) || defined(CONFIG_BGP)
>> #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
>> #endif
>
> Is
> >> >> > Eric,
> >> >> >
> >> >> >> This patch adds save/restore register support for the BlueGene/P
> >> >> >> double hummer FPU.
> >> >> >
> >> >> > What does this mean? =3DA0Needs more details here.
> >> >> >
> >>
> >> okay, I've changed it a bit in [V2], if you want more I can do my best.
> >
On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
> BG/P maps firmware with an early TLB
That's a bit gross. How often do you call that firmware in practice ?
Aren't you better off instead inserting a TLB entry for it when you call
it instead ? A simple tlbsx. + tlbwe sequence would do
On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
> For BGP, it is convenient for 'kmalloc' to come back with 32-byte
> aligned units for torus DMA
>
> Signed-off-by: Eric Van Hensbergen
> ---
> arch/powerpc/include/asm/page_32.h |2 +-
> 1 files changed, 1 insertions(+), 1 delet
On Wed, 2011-05-18 at 16:24 -0500, Eric Van Hensbergen wrote:
> Signed-off-by: Eric Van Hensbergen
> ---
> arch/powerpc/kernel/cputable.c | 14 ++
> 1 files changed, 14 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
>
On Thu, May 19, 2011 at 6:16 PM, Michael Neuling wrote:
> In message you wrote:
>> On Thu, May 19, 2011 at 4:36 PM, Michael Neuling wrote:
>> > In message you wrote=
>> :
>> >> On Thu, May 19, 2011 at 12:58 AM, Michael Neuling wr=
>> ote=3D
>> >> :
>> >> > Eric,
>> >> >
>> >> >> This patch add
On Thu, May 19, 2011 at 5:12 PM, Benjamin Herrenschmidt
wrote:
> On Thu, 2011-05-19 at 11:58 -0600, Bjorn Helgaas wrote:
>> The scan below PCIX0 (bus 0001:00) doesn't find anything. You really
>> need a powerpc expert to help here, but in their absence, my guess
>> would be something's wrong with
In message you wrote:
> Damnit Mikey, just after I hit send on [V2].
>
> On Thu, May 19, 2011 at 4:36 PM, Michael Neuling wrote:
> > In message you wrote=
> :
> >> On Thu, May 19, 2011 at 12:58 AM, Michael Neuling wr=
> ote=3D
> >> :
> >> > Eric,
> >> >
> >> >> This patch adds save/restore
On Thu, 2011-05-19 at 11:58 -0600, Bjorn Helgaas wrote:
> The scan below PCIX0 (bus 0001:00) doesn't find anything. You really
> need a powerpc expert to help here, but in their absence, my guess
> would be something's wrong with config space access, so I would start
> by just adding some printks
Damnit Mikey, just after I hit send on [V2].
On Thu, May 19, 2011 at 4:36 PM, Michael Neuling wrote:
> In message you wrote:
>> On Thu, May 19, 2011 at 12:58 AM, Michael Neuling wrote=
>> :
>> > Eric,
>> >
>> >> This patch adds save/restore register support for the BlueGene/P
>> >> double h
BG/P nodes need to be configured for writethrough to work in SMP
configurations. This patch adds the right hooks in the MMU code
to make sure BGP_L1_WRITETHROUGH configurations are setup for BG/P.
Signed-off-by: Eric Van Hensbergen
---
arch/powerpc/include/asm/mmu-44x.h |2 ++
arch/powe
This patch adds save/restore register support for the BlueGene/P
double FPU. Since there are two FPUs, we need to save and restore
twice the registers. Fortunately BG/P gives us some opcodes to
assist with that task.
Signed-off-by: Eric Van Hensbergen
---
arch/powerpc/include/asm/ppc-opcode.h
Hello,
I'm trying to get 2.6.38.6 up and running on my ppc880 board and I've
run into a problem when the kernel is attempting to perform it's first
exec (/sbin/init). I've tried to debug it as much as I can so I thought
I would post this to see if anybody has any ideas or suggestions about
wha
In message you wrote:
> On Thu, May 19, 2011 at 12:58 AM, Michael Neuling wrote=
> :
> > Eric,
> >
> >> This patch adds save/restore register support for the BlueGene/P
> >> double hummer FPU.
> >
> > What does this mean? =A0Needs more details here.
> >
>
> Hi Mikey,
>
> any specific details yo
On Thu, May 19, 2011 at 7:22 AM, Steven Rostedt wrote:
> On Wed, 2011-05-18 at 21:07 -0700, Will Drewry wrote:
>
>> Do event_* that return non-void exist in the tree at all now? I've
>> looked at the various tracepoint macros as well as some of the other
>> handlers (trace_function, perf_tp_event
The ePAPR embedded hypervisor specification provides an API for "byte
channels", which are serial-like virtual devices for sending and receiving
streams of bytes. This driver provides Linux kernel support for byte
channels via three distinct interfaces:
1) An early-console (udbg) driver. This pr
* Benjamin Herrenschmidt wrote:
> On Wed, 2011-05-18 at 21:16 -0700, Roland Dreier wrote:
> > On Wed, May 18, 2011 at 11:31 AM, Milton Miller wrote:
> > > So the real question should be why is x86-32 supplying a broken writeq
> > > instead of letting drivers work out what to do it when needed?
2.6.38-stable review patch. If anyone has any objections, please let us know.
--
From: Frederic Weisbecker
commit 925f83c085e1bb08435556c5b4844a60de002e31 upstream.
We make use of ptrace_get_breakpoints() / ptrace_put_breakpoints() to
protect ptrace_set_debugreg() even if CONF
On Thu, May 19, 2011 at 6:41 AM, Prashant Bhole
wrote:
> On Wed, May 18, 2011 at 7:44 PM, Bjorn Helgaas wrote:
>> On Wed, May 18, 2011 at 4:02 AM, Prashant Bhole
>> wrote:
>>> On Mon, May 2, 2011 at 10:21 AM, Prashant Bhole
>>> wrote:
I have a custom made powerpc 460EX board. On that
On 19.05.2011 [17:43:56 +1000], Benjamin Herrenschmidt wrote:
> On Wed, 2011-05-11 at 15:25 -0700, Nishanth Aravamudan wrote:
> > From: Milton Miller
> >
> > The hook dma_get_required_mask is supposed to return the mask required
> > by the platform to operate efficently. The generic version of
>
On Thu, 19 May 2011 11:31:32 -0500
Timur Tabi wrote:
> Alan Cox wrote:
> > You really also need a hangup method so vhangup() does the right thing
> > and you can securely do logins etc and sessions on your console. As
> > you've got no hardware entangled in this and you already use tty_port
> > h
Hi Shawn,
> Should I go for v3 right now to address the patch applying problems
> and that ESDHC_IMX build issue, or hold for a while to see if you
> have more comments on v2?
Please wait a little bit more.
> And what is your position on patch #5 which merges esdhc imx and mpc
> support into one
Currently Maple setup code creates cpc925_edac device only on
Motorola ATCA-6101 blade. Make setup code check bridge revision
and enable EDAC on all U3 bridges.
Verified on Momentum MapleD (ppc970fx kit) board.
Signed-off-by: Dmitry Eremin-Solenikov
---
arch/powerpc/platforms/maple/setup.c |
Alan Cox wrote:
> You really also need a hangup method so vhangup() does the right thing
> and you can securely do logins etc and sessions on your console. As
> you've got no hardware entangled in this and you already use tty_port
> helpers the hangup helper will do the work for you.
So all I need
Greg KH wrote:
> It's too late, it needed to be in linux-next _before_ the window opened.
>
> sorry,
Curses! Foiled again!
Well, then I'd like to get this patchset fixed up and approved soon after the
window closes, so that there's no excuse for missing 2.6.41.
--
Timur Tabi
Linux kernel deve
On Thu, May 19, 2011 at 02:13:41PM +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2011-02-11 at 15:34 -0800, Ira W. Snyder wrote:
> > Hello everyone,
> >
> > This is the seventh posting of these drivers, taking into account comments
> > from earlier postings. I've made sure that the drivers both p
Alan Cox wrote:
>> > + /* Pass the received data to the tty layer. Note that this
>> > + * function calls tty_buffer_request_room(), so I'm not sure if
>> > + * we should have also called tty_buffer_request_room().
>> > + */
>> > + ret = tty_insert_f
Hi Wolfram,
On Thu, May 19, 2011 at 11:40:46AM +0200, Wolfram Sang wrote:
> Hi Shawn,
>
> > Changes since v1:
> > * Rebase on cjb's mmc-next tree
>
> Is it maybe possible that you get access to
> http://opensource.freescale.com/git or another machine? A branch to pull
> from would be more conve
On Thu, May 19, 2011 at 10:54:03AM -0500, Timur Tabi wrote:
> > Depends if the functionality is useful in your environment or not
>
> It is, but I'd like to add it later so that I can make the 2.6.40 window (if
> it
> isn't already too late).
It's too late, it needed to be in linux-next _before_
On Thu, 19 May 2011 00:41:29 -0500
Kumar Gala wrote:
>
> On May 9, 2011, at 4:26 PM, Scott Wood wrote:
>
> > Without this, we attempt to use doorbells for IPIs, and end up
> > branching to some bad address. Plus, even for the exceptions
> > we don't implement, it's good to handle it and get a
> Ok, I can do that.
>
> > Depends if the functionality is useful in your environment or not
>
> It is, but I'd like to add it later so that I can make the 2.6.40 window (if
> it
> isn't already too late).
Seems sensible.
Alan
___
Linuxppc-dev mailin
Alan Cox wrote:
>>> > > The kfifo API is probably faster and cleaner. Much of tty still uses
>>> > > CIRC_* because they predate the new APIs.
>> >
>> > Ok, I'll change it.
> I flag that one up as a general comment - don't feel you need to change
> it if CIRC_* works in your case.
CIRC_* does wor
> Under what circumstances can ttys be NULL? I currently only use this code in
> the RX and TX interrupt handlers, which are both enabled in the
> tty_port_operations.activate() function.
When you add hangup support.
>
> Is this right for the TX handler:
>
> static irqreturn_t ehv_bc_tty_tx_is
On 05/19/2011 08:53 AM, Eric Van Hensbergen wrote:
>> +#ifdef CONFIG_BGP
>> +#define SAVE_FPR(n, b, base) li b, THREAD_FPR0+(16*(n)); STFPDX(n, base, b)
>> +#define REST_FPR(n, b, base) li b, THREAD_FPR0+(16*(n)); LFPDX(n, base, b)
>
> 16*? Are these FP regs 64 or 128 bits wide? If
Alan Cox wrote:
> ttys = tty_port_tty_get(&bc->port);
> stuff
> if (ttys != NULL)
> tty stuff
> tty_kref_put(ttys);
Under what circumstances can ttys be NULL? I currently only use this code in
the RX and TX interrupt handlers, which are both enabled in the
tty_port_operations.activate
Arnd Bergmann wrote:
> Why is this using a full tty driver instead of the hvc framework that most
> other hypervisor consoles use?
Because HVC uses the same interface for consoles and tty, and that resulted in
dropped characters if the client driver returns EAGAIN because it's output
buffer is ful
> + struct tty_struct *ttys;
ttys are refcounted and you have a refcounted pointer for free in your
tty_port that is maintained by the tty_port logic, as well as it
providing ref counted, properly locked handling for the reference.
> +/ TTY DRIVER
> ***
On Thu, 19 May 2011 07:22:25 -0700
Greg KH wrote:
> On Thu, May 19, 2011 at 08:54:31AM -0500, Timur Tabi wrote:
> > +/*
> > + * The udbg subsystem calls this function to display a single character.
> > + * We convert CR to a CR/LF.
> > + */
> > +static void ehv_bc_udbg_putc(char c)
> > +{
> > +
On Thursday 19 May 2011, Timur Tabi wrote:
>
> The ePAPR embedded hypervisor specification provides an API for "byte
> channels", which are serial-like virtual devices for sending and receiving
> streams of bytes.
Why is this using a full tty driver instead of the hvc framework that most
other hy
On Thu, May 19, 2011 at 08:54:31AM -0500, Timur Tabi wrote:
> +/*
> + * The udbg subsystem calls this function to display a single character.
> + * We convert CR to a CR/LF.
> + */
> +static void ehv_bc_udbg_putc(char c)
> +{
> + if (c == '\n')
> + byte_channel_spin_send('\r');
> +
Greg KH wrote:
> Why do this conversion in the driver? Shouldn't that be something that
> userspace worries about?
The udbg interface is a very early kernel printk interface. I don't know what
the "u" stands for, but "dbg" is for "debug". The udbg interface is removed
once a normal console driv
Timur Tabi wrote:
> have hypervisor extensions (e.g. the P4080 which has an e500mc core).
Oops, this email got munged. The first paragraph should say:
This patchset adds support for running Linux under the Freescale hypervisor,
which is an ePAPR-compliant hypervisor that runs on our PowerPC SOCs
From: Michel Dänzer
This was based on a description by Ben Herrenschmidt:
> I've removed that SBA reset from the normal TLB invalidation path and
> left it only once after turning AGP on.
About six months ago, he said:
> I did it a bit differently, but yeah, you get the idea. I'm doing a
> pat
From: Ashish Kalra
The Freescale ePAPR reference hypervisor provides interrupt controller services
via a hypercall interface, instead of emulating the MPIC controller. This is
called the VMPIC.
The ePAPR "virtual interrupt controller" provides interrupt controller services
for external interrup
The Freescale hypervisor management driver provides several services to
drivers and applications related to the Freescale hypervisor:
1. An ioctl interface for querying and managing partitions
2. A file interface to reading incoming doorbells
3. An interrupt handler for shutting down the partiti
ePAPR hypervisors provide operating system services via a "hypercall"
interface. The following steps need to be performed to make an hcall:
1. Load r11 with the hcall number
2. Load specific other registers with parameters
3. Issue instrucion "sc 1"
4. The return code is in r3
5. Other returned p
Add functions to restart and halt the current partition when running under
the Freescale hypervisor. These functions should be assigned to various
function pointers of the ppc_md structure during the .probe() function for
the board:
ppc_md.restart = fsl_hv_restart;
ppc_md.power_of
From: Stuart Yoder
Move irq_choose_cpu() into arch/powerpc/kernel/irq.c so that it can be used
by other PIC drivers. The function is not MPIC-specific.
Signed-off-by: Stuart Yoder
Signed-off-by: Timur Tabi
---
arch/powerpc/include/asm/irq.h |2 ++
arch/powerpc/kernel/irq.c | 35 ++
Add support for the ePAPR-compliant Freescale hypervisor (aka "Topaz") on the
Freescale P3041DS, P4080DS, and P5020DS reference boards.
Signed-off-by: Timur Tabi
---
arch/powerpc/platforms/85xx/Kconfig |3 +++
arch/powerpc/platforms/85xx/corenet_ds.c |7 +++
arch/powerpc/platfor
The ePAPR embedded hypervisor specification provides an API for "byte
channels", which are serial-like virtual devices for sending and receiving
streams of bytes. This driver provides Linux kernel support for byte
channels via three distinct interfaces:
1) An early-console (udbg) driver. This pr
have hypervisor extensions (e.g. the P4080 which has an e500mc core).
I think it makes sense for this patchset to go through Kumar Gala's -next
branch, but I still need ACKs from various people on the parts that are
not e500-specific.
1. powerpc: make irq_choose_cpu() available to all PIC driver
On Thu, May 19, 2011 at 12:58 AM, Michael Neuling wrote:
> Eric,
>
>> This patch adds save/restore register support for the BlueGene/P
>> double hummer FPU.
>
> What does this mean? Needs more details here.
>
Hi Mikey,
any specific details you are looking for here? AFAIK these patches
are requ
On May 19, 2011, at 6:22 AM, Kushwaha Prabhakar-B32579 wrote:
> Hi Kumar,
> Please find my answer in-lined
>
>> -Original Message-
>> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
>> Sent: Thursday, May 19, 2011 12:00 PM
>> To: Kushwaha Prabhakar-B32579
>> Cc: linuxppc-dev@lists.o
On May 19, 2011, at 6:25 AM, Kushwaha Prabhakar-B32579 wrote:
> Hello Kumar,
> Please find my answer in-lined
>
>> -Original Message-
>> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
>> Sent: Thursday, May 19, 2011 11:55 AM
>> To: Kushwaha Prabhakar-B32579
>> Cc: linuxppc-dev@list
On Thu, May 19, 2011 at 5:43 AM, Josh Boyer wrote:
> On Wed, May 18, 2011 at 04:24:52PM -0500, Eric Van Hensbergen wrote:
>>
>>+config L1_WRITETHROUGH
>>+ bool "Blue Gene/P enabled writethrough mode"
>>+ depends on BGP
>>+ default y
>
> You add this config option here, named generic
On Wed, Mar 30, 2011 at 02:40:24PM +0530, Rupjyoti Sarmah wrote:
>This patch adds MSI support for 440SPe, 460Ex, 460Sx and 405Ex.
>
>Signed-off-by: Rupjyoti Sarmah
>Signed-off-by: Tirumala R Marri
Acked-by: Josh Boyer
>---
>v4:
> * Updated the coding style as per recommendation by Philipp
> *
Hi,
On Wed, May 18, 2011 at 7:44 PM, Bjorn Helgaas wrote:
> On Wed, May 18, 2011 at 4:02 AM, Prashant Bhole
> wrote:
>> On Mon, May 2, 2011 at 10:21 AM, Prashant Bhole
>> wrote:
>>>
>>> Hi,
>>> I have a custom made powerpc 460EX board. On that board u-boot
>>> can see a PCI device but Linux ker
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