On Oct 20, 2010, at 12:12 AM, Zang Roy-R61911 wrote:
>
>
>> -Original Message-
>> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
>> Sent: Tuesday, October 19, 2010 21:19 PM
>> To: Zang Roy-R61911
>> Cc: linux-...@lists.infradead.org; Wood Scott-B07421;
> dedeki...@gmail.com; Lan
>>
Nishanth Aravamudan wrote:
> Use set_dma_ops and remove now used-once oddly named temp pointer sd.
>
> Signed-off-by: Milton Miller
> Signed-off-by: Nishanth Aravamudan
> Cc: b...@kernel.crashing.org
> Cc: linuxppc-dev@lists.ozlabs.org
> ---
Maybe I forget to write you that this patch is alread
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Tuesday, October 19, 2010 21:19 PM
> To: Zang Roy-R61911
> Cc: linux-...@lists.infradead.org; Wood Scott-B07421;
dedeki...@gmail.com; Lan
> Chunhe-B25806; linuxppc-...@ozlabs.org; a...@linux-foundation.org;
icswx is a PowerPC co-processor instruction to send data to a
co-processor. On Book-S processors the LPAR_ID and process ID (PID) of
the owning process are registered in the window context of the
co-processor at initial time. When the icswx instruction is executed,
the L2 generates a cop-reg transa
Benjamin Herrenschmidt writes:
>
> On Tue, 2010-10-19 at 22:47 +0200, Segher Boessenkool wrote:
> >
> > It looks like it is the frame counter in an USB OHCI HCCA.
> > 16-bit, 1kHz update, offset x'80 in a page.
> >
> > So either the kernel forgot to call quiesce on it, or the firmware
> > doesn'
On Tue, 2010-10-19 at 22:47 +0200, Segher Boessenkool wrote:
>
> It looks like it is the frame counter in an USB OHCI HCCA.
> 16-bit, 1kHz update, offset x'80 in a page.
>
> So either the kernel forgot to call quiesce on it, or the firmware
> doesn't implement that, or the firmware messed up some
On Tue, 2010-10-19 at 13:10 -0500, pac...@kosh.dhis.org wrote:
>
> So what type of driver, firmware, or hardware bug puts a 16-bit 1000Hz
> timer
> in memory, and does it in little-endian instead of the CPU's native
> byte
> order? And why does it stop doing it some time during the early init
> sc
> I made a new discovery.
And this nails it :-)
> So then I ran
> dd if=/dev/mem bs=4 count=1 skip=$((0xfc5c080/4)) | od -t x4
> a few times very fast, plucking the first affected word directly out of
> memory by its physical address. The result:
>
> The low 16 bits are always zero as before. T
Benjamin Herrenschmidt writes:
> >
> > I thought of that, but as far as I can tell, this CPU doesn't have DABR.
>
> AFAIK, the 7447 is just a derivative of the 7450 design which -does-
> have a DABR ... Unless it's broken :-)
Hmm. gdb resorts to single-stepping when I set a watchpoint while debu
On Mon, Oct 18, 2010 at 11:55:44PM +0200, Thomas Gleixner wrote:
> I might be completely one off as usual, but this thing reminds me of a
> bug I stared at yesterday night:
This problem is completely unrelated. My problem was caused by using
binutils-gold.
Helmut
_
Eran Liberty wrote:
Eran Liberty wrote:
This should probably go to the Freescale support, as it feels like a
hardware issue yet the end result is a very frozen Linux kernel so I
post here first...
I have a programmable FPGA PCIe device connected to a Freescale's
P2020 PCIe port. As part of t
On Tue, 19 Oct 2010, Helmut Grohne wrote:
> On Mon, Oct 18, 2010 at 11:55:44PM +0200, Thomas Gleixner wrote:
> > I might be completely one off as usual, but this thing reminds me of a
> > bug I stared at yesterday night:
>
> This problem is completely unrelated. My problem was caused by using
> b
On Fri, Oct 15, 2010 at 09:24:38PM +0200, Eric Bénard wrote:
> Hi Greg,
>
> Le 15/10/2010 21:10, Greg KH a écrit :
> >On Fri, Oct 15, 2010 at 02:30:58PM +0200, Eric Bénard wrote:
> >>this patch gives the possibility to workaround bug ENGcm09152
> >>on i.MX35 when the hardware workaround is also im
On Oct 18, 2010, at 2:22 AM, Roy Zang wrote:
> Move Freescale elbc interrupt from nand dirver to elbc driver.
> Then all elbc devices can use the interrupt instead of ONLY nand.
>
> For former nand driver, it had the two functions:
>
> 1. detecting nand flash partitions;
> 2. registering elbc i
> > >From there, you might be able to close onto the culprit a bit more, for
> > example, try using the DABR register to set data access breakpoints
> > shortly before the corruption spot. AFAIK, On those old 32-bit CPUs, you
> > can set whether you want it to break on a real or a virtual address.
On Tue, Oct 19, 2010 at 6:32 AM, Scott Wood wrote:
> If mem= is used on the kernel command line to create reserved regions
> for userspace to map using /dev/mem, let it be mapped cacheable as long
> as it is within the memory region described in the device tree.
>
> Signed-off-by: Scott Wood
> --
--
Roberto Mantovani
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>-Original Message-
>From: Tonyliu [mailto:bo@windriver.com]
>
>> Thanks, the missing clock-frequency was part of my problem. The rest was
>> solved by adding some more quirks to the esdhc-driver
>> (SDHCI_QUIRK_FORCE_1_BIT_DATA and >SDHCI_QUIRK_RESET_AFTER_REQUEST). Why it
>> is ne
hi!
i assume the mpc8343 dma controllers ability to do internally controlled
operations (csb/csb)
is _not_ affected by deactivating externally controlled operations via
pinmultiplexing in sicrl.
am I correct?
thanks
horst kronstorfer
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> -Original Message-
> From: linuxppc-dev-bounces+tie-fei.zang=freescale@lists.ozlabs.org
>
[mailto:linuxppc-dev-bounces+tie-fei.zang=freescale@lists.ozlabs.org
] On
> Behalf Of Tonyliu
> Sent: Tuesday, October 19, 2010 15:56 PM
> To: Maria Johansen
> Cc: linuxppc-dev@lists.ozlabs
Maria Johansen wrote:
-Original Message-
From: Tonyliu [mailto:bo@windriver.com]
Could this be a problem related the eSDHC controller (or the driver),
or is it the memory card? (a 4GB SanDisk Extreme SDHC card, which unfortunately is the only card I have available at the mo
>-Original Message-
>From: Tonyliu [mailto:bo@windriver.com]
>
>> Could this be a problem related the eSDHC controller (or the driver),
>> or is it the memory card? (a 4GB SanDisk Extreme SDHC card, which
>> unfortunately is the only card I have available at the moment.) I will kee
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