On Wed, Feb 10, 2010 at 10:10:25PM +1100, Anton Blanchard wrote:
>
> Nick Piggin discovered that lwsync barriers around locks were faster than
> isync
> on 970. That was a long time ago and I completely dropped the ball in testing
> his patches across other ppc64 processors.
>
> Turns out the id
On Wed, Feb 10, 2010 at 09:57:28PM +1100, Anton Blanchard wrote:
>
> Recent versions of the PowerPC architecture added a hint bit to the larx
> instructions to differentiate between an atomic operation and a lock
> operation:
>
> > 0 Other programs might attempt to modify the word in storage add
Hi Anton,
On Thursday 11 February 2010 15:07:54 Anton Blanchard wrote:
>
> A number of our chips like loads and stores to be paired. A small kernel
> module testcase shows the improvement of pairing loads and stores in
> copy_4k_page:
>
> POWER6: +9%
> POWER7: +1.5%
I just tried this on one of
On Tue, 2010-02-09 at 16:24 +0100, Pavel Machek wrote:
> ...according to gcc docs, sp should be global, or placement in
> register is not guaranteed (except at asm boundaries, but there are
> none).
Sorry I'm not sure I grok what you mean.
Cheers,
Ben.
__
A number of our chips like loads and stores to be paired. A small kernel
module testcase shows the improvement of pairing loads and stores in
copy_4k_page:
POWER6: +9%
POWER7: +1.5%
#include
#include
#define ITERATIONS 1000
static int __init copypage_init(void)
{
struct timespe
On Mon, Feb 08, 2010 at 02:50:57PM -0700, Dave Kleikamp wrote:
> powerpc/booke: Introduce new CONFIG options for advanced debug registers
>
> From: Dave Kleikamp
>
> Introduce new config options to simplify the ifdefs pertaining to the
> advanced debug registers for booke and 40x processors:
>
On Wed, Feb 10, 2010 at 06:06:10PM -0600, Scott Wood wrote:
> Paul Mackerras wrote:
> >>Some limitations:
> >>- No threshold support -- need to figure out how to represent it in
> >> the event struct from userspace.
> >
> >What does "threshold support" mean in this context? Does it mean
> >somet
On Wed, 2010-02-10 at 14:54 +0100, Stefan Roese wrote:
> This patch adds support for boards with more that 512MByte RAM. Currently
> only 512MB of memory are enabled in the DCCR/ICCR real-mode cache
> control registers. This patch now enables caching in real-mode for
> 2GByte.
Should we make that
Here is a patch from Paul Mackerras that improves the ppc64 copy_tofrom_user.
The loop now does 32 bytes at a time and as well as pairing loads and stores.
A quick test case that reads 8kB over and over shows the improvement:
POWER6: 53% faster
POWER7: 51% faster
#define _XOPEN_SOURCE 500
#inc
Paul Mackerras wrote:
Some limitations:
- No threshold support -- need to figure out how to represent it in
the event struct from userspace.
What does "threshold support" mean in this context? Does it mean
something different from getting an interrupt after N events have been
counted? Or do
On Fri, Jan 15, 2010 at 03:43:51PM -0600, Scott Wood wrote:
> This implements perf_event support for the Freescale embedded performance
> monitor, based on the existing perf_event.c that supports server/classic
> chips. Eventually we may want to factor out some of the common bits.
Cool! I agree
On Wed, Feb 10, 2010 at 09:40:34AM -0600, Kumar Gala wrote:
>> In the off chance that someone actually does an SMP 44x, I think the hint bit
>> here would just be ignored (I could test possibly if we want to verify).
>> However, I thought the FSL parts didn't like toggling the reserved bits and
>>
On Tue, 9 Feb 2010 19:39:35 -0700
Grant Likely wrote:
> Acked-by: Grant Likely
>
> Alessandro, do you want me to carry this one in my powerpc tree along
> with the rest of the 5121 patches, or do you want to carry it? There
> aren't any commit ordering issues on this one.
Yes please. thanks.
On Feb 9, 2010, at 9:19 PM, Josh Boyer wrote:
> On Wed, Feb 10, 2010 at 01:50:11PM +1100, Anton Blanchard wrote:
>>
>> Recent versions of the PowerPC architecture added a hint bit to the larx
>> instructions to differentiate between an atomic operation and a lock
>> operation:
>>
>>> 0 Other p
From: Wolfgang Grandegger
This patch adds the MPC5121 to the list of supported devices,
enhances the doc of the "clock-frequency" property and removes
the obsolete "cell-index", "device_type" and "fsl-i2c" property.
Furthermore an example for the MPC5121 has been added.
Signed-off-by: Wolfgang G
From: Wolfgang Grandegger
"__devinit[data]" has not yet been used for all initialization functions
and data. To avoid truncating lines, the struct "mpc_i2c_match_data" has
been renamed to "mpc_i2c_data", which is even the better name.
Signed-off-by: Wolfgang Grandegger
Tested-by: Wolfram Sang
From: Wolfgang Grandegger
As I2C interrupts must be enabled for the MPC512x by the setup function
as well, "fsl,preserve-clocking" is handled in a slighly different way.
Also, the old settings are now reported calling dev_dbg(). For the
MPC512x the clock setup function of the MPC52xx can be re-u
From: Wolfgang Grandegger
This patch series adds support for the MPC512x from Freescale to the
i2c-mpc driver. At that occasion, issues with __devinit[data] have
been fixed and the doc of the FSL I2C dts bindings updated. It has
been tested on a MPC5121ADS, TQM5200 and TQM8560 board
Changes sin
From: Wolfgang Grandegger
To prepare support for the MPC512x processors from Freescale the
"setclock" initialization functions have been renamed to "setup"
because I2C interrupts must be enabled for the MPC512x by this
function as well.
Signed-off-by: Wolfgang Grandegger
---
drivers/i2c/busse
Grant Likely wrote:
> On Wed, Feb 10, 2010 at 3:53 AM, Wolfgang Grandegger
> wrote:
>> Stephen Rothwell wrote:
>>> Hi Wolfgang,
>>>
>>> On Wed, 10 Feb 2010 11:09:25 +0100 Wolfgang Grandegger
>>> wrote:
> __devinitdata goes at the end, immediately before the '='. Ditto
> throughout the
On Wed, Feb 10, 2010 at 3:20 AM, Wolfgang Grandegger
wrote:
> Wolfgang Grandegger wrote:
>> Hi David,
>>
>> David Miller wrote:
>>> From: Anatolij Gustschin
>>> Date: Tue, 9 Feb 2010 15:23:17 +0100
>>>
In my understanding, in the ESP scsi driver the set of defines for
the register offs
On Wed, Feb 10, 2010 at 3:53 AM, Wolfgang Grandegger
wrote:
> Stephen Rothwell wrote:
>> Hi Wolfgang,
>>
>> On Wed, 10 Feb 2010 11:09:25 +0100 Wolfgang Grandegger
>> wrote:
__devinitdata goes at the end, immediately before the '='. Ditto
throughout the file.
>>> This made a differenc
This patch adds support for boards with more that 512MByte RAM. Currently
only 512MB of memory are enabled in the DCCR/ICCR real-mode cache
control registers. This patch now enables caching in real-mode for
2GByte.
Signed-off-by: Stefan Roese
Cc: Benjamin Herrenschmidt
Cc: Josh Boyer
---
arch/
Nick Piggin discovered that lwsync barriers around locks were faster than isync
on 970. That was a long time ago and I completely dropped the ball in testing
his patches across other ppc64 processors.
Turns out the idea helps on other chips. Using a microbenchmark that
uses a lot of threads to co
For performance reasons we are about to change ISYNC_ON_SMP to sometimes be
lwsync. Now that the macro name doesn't make sense, change it and LWSYNC_ON_SMP
to better explain what the barriers are doing.
Signed-off-by: Anton Blanchard
---
Index: powerpc.git/arch/powerpc/include/asm/atomic.h
do_lwsync_fixups doesn't work on 64bit, we end up writing lwsyncs to the
wrong addresses:
0:mon> di c001000bfacc
c001000bfacc 7c2004ac lwsync
Since the lwsync section has negative offsets we need to use a signed int
pointer so we sign extend the value.
Signed-off-by: Anton Blancha
This patch implements the lwarx/ldarx hint bit for bit locks.
Signed-off-by: Anton Blanchard
---
Index: powerpc.git/arch/powerpc/include/asm/asm-compat.h
===
--- powerpc.git.orig/arch/powerpc/include/asm/asm-compat.h 2010-02-1
Now we have real bit locks use them instead of open coding it.
Signed-off-by: Anton Blanchard
---
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 056d23a..9e1aa4f 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -122,
Recent versions of the PowerPC architecture added a hint bit to the larx
instructions to differentiate between an atomic operation and a lock operation:
> 0 Other programs might attempt to modify the word in storage addressed by EA
> even if the subsequent Store Conditional succeeds.
>
> 1 Other
Stephen Rothwell wrote:
> Hi Wolfgang,
>
> On Wed, 10 Feb 2010 11:09:25 +0100 Wolfgang Grandegger
> wrote:
>>> __devinitdata goes at the end, immediately before the '='. Ditto
>>> throughout the file.
>> This made a difference and revealed section mismatches. "const" seems to
>> be incompatible
Hi Wolfgang,
On Wed, 10 Feb 2010 11:09:25 +0100 Wolfgang Grandegger
wrote:
>
> > __devinitdata goes at the end, immediately before the '='. Ditto
> > throughout the file.
>
> This made a difference and revealed section mismatches. "const" seems to
> be incompatible with "__devinitdata".
Maybe
Wolfgang Grandegger wrote:
> Hi David,
>
> David Miller wrote:
>> From: Anatolij Gustschin
>> Date: Tue, 9 Feb 2010 15:23:17 +0100
>>
>>> In my understanding, in the ESP scsi driver the set of defines for
>>> the register offsets is common for all chip drivers. The chip driver
>>> methods for reg
On Wed, Feb 10, 2010 at 11:05:28AM +0100, Wolfgang Grandegger wrote:
> From: Wolfgang Grandegger
>
> To prepare support for the MPC512x processors from Freescale the
> "setclock" initialization functions have been renamed to "setup"
> because I2C interrupts must be enabled for the MPC512x by thi
Grant Likely wrote:
> On Thu, Jan 28, 2010 at 6:25 AM, Wolfgang Grandegger
> wrote:
>> From: Wolfgang Grandegger
>>
>> "__devinit[data]" has not yet been used for all initialization functions
>> and data. To avoid truncating lines, the struct "mpc_i2c_match_data" has
>> been renamed to "mpc_i2c_
From: Wolfgang Grandegger
This patch series adds support for the MPC512x from Freescale to the
i2c-mpc driver. At that occasion, issues with __devinit[data] have
been fixed and the doc of the FSL I2C dts bindings updated. It has
been tested on a MPC5121ADS, TQM5200 and TQM8560 board
Changes sin
From: Wolfgang Grandegger
As I2C interrupts must be enabled for the MPC512x by the setup function
as well, "fsl,preserve-clocking" is handled in a slighly different way.
Also, the old settings are now reported calling dev_dbg(). For the
MPC512x the clock setup function of the MPC52xx can be re-u
From: Wolfgang Grandegger
"__devinit[data]" has not yet been used for all initialization functions
and data. To avoid truncating lines, the struct "mpc_i2c_match_data" has
been renamed to "mpc_i2c_data", which is even the better name.
Signed-off-by: Wolfgang Grandegger
Tested-by: Wolfram Sang
From: Wolfgang Grandegger
To prepare support for the MPC512x processors from Freescale the
"setclock" initialization functions have been renamed to "setup"
because I2C interrupts must be enabled for the MPC512x by this
function as well.
Signed-off-by: Wolfgang Grandegger
---
drivers/i2c/busse
From: Wolfgang Grandegger
This patch adds the MPC5121 to the list of supported devices,
enhances the doc of the "clock-frequency" property and removes
the obsolete "cell-index", "device_type" and "fsl-i2c" property.
Furthermore an example for the MPC5121 has been added.
Signed-off-by: Wolfgang G
Hi David,
David Miller wrote:
> From: Anatolij Gustschin
> Date: Tue, 9 Feb 2010 15:23:17 +0100
>
>> In my understanding, in the ESP scsi driver the set of defines for
>> the register offsets is common for all chip drivers. The chip driver
>> methods for register access translate the offsets bec
Sync Arches dts with latest Canyonlands version:
- Add 16k FIFO size to supported EMAC nodes
- Add next-level-cache property
- Add Crypto device node
Signed-off-by: Stefan Roese
Cc: Josh Boyer
---
arch/powerpc/boot/dts/arches.dts | 12
1 files changed, 12 insertions(+), 0 deleti
Also set L2C_CFG_RDBW on 460GT platforms and not only on 460EX.
Signed-off-by: Stefan Roese
Cc: Josh Boyer
---
arch/powerpc/sysdev/ppc4xx_soc.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/sysdev/ppc4xx_soc.c b/arch/powerpc/sysdev/ppc4xx_soc.c
index 5b
Sync Glacier dts with latest Canyonlands version:
- Add l2 cache support
- Add NDFC support
- Add RTC support
- Add AD7414 hwmon support
- Change EMAC compatible node from emac4 to emac4sync and correct the
register size
- Add support for ISA holes on 4xx PCI/X/E
(as done in Benjamin Herrensch
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