On Fri, Sep 4, 2009 at 4:14 PM, Alemao wrote:
> I've read some posts in the list, and about:
>
> irq_of_parse_and_map()
> irq_create_map()
>
> But Im still trying to understand MPC85xx TSEC1 dts.
>
> Gianfar driver is using request_irq(), and request_irq() uses virtual
> irq, right?
>
> Thats why i
I've read some posts in the list, and about:
irq_of_parse_and_map()
irq_create_map()
But Im still trying to understand MPC85xx TSEC1 dts.
Gianfar driver is using request_irq(), and request_irq() uses virtual
irq, right?
Thats why in dts all irqs for TSEC1 are "offseted" of 16?
Manual | DTS
-
Hi all,
In all MPC85xx DTS files I have seen this interrupt configuration for
TSEC1:
interrupts = <29 2 30 2 34 2>;
29 - TSEC1 interrupt transmit
30 - TSEC1 interrupt receive
34 - TSEC1 interrupt error
But in MPC8555RM, chapter 10.1.5.2 the numbers are these:
13 - TSEC1 interrupt transmit
14
On Sat, Jul 18, 2009 at 02:01:45PM +0200, Ingo Molnar wrote:
>
> * Anton Vorontsov wrote:
>
> > On Wed, Jun 17, 2009 at 12:16:30AM +0400, Anton Vorontsov wrote:
> > > According to Segher Boessenkool and GCC manual, -fomit-frame-pointer
> > > is only the default when optimising on archs/ABIs wher
On Thu, Aug 27, 2009 at 09:41:59PM -0700, David Brownell wrote:
> On Tuesday 18 August 2009, Anton Vorontsov wrote:
>
> > - Fix build issues in fsl_qe_udc;
> > - Some minor cosmetic changes in "Add support for QE DMA mode and
> > CPM1/CPM2 chips" patch.
>
> Hmm ... the first four of these are p
On Fri, Sep 4, 2009 at 9:38 AM, Sebastian Andrzej
Siewior wrote:
> Grant Likely wrote:
> > What version of the kernel are you using? The line numbers don't
>>
>> match up with kernel mainline, so I wonder if this is before or after
>> the OF MDIO rework changes.
>
> It is the kernel which was shi
Grant Likely wrote:
> What version of the kernel are you using? The line numbers don't
match up with kernel mainline, so I wonder if this is before or after
the OF MDIO rework changes.
It is the kernel which was shipped in ads5121's bsp which is 2.6.24.
Regardless, this doesn't look right.
Hi all,
In all MPC85xx DTS files I have seen this interrupt configuration for
TSEC1:
interrupts = <29 2 30 2 34 2>;
29 - TSEC1 interrupt transmit
30 - TSEC1 interrupt receive
34 - TSEC1 interrupt error
But in MPC8555RM, chapter 10.1.5.2 the numbers are these:
13 - TSEC1 interrupt transmit
14
The following patch is needed to correctly assign the IRQs for the gianfar
driver on the MPC8313ERDB-revc boards. ERR and TX are swapped as well as the
interrupt lines for the two devices.
Signed-off-by: Roland Lezuo
---
arch/powerpc/boot/dts/mpc8313erdb.dts |4 ++--
1 files changed, 2 in
On Sat, 2009-06-13 at 18:45 +0200, Albrecht Dreß wrote:
> Am 11.06.09 19:28 schrieb(en) Grant Likely:
> > So; the solution to me seems to be on an MPC5200 platform replace the
> > offending hooks with MPC5200 specific variants at runtime.
>
> Will re-work the patch that way! BTW, a dumb questio
Currently we have a fair bit of rather fiddly code to manage the
various kmem_caches used to store page tables of various levels. We
generally have two caches holding some combination of PGD, PUD and PMD
tables, plus several more for the special hugepage pagetables.
This patch cleans this all up
Currently each available hugepage size uses a slightly different
pagetable layout: that is, the bottem level table of pointers to
hugepages is a different size, and may branch off from the normal page
tables at a different level. Every hugepage aware path that needs to
walk the pagetables must the
Currently, hpte_need_flush() only correctly flushes the given address
for normal pages. Callers for hugepages are required to mask the
address themselves.
But hpte_nned_flush() already looks up the page sizes for its own
reasons, so this is a rather silly imposition on the callers. This
patch al
Currently, ordinary pages use one pagetable layout, and each different
hugepage size uses a slightly different variant layout. A number of
places which need to walk the pagetable must first check the slice map
to see what the pagetable layout then handle the various different
forms. New hardware,
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