A change to the i2c subsystem breaks the warp platform code. The patch
is cleaner anyway, the old way was a bit crufty.
For those with keen eyes, the gratuitous change in the string from
PIKA to Warp is just so the logs look a bit nicer. The following two
lines tend to be printed one after another
On Fri, 2009-06-19 at 18:24 +1000, Michael Ellerman wrote:
> I think we /probably/ want a similar change in legacy_serial.c, for
> soc
> ports at least.
>
> Or do people have things that are compatible "ns16550" but aren't?
>
Do we really want to keep of_serial.c ?
I fail to see the point in kee
On Fri, 2009-06-19 at 22:36 +0530, Sachin Sant wrote:
> The offending commit seems to be
> c868d550115b9ccc0027c67265b9520790f05601.
> mm: Move pgtable_cache_init() earlier
>
> If i revert this commit, the machine boots fine.
That is strange. If I revert that commit, I get breakages on machines
h
The kernel reserves the I/O address space from 0x0 to 0xfff for legacy
ISA devices. Change the ranges property for the PCI2ISA bridge to match
the kernels behavior, even if the ranges property isn't used for now.
Signed-off-by: Gerhard Pircher
---
arch/powerpc/boot/dts/amigaone.dts |4 ++--
This allows to remove the ppc_md.init() hook in the setup code.
Signed-off-by: Gerhard Pircher
---
arch/powerpc/platforms/amigaone/setup.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/amigaone/setup.c
b/arch/powerpc/platforms/amigaone/setu
You will have to program GPIO's to select appropriate external IRQ as
they are shared .
From: linuxppc-dev-bounces+tmarri=amcc@lists.ozlabs.org
[mailto:linuxppc-dev-bounces+tmarri=amcc@lists.ozlabs.org] On Behalf
Of Lada Podivin
Sent: Friday, June 19, 2009 1:01 AM
To: linuxppc-dev@lists
Use the DMA_SLAVE capability of the DMAEngine API to copy/from a
scatterlist into an arbitrary list of hardware address/length pairs.
This allows a single DMA transaction to copy data from several different
devices into a scatterlist at the same time.
This also adds support to enable some control
When using the Freescale DMA controller in external control mode, both the
request count and external pause bits need to be setup correctly. This was
being done with the same function.
The 83xx controller lacks the external pause feature, but has a similar
feature called external start. This featu
On Thu, 18 Jun 2009 00:14:08 +0400
Anton Vorontsov wrote:
> Some hosts (hardware configurations, or particular SD/MMC slots) may
> not support 4-bit bus. For example, on MPC8569E-MDS boards we can
> switch between serial (1-bit only) and nibble (4-bit) modes, thought
> we have to disable more per
Albrecht Dreß wrote:
This trivial patch changes memcpy_(to|from)io as to transfer as many
32-bit words as possible in 32-bit accesses (in the current solution,
the last 32-bit word was transferred as 4 byte accesses).
Signed-off-by: Albrecht Dreß
---
diff -urpN -X linux-2.6.29.1.orig/Documen
On Thu, Jun 18, 2009 at 03:53:45PM -0700, Ira Snyder wrote:
> Use the DMA_SLAVE capability of the DMAEngine API to copy/from a
> scatterlist into an arbitrary list of hardware address/length pairs.
>
> This allows a single DMA transaction to copy data from several different
> devices into a scatte
Could you please try the following patch, I am quite sure that checking
for > 4 was accidentially done within io.c instead of >= 4 as if it's 4
we still can copy a 32-bit word. Some hardware might not be happy about
8-bit accesses...
Index: 2.6.30-source/arch/powerpc/kernel/io.c
==
Am 19.06.09 19:06 schrieb(en) Lorenz Kolb:
Could you please try the following patch, I am quite sure that
checking for > 4 was accidentially done within io.c instead of >= 4
as if it's 4 we still can copy a 32-bit word. Some hardware might not
be happy about 8-bit accesses...
I submitted t
On Fri, Jun 19, 2009 at 07:06:18PM +0200, Lorenz Kolb wrote:
> Could you please try the following patch, I am quite sure that checking
> for > 4 was accidentially done within io.c instead of >= 4 as if it's 4
> we still can copy a 32-bit word. Some hardware might not be happy about
> 8-bit a
Could you please try the following patch, I am quite sure that checking
for > 4 was accidentially done within io.c instead of >= 4 as if it's 4
we still can copy a 32-bit word. Some hardware might not be happy about
8-bit accesses...
Index: 2.6.30-source/arch/powerpc/kernel/io.c
==
Sachin Sant wrote:
2.6.30-git14 (0732f87761dbe417cb6e084b712d07e879e876ef) fails to boot
on various PowerPC machines. Here are last few boot messages from a
Power6
box.
I will go back and check what changes between git10 and git11
could have caused this boot failure.
The offending commit
* Paul Mackerras wrote:
> Ingo Molnar writes:
>
> > Note, i left out this bit from the commit - we need to find a
> > better solution than to allow ugly warnings on PowerPC.
> >
> > Could we use the kernel's u64 type directly perhaps? That would
> > allow us to change all __u64 to u64 in all
On Jun 19, 2009, at 10:31 AM, Anton Vorontsov wrote:
On Thu, Jun 18, 2009 at 09:25:46PM -0500, Kumar Gala wrote:
On Jun 18, 2009, at 6:37 PM, Anton Vorontsov wrote:
For yet unknown reason 4-bit mode doesn't work on MPC8569E-MDS
boards,
so make 1-bit mode default. When we resolve the issue
On Thu, Jun 18, 2009 at 09:25:46PM -0500, Kumar Gala wrote:
>
> On Jun 18, 2009, at 6:37 PM, Anton Vorontsov wrote:
>
>> For yet unknown reason 4-bit mode doesn't work on MPC8569E-MDS boards,
>> so make 1-bit mode default. When we resolve the issue, u-boot will
>> remove sdhci,1-bit-only property f
On Fri, Jun 19, 2009 at 7:25 AM, Anton
Vorontsov wrote:
> Surely we can hide the bridge into the SPI controller driver,
> but I think it would be beneficial to "factor-out" it to a
> stand-alone entity, so that other SPI controllers could work
> with this setup without any modifications (oh and btw
This patch adds the possibility to have a spi device without a cs.
For example, the dts file should look something like this:
spi-controller {
gpios = <&pio1 1 0 /* cs0 */
0 /* cs1, no GPIO */
&pio2 2 0>;/* cs2 */
This feature is need
When a process tries to read/write a disconnected i2c device, it receives a
signal (e.g. ctrl-c) and the kernel gets stuck.
BUG: soft lockup - CPU#0 stuck for 61s! [I2CEEpromTest:392]
NIP: c01628f8 LR: c01628f0 CTR: c00177cc
REGS: c39abd70 TRAP: 0901 Not tainted (2.6.25.7-alcore)
MSR: 9032
On Fri, Jun 19, 2009 at 09:26:08AM +0200, Rini van Zetten wrote:
> This patch adds the possibility to have a spi device without a cs.
>
> For example, the dts file should look something like this:
>
> spi-controller {
>gpios = <&pio1 1 0 /* cs0 */
> 0 /* cs
On Fri, Jun 19, 2009 at 01:45:46PM +0200, Leon Woestenberg wrote:
> Hello,
>
> On Thu, Jun 18, 2009 at 4:04 PM, Kumar Gala wrote:
> > On Jun 18, 2009, at 8:09 AM, Anton Vorontsov wrote:
> >> On Thu, Jun 18, 2009 at 08:19:44AM +0200, Rini van Zetten wrote:
> >>>
> >>> This patch adds the possibilit
Hi,
I'm writing a linux driver that uses an external interrupt (ppc 405ex). I'm
using GPIO pin 30 (external IRQ 1) connected to UIC1. I'm aware of the
virtual interrupt stuff, so I added a new node to my device tree in order to
get proper virtual IRQ number. This node describes an external event an
Hello,
On Thu, Jun 18, 2009 at 4:04 PM, Kumar Gala wrote:
> On Jun 18, 2009, at 8:09 AM, Anton Vorontsov wrote:
>> On Thu, Jun 18, 2009 at 08:19:44AM +0200, Rini van Zetten wrote:
>>>
>>> This patch adds the possibility to have a spi device without a cs.
>>>
> That is a good question. What HW is
On Jun 19, 2009, at 2:26 AM, Rini van Zetten wrote:
This patch adds the possibility to have a spi device without a cs.
For example, the dts file should look something like this:
spi-controller {
gpios = <&pio1 1 0 /* cs0 */
0 /* cs1, no GPIO */
The old PowerSurge SMP (ie, dual or quad 604 machines) code has
numerous issues in modern world.
One is cpu_possible_map is set too late (the device-tree is bogus)
so we fail to allocate the interrupt stacks and crash. Another
problem is the fact the timebase is frozen by the bringup of the
second
lockdep trace found the following:
[ cut here ]
Badness at c007baf0 [verbose debug info unavailable]
NIP: c007baf0 LR: c007bad8 CTR:
REGS: ef855e00 TRAP: 0700 Tainted: GW
(2.6.30-06736-g12a31df-dirty)
MSR: 00021000 CR: 24044022 XER: 2000
TASK = ef8
Original-Nachricht
> Datum: Thu, 18 Jun 2009 09:38:50 -0500
> Von: Kumar Gala
> An: Gerhard Pircher , Benjamin Herrenschmidt
>
> CC: linuxppc-dev list
> Betreff: killing use of ppc_md.init
> ppc_md.init only exists on ppc32 and seems like its pretty useless
> today. The u
For some reason we've had an explicit KERN_INFO for GPR dumps. With
recent changes we get output like:
<6>GPR00: ef855eb0 ef858000 0001 00d0 f100 ffbc8000
The KERN_INFO is causing the <6>. Don't see any reason to keep it
around.
Signed-off-by: Kumar Gala
---
ar
On Tue, 2009-06-09 at 18:39 -0500, Dave Mitchell wrote:
> This patch adds the UPF_FIXED_TYPE flag which will bypass the
> 8250's autoconfig probe for uart type. The uart type identified
> by the of_serial's parse of the flat device tree will be utilized
> as defined.
>
> Signed-off-by: Dave Mitche
Ingo Molnar writes:
> Note, i left out this bit from the commit - we need to find a better
> solution than to allow ugly warnings on PowerPC.
>
> Could we use the kernel's u64 type directly perhaps? That would
> allow us to change all __u64 to u64 in all of tools/perf/ which is a
> nice clean-
Since we can use kmalloc earlier we are getting the following since the
mpic_alloc() code calls alloc_bootmem(). Move to using kzalloc() to
remove the warning.
[ cut here ]
Badness at c0583248 [verbose debug info unavailable]
NIP: c0583248 LR: c0583210 CTR: 0004
REGS:
On Jun 17, 2009, at 10:43 PM, Benjamin Herrenschmidt wrote:
Based on initial work from: Dale Farnsworth
Add the low level irq tracing hooks for 32-bit powerpc needed
to enable full lockdep functionality.
The approach taken to deal with the code in entry_32.S is that
we don't trace all the tr
On Jun 19, 2009, at 2:26 AM, Rini van Zetten wrote:
This patch adds the possibility to have a spi device without a cs.
For example, the dts file should look something like this:
spi-controller {
gpios = <&pio1 1 0 /* cs0 */
0 /* cs1, no GPIO */
This patch adds the possibility to have a spi device without a cs.
For example, the dts file should look something like this:
spi-controller {
gpios = <&pio1 1 0 /* cs0 */
0 /* cs1, no GPIO */
&pio2 2 0>;/* cs2 */
Signed-off-by: Rini
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