the patches needed so that it
applies properly, but I've finally been able to test it on a Sinlinx
SinA33 with peripheral-only mUSB, and it works like a charm.
You can add my Tested-by.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-ele
Hi,
On Wed, Jun 08, 2016 at 12:30:20PM +0200, Hans de Goede wrote:
> Hi,
>
> On 08-06-16 12:23, Maxime Ripard wrote:
> >Hi,
> >
> >On Sun, Jun 05, 2016 at 04:59:36PM +0200, Hans de Goede wrote:
> >>phy-sun4i-usb now has proper dr_mode handling, it always
the
is_otg variable is never set to true, and thus, the function
ci_hdrc_otg_init is never called. This is problematic since it
registers the set_peripheral callback, that is called later in the
function if the gadget role is defined. And I believe that this is
what actually triggers the pani
Hi Peter,
Thanks for your answer.
On 09/01/2013 04:23, Peter Chen wrote:
> On Tue, Jan 08, 2013 at 04:27:21PM +0100, Maxime Ripard wrote:
>> Hi Peter,
>>
>> On 27/12/2012 07:59, Peter Chen wrote:
>>> (Sorry for update slowly due to long time business trip)
>>
Commit 09f6ffde introduced a dependency on USB_EHCI_HCD for the chipidea
USB host driver, that in turns depends on USB_ARCH_HAS_EHCI.
If this symbol is not set for MXS, the MXS boards are not able to use the
chipidea driver anymore.
Signed-off-by: Maxime Ripard
---
drivers/usb/Kconfig |1
anymore.
Signed-off-by: Maxime Ripard
---
drivers/usb/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 4c90b51..640ae6c 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -37,6 +37,7 @@ config USB_ARCH_HAS_EHCI
On Wed, Nov 30, 2016 at 02:57:35PM +0900, Chanwoo Choi wrote:
> This patch just uses the resource-managed extcon API when registering
> the extcon notifier.
>
> Signed-off-by: Chanwoo Choi
Acked-by: Maxime Ripard
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linu
On Tue, Jan 03, 2017 at 11:25:33PM +0800, Icenowy Zheng wrote:
> V3s SoC features a USB PHY controller and a MUSB OTG controller.
>
> Add device nodes for them.
>
> Signed-off-by: Icenowy Zheng
This can be merged in your other DTSI patch.
Maxime
--
Maxime Ripard, Free Ele
On Tue, Jan 03, 2017 at 11:25:32PM +0800, Icenowy Zheng wrote:
> Allwinner H3/V3s features a variant of MUSB controller, which lacks one
> endpoint.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripard
Thanks,
Maxime
--
Maxime Ripard, Free
On Tue, Jan 03, 2017 at 11:25:31PM +0800, Icenowy Zheng wrote:
> Allwinner V3s come with a USB PHY controller slightly different to other
> SoCs, with only one PHY.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripard
Thanks,
Maxime
--
M
in dtsi instead?
> > >
> > > Regards,
> > > -Bin.
> >
> > There's possibly boards which do not have OTG functions.
>
> That is board specific.
Exactly, and this is why it should be done in the board DT.
The controller in the Allwinner SoCs do not handle directly the ID pin
and VBUS, but rather rely on a GPIO to do so.
So boards with OTG will need setup anyway, at least to tell which
GPIOs are used. There's no point in enforcing a default if it doesn't
work by default.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Hi Bin,
On Thu, Jan 12, 2017 at 08:50:14AM -0600, Bin Liu wrote:
> On Wed, Jan 11, 2017 at 10:06:38PM +0100, Maxime Ripard wrote:
> > On Wed, Jan 11, 2017 at 02:08:11PM -0600, Bin Liu wrote:
> > > On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote:
> > > >
at? What's wrong with it?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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On Wed, Jan 18, 2017 at 12:57:08AM +0800, Icenowy Zheng wrote:
>
>
> 17.01.2017, 16:06, "Maxime Ripard" :
> > On Tue, Jan 17, 2017 at 03:14:46AM +0800, Icenowy Zheng wrote:
> >> The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
> >>
On Wed, Jan 18, 2017 at 04:09:32AM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Wed, Jan 18, 2017 at 4:06 AM, Maxime Ripard
> wrote:
> > On Wed, Jan 18, 2017 at 12:57:08AM +0800, Icenowy Zheng wrote:
> >>
> >>
> >> 17.01.2017, 16:06, "Maxime Ripard&
pretty much the pattern used everywhere else
(irqs, regulator, clocks, etc.), so it's going to be easier to review
as well.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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On Mon, Dec 14, 2015 at 10:50:55AM +0100, Philipp Zabel wrote:
> Am Montag, den 14.12.2015, 10:36 +0100 schrieb Maxime Ripard:
> > Hi,
> >
> > On Fri, Dec 11, 2015 at 04:41:58PM +0100, Hans de Goede wrote:
> > > diff --git a/include/linux/reset.h b/include/lin
On Wed, Dec 16, 2015 at 12:21:48PM +0100, Philipp Zabel wrote:
> Hi Maxime,
>
> Am Mittwoch, den 16.12.2015, 11:29 +0100 schrieb Maxime Ripard:
> > On Mon, Dec 14, 2015 at 10:50:55AM +0100, Philipp Zabel wrote:
> > > Am Montag, den 14.12.2015, 10:36 +0100 schrieb M
0%)
That would be allwinner in this case, sunxi is the SoC family
Allwinner produces.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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rom []
(cpu_idle+0x60/0xec)
[2.403990] [] (cpu_idle+0x60/0xec) from []
(start_kernel+0x260/0x2a0)
[2.412291] [] (start_kernel+0x260/0x2a0) from [<40008040>]
(0x40008040)
--
Maxime Ripard, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training
Hi Alexander,
Thanks for your reply.
Le 06/03/2013 14:43, Alexander Shishkin a écrit :
> On 6 March 2013 12:33, Maxime Ripard
> wrote:
>> Just noticed this in 3.9-rc1 on an iMX28 (ARM) board with a config
>> based on mxs_defconfig. I'm using the patchset "Add t
Hi Peter,
Le 07/03/2013 09:08, Peter Chen a écrit :
> On Wed, Mar 06, 2013 at 11:33:02AM +0100, Maxime Ripard wrote:
>> [2.149645] other info that might help us debug this:
>> [2.149645]
>> [2.157667] Possible unsafe locking scenario:
>> [2.157667]
&g
t, that
manages both the reset, regulators and clocks, and loads both the ohci
and ehci layers. bcma-hcd seems to be doing exactly that for example.
Maxime
--
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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ant is to access the clocks by
index, that you can do with of_clk_get.
Calling it "bus" and "phy" or whatever it's used for both provide a
way of differentiating the two, yet being rather generic. And if we
need to add a third one, I'm pretty sure we will be able to come up
with a generic name then.
Maxime
--
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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s)
> +{
> + struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
> +
> + if (WARN_ON(args->args[0] == 0 || args->args[0] >= data->num_phys))
> + return ERR_PTR(-ENODEV);
> +
> + return data->phys[args->args[0]].phy;
> +}
>
my previous serie to introduce support
for the the A385 AP board.
Thanks,
Maxime
Maxime Ripard (4):
usb: phy: Fix deferred probing
usb: XHCI: platform: Move the Marvell quirks after the enabling the
clocks
usb: xhci: plat: Add USB phy support
ARM: mvebu: armada-385-ap: Enable USB3 port
The Armada 385 AP board has a USB3 port exposed that uses a GPIO to drive the
VBUS line. Enable the needed drivers to support this.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/armada-385-ap.dts | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm
The Marvell Armada 385 AP needs a dumb phy in order to enable the USB3 VBUS.
Add a call to retrieve a USB PHY to XHCI plat in order to support this.
Signed-off-by: Maxime Ripard
---
drivers/usb/host/xhci-plat.c | 13 +
drivers/usb/host/xhci.h | 2 ++
2 files changed, 15
art
of its error path, the driver will rightfully disable the clock. When the
driver will be reprobed, it will retry to access the MBUS registers, but this
time with the clock disabled, which hangs forever.
Fix this by running the quirks after the clock has been enabled by the driver.
Signed-off-
d by the caller, and ENODEV if try_module_get fails.
Signed-off-by: Maxime Ripard
---
drivers/usb/phy/phy.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/phy/phy.c b/drivers/usb/phy/phy.c
index b4066a001ba0..353c686498d4 100644
--- a/drivers/usb/phy/phy.c
++
t at least for the DT that are
in Linux, relying on the fact that there is no driver having a
compatible of "usb-ehci" to work looks very fragile. I'd be in favour
of removing it from the OMAP DTs, and every affected DTs.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-sunxi.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a
The OHCI controllers used in the Allwinner A31 are asserted in reset using a
global reset controller.
Add optional support for such a controller in the OHCI platform driver.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/usb/usb-ohci.txt | 1 +
drivers/usb/host/ohci
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts
d-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/usb/usb-ehci.txt | 1 +
drivers/usb/host/ehci-platform.c | 25 +-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt
b/Document
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard
---
drivers/phy/phy-sun4i-usb.c | 35 ++-
1
one
for all the PHYs.
Thanks,
Maxime
Boris BREZILLON (2):
usb: ehci-platform: add optional reset controller retrieval
ARM: sunxi: dt: add APP4-EVB1 board support
Maxime Ripard (5):
clk: sunxi: Implement A31 USB clock
ARM: sun6i: Add the USB clocks to the DTSI.
phy: usb: sunxi: Introduce
From: Boris BREZILLON
The APP4 EVB1 development boards embeds an A31, together with some NAND, one SD
card slot, and one SDIO + UART WiFi and Bluetooth chip, a few I2C buses, USB,
and a LCD display.
Signed-off-by: Boris BREZILLON
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/Makefile
On Wed, May 07, 2014 at 07:05:30PM +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Wednesday 07 May 2014 09:20 AM, Maxime Ripard wrote:
> > The USB phy controller in the A31 differs mostly from the older controllers
> > because it has a clock dedicated for each phy, whil
On Wed, May 07, 2014 at 08:26:39PM +0400, Sergei Shtylyov wrote:
> Hello.
>
> On 07-05-2014 7:50, Maxime Ripard wrote:
>
> >The OHCI controllers used in the Allwinner A31 are asserted in reset using a
>
>s/asserted/powered up/?
No. There's an external reset co
On Wed, May 07, 2014 at 10:25:55AM -0400, Alan Stern wrote:
> On Tue, 6 May 2014, Maxime Ripard wrote:
>
> > From: Boris BREZILLON
> >
> > On the Allwinner's A31 SoC the reset line connected to the EHCI IP has to
> > be deasserted for the EHCI block to be
On Thu, May 08, 2014 at 10:07:25AM -0400, Alan Stern wrote:
> On Thu, 8 May 2014, Hans de Goede wrote:
>
> > Hi,
> >
> > On 05/08/2014 12:00 AM, Maxime Ripard wrote:
> > > On Wed, May 07, 2014 at 10:25:55AM -0400, Alan Stern wrote:
> > >
From: Boris BREZILLON
The APP4 EVB1 development boards embeds an A31, together with some NAND, one SD
card slot, and one SDIO + UART WiFi and Bluetooth chip, a few I2C buses, USB,
and a LCD display.
Signed-off-by: Boris BREZILLON
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31
d-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
Documentation/devicetree/bindings/usb/usb-ehci.txt | 1 +
drivers/usb/host/ehci-platform.c | 18 ++
2 files changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.t
controller retrieval
ARM: sunxi: dt: add APP4-EVB1 board support
Maxime Ripard (5):
clk: sunxi: Implement A31 USB clock
ARM: sun6i: Add the USB clocks to the DTSI.
phy: usb: sunxi: Introduce Allwinner A31 USB PHY support
usb: ohci-platform: Enable optional use of reset controller
ARM: sun6i
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
drivers/phy/phy-sun4i-usb.c | 35
The OHCI controllers used in the Allwinner A31 are asserted in reset using a
global reset controller.
Add optional support for such a controller in the OHCI platform driver.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
Documentation/devicetree/bindings/usb/usb-ohci.txt | 1
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
drivers/clk/sunxi/clk-sunxi.c | 6 ++
1 file changed, 6
de
> outside the "if" statement, so it applies to all devices?
Hmmm, I did this because so far, the reset framework only handles the
DT case. But that's right that it can be extended in the future, I'll
update it.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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On Mon, May 12, 2014 at 05:14:26PM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Sat, May 10, 2014 at 8:56 PM, Maxime Ripard
> wrote:
> > The USB phy controller in the A31 differs mostly from the older controllers
> > because it has a clock dedicated for each phy, while the old
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
drivers/phy/phy-sun4i-usb.c | 33
The OHCI controllers used in the Allwinner A31 are asserted in reset using a
global reset controller.
Add optional support for such a controller in the OHCI platform driver.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
Documentation/devicetree/bindings/usb/usb-ohci.txt | 1
retrieval
ARM: sunxi: dt: add APP4-EVB1 board support
Maxime Ripard (6):
clk: sunxi: Implement A31 USB clock
ARM: sun6i: Add the USB clocks to the DTSI.
phy: sunxi: Rework phy initialization
phy: usb: sunxi: Introduce Allwinner A31 USB PHY support
usb: ohci-platform: Enable optional use of
From: Boris BREZILLON
The APP4 EVB1 development boards embeds an A31, together with some NAND, one SD
card slot, and one SDIO + UART WiFi and Bluetooth chip, a few I2C buses, USB,
and a LCD display.
Signed-off-by: Boris BREZILLON
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
d-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
Documentation/devicetree/bindings/usb/usb-ehci.txt | 1 +
drivers/usb/host/ehci-platform.c | 17 +
2 files changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.t
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31
Move the phy initialization and variables declaration to the loop itself, since
it is where it really belongs. Also remove all the temporary variables, we can
use the structure members directly.
Signed-off-by: Maxime Ripard
---
drivers/phy/phy-sun4i-usb.c | 44
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
drivers/clk/sunxi/clk-sunxi.c | 6 ++
1 file changed, 6
On Mon, May 12, 2014 at 04:06:16PM -0400, Alan Stern wrote:
> On Mon, 12 May 2014, Maxime Ripard wrote:
>
> > From: Boris BREZILLON
> >
> > On the Allwinner's A31 SoC the reset line connected to the EHCI IP has to
> > be deasserted for the EHCI block to be
From: Boris BREZILLON
The APP4 EVB1 development boards embeds an A31, together with some NAND, one SD
card slot, and one SDIO + UART WiFi and Bluetooth chip, a few I2C buses, USB,
and a LCD display.
Signed-off-by: Boris BREZILLON
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31
function instead of the
private structure since it was the only user
Boris BREZILLON (2):
usb: ehci-platform: add optional reset controller retrieval
ARM: sunxi: dt: add APP4-EVB1 board support
Maxime Ripard (6):
clk: sunxi: Implement A31 USB clock
ARM: sun6i: Add the USB clocks to the DTSI
The OHCI controllers used in the Allwinner A31 are asserted in reset using a
global reset controller.
Add optional support for such a controller in the OHCI platform driver.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
Documentation/devicetree/bindings/usb/usb-ohci.txt | 1
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
Acked-by: Mike Turquette
---
drivers/clk/sunxi/clk-sunxi.c | 6
d-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
Documentation/devicetree/bindings/usb/usb-ehci.txt | 1 +
drivers/usb/host/ehci-platform.c | 26 +++---
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/us
Move the phy initialization and variables declaration to the loop itself, since
it is where it really belongs. Also remove all the temporary variables, we can
use the structure members directly.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
drivers/phy/phy-sun4i-usb.c | 42
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
drivers/phy/phy-sun4i-usb.c | 33
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
Acked-by: Mike Turquette
---
drivers/clk/sunxi/clk-sunxi.c | 6
The OHCI controllers used in the Allwinner A31 are asserted in reset using a
global reset controller.
Add optional support for such a controller in the OHCI platform driver.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
Acked-by: Alan Stern
---
Documentation/devicetree/bindings/usb
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31
d-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
Acked-by: Alan Stern
---
Documentation/devicetree/bindings/usb/usb-ehci.txt | 1 +
drivers/usb/host/ehci-platform.c | 26 +++---
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/Document
reset assertion/deassertion to probe/remove
- Moved the dedicated_clocks to the probe function instead of the
private structure since it was the only user
Boris BREZILLON (2):
usb: ehci-platform: add optional reset controller retrieval
ARM: sunxi: dt: add APP4-EVB1 board support
Maxime R
From: Boris BREZILLON
The APP4 EVB1 development boards embeds an A31, together with some NAND, one SD
card slot, and one SDIO + UART WiFi and Bluetooth chip, a few I2C buses, USB,
and a LCD display.
Signed-off-by: Boris BREZILLON
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
drivers/phy/phy-sun4i-usb.c | 33
Move the phy initialization and variables declaration to the loop itself, since
it is where it really belongs. Also remove all the temporary variables, we can
use the structure members directly.
Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
---
drivers/phy/phy-sun4i-usb.c | 42
On Wed, May 14, 2014 at 11:18:51AM +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 13 May 2014 09:14 PM, Maxime Ripard wrote:
> > Move the phy initialization and variables declaration to the loop itself,
> > since
> > it is where it really belongs. Al
t;allwinner,sun4i-a10-usb-phy" },
> > { .compatible = "allwinner,sun5i-a13-usb-phy" },
> > + { .compatible = "allwinner,sun6i-a31-usb-phy" },
>
> Do you have Documentation for this comptible binding? Would be good to mention
> that in the commit log.
Ah righ
On Tue, May 13, 2014 at 05:44:14PM +0200, Maxime Ripard wrote:
> Hi everyone,
>
> This patchset adds support for the USB controllers found in the
> Allwinner A31.
>
> While the design is similar to the earlier Allwinner SoCs that are
> already supported, a few details here a
Hi Greg,
On Wed, May 14, 2014 at 06:05:20PM +0200, Greg Kroah-Hartman wrote:
> On Wed, May 14, 2014 at 02:34:19PM +0200, Maxime Ripard wrote:
> > On Tue, May 13, 2014 at 05:44:14PM +0200, Maxime Ripard wrote:
> > > Hi everyone,
> > >
> > > This patchset adds s
Hi Greg,
On Wed, May 14, 2014 at 06:05:20PM +0200, Greg Kroah-Hartman wrote:
> On Wed, May 14, 2014 at 02:34:19PM +0200, Maxime Ripard wrote:
> > On Tue, May 13, 2014 at 05:44:14PM +0200, Maxime Ripard wrote:
> > > Hi everyone,
> > >
> > > This patchset adds s
On Sat, May 24, 2014 at 07:19:40AM +0900, Greg Kroah-Hartman wrote:
> On Fri, May 23, 2014 at 08:33:39PM +0200, Maxime Ripard wrote:
> > Hi Greg,
> >
> > On Wed, May 14, 2014 at 06:05:20PM +0200, Greg Kroah-Hartman wrote:
> > > On Wed, May 14, 2014 at 02:34:1
On Tue, May 27, 2014 at 03:53:18PM -0700, Greg Kroah-Hartman wrote:
> On Thu, May 15, 2014 at 11:14:38AM +0200, Maxime Ripard wrote:
> > Hi Greg,
> >
> > On Wed, May 14, 2014 at 06:05:20PM +0200, Greg Kroah-Hartman wrote:
> > > On Wed, May 14, 2014 at 02:34:1
haven't really followed the rest of the discussion, so sorry if you
already talked about that, but why can't you just set the dr_mode to
peripheral in such a case?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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On Thu, Sep 10, 2015 at 08:38:38PM +0200, Hans de Goede wrote:
> Hi,
>
> On 10-09-15 20:30, Maxime Ripard wrote:
> >On Thu, Sep 10, 2015 at 08:23:23PM +0200, Hans de Goede wrote:
> >>Hi,
> >>
> >>On 04-09-15 08:43, Olliver Schinagl wrote:
> >&
preparation patches can be merged already
> (assuming there are no objections).
>
> And then once the SRAM controller patches are in next we can also merge
> the "musb: Add support for the Allwinner sunxi musb" commit and the dts
> changes.
All the DT bits look fine to me. I
Hi,
On Thu, Feb 05, 2015 at 02:21:42PM +0100, Maxime Ripard wrote:
> Hi,
>
> On Thu, Jan 22, 2015 at 08:37:45AM +0100, Yegor Yefremov wrote:
> > I have the same experience with 3.15. The switching is working when
> > CONFIG_USB_MUSB_DUAL_ROLE is set and dr_mode = "o
() for the first hcd much later, and it could
> > maybe init
> > the phy for us?
>
> I thought usb_phy_*() stuff would be deprecated and we should use
> phy framework instead i.e. phy_init() and friends.
Except that all drivers have not been converted yet... So it's not
re
On Tue, Apr 21, 2015 at 01:46:36PM +0300, Roger Quadros wrote:
> On 21/04/15 11:08, Maxime Ripard wrote:
> > On Tue, Apr 21, 2015 at 12:49:54PM +0300, Roger Quadros wrote:
> >> On 20/04/15 15:35, Mathias Nyman wrote:
> >>> Hi
> >>>
> >>> On 02.
+ return -ENODEV;
> + }
The fact that the driver expects both to be set if one is should be in
the binding documentation.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Hi,
On Mon, Jun 01, 2015 at 11:28:23AM +0200, Hans de Goede wrote:
> On 01-06-15 11:22, Maxime Ripard wrote:
> >On Sun, May 31, 2015 at 06:10:25PM +0200, Hans de Goede wrote:
> >>+ /* We either want both gpio pins or neither (when in host mode) */
> >>+ if (
y're fixing some real
issue that we're seeing, and it seems to both work quite well and not
generate a lot of pushback.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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e a lot of pushback.
>
> This patch series has stack on review due to different views
> on checking input parameters of externally visible function.
>
> I see there is no any way to get these patches accepted other
> than skip checking validity of some input parameters as
> w
rol_deassert will deassert the reset, whether
> you count or not.
> But if the two drivers have deasserted an initially asserted reset, a
> reset_control_assert for one of them will silently fail.
Then maybe we can just make it return an error when someone calls
_assert or _reset on a rese
G_ON) if the shared bool is true
I don't think silently failing (at least from the driver point of
view) is the right approach. You've used clocks as an example, but
there's a quite significant difference between clocks and reset lines:
you never really care if the clock is
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