with up to three ports enabled on
the internal roothub. Using only the top-level "phy" properties does not
work here since one can only specify one "usb2-phy" and one "usb3-phy",
while actually at least two "usb2-phy" have to be specified.
Signed-off-by: Ma
A USB root-hub may have several PHYs which need to be configured before
the root-hub starts working.
This adds the documentation for such a USB root-hub as well as a hint
regarding the child-nodes on XHCI controllers which can include the
roothub.
Signed-off-by: Martin Blumenstingl
Acked-by: Rob
Hello Mathias, Hello Greg,
On Sun, Sep 3, 2017 at 11:38 PM, Martin Blumenstingl
wrote:
> This series is the outcome of a discussion with Felipe Balbi,
> see [0] and [1].
> The quick-summary of this is:
> - dwc3 already takes one USB2 and one USB3 PHY and initializes these
> c
Hello Greg, Hello Mathias,
On Mon, Sep 18, 2017 at 10:49 AM, Greg KH wrote:
> On Sun, Sep 17, 2017 at 10:51:31PM +0200, Martin Blumenstingl wrote:
>> Hello Mathias, Hello Greg,
>>
>> On Sun, Sep 3, 2017 at 11:38 PM, Martin Blumenstingl
>> wrote:
>> > This s
Hello Minas,
On Thu, May 10, 2018 at 11:44 AM Martin Blumenstingl
wrote:
>
> Hello Minas,
>
> On Mon, May 7, 2018 at 3:27 PM, Minas Harutyunyan
> wrote:
> > Hi Martin,
> >
> > On 5/7/2018 12:28 AM, Martin Blumenstingl wrote:
> >> Hello,
> >>
Hello Arthur, Hello Minas,
On Wed, Jul 4, 2018 at 1:43 PM Artur Petrosyan
wrote:
>
> Hello Martin,
>
> On 7/4/2018 01:39, Martin Blumenstingl wrote:
> > Hello Minas,
> >
> > On Thu, May 10, 2018 at 11:44 AM Martin Blumenstingl
> > wrote:
> >>
> &g
On Wed, Jul 4, 2018 at 4:16 PM Martin Blumenstingl
wrote:
[...]
> unfortunately it seems that plugging in seems to fill the kmsg buffer
> instantly, so I cannot (at least I don't know how - do you have any
> idea how to get around this?) get the information from the second
> wher
HANG! AHB Idle timeout
> GRSTCTL GRSTCTL_AHBIDLE
> [2.015176] dwc2: probe of 5000.usb failed with error -16
>
> The proposed patch changes the location where dwc2_check_core_endianness
> is called, allowing the clock peripheral to be enabled first.
>
> Signed-off-by: B
/2018/4/19/88
> [1] https://patchwork.kernel.org/patch/10160181/
>
> Signed-off-by: Chunfeng Yun
> Reviewed-by: Johan Hovold
Reviewed-by: Martin Blumenstingl
thanks to both of you for fixing my code!
Regards
Martin
v" as a workaround)
Christian Hewitt made me aware of a similar issue that was fixed for
Rockchip devices. This single patch applies the same fix to the
Amlogic devices as well.
[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-May/007310.html
Martin Blumenstingl (1):
usb: dwc
arameter (which then got renamed to
"power_down" to support other modes) was changed in the v4.17 merge
window with:
commit 6d23ee9caa6790 ("Merge tag 'usb-for-v4.17' of
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-testing").
Cc: # 4.19
Sug
PHY
Bindings. The PHY works for host or peripheral modes. Configuration of
the mode is part of the USBCTRL registers which are outside of the PHY
registers."
> Signed-off-by: Neil Armstrong
with the patch description nit-pick addressed:
Reviewed-by: Martin Blumenstingl
Regards
Martin
On Tue, Feb 12, 2019 at 4:15 PM Neil Armstrong wrote:
>
> Add the Amlogic G12A Family USB3 + PCIE Combo PHY Bindings.
>
> This PHY can provide exclusively USB3 or PCIE support on shared I/Os.
>
> Signed-off-by: Neil Armstrong
one nit-pick below, but apart from that:
R
Hi Neil,
On Tue, Feb 12, 2019 at 4:15 PM Neil Armstrong wrote:
>
> Adds the specific compatible string for the DWC2 IP found in the
> Amlogic G12A SoC Family.
>
> Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
> ---
> Documentation/devicetree/bindings/us
L_USB3) += phy-meson-gxl-usb3.o
> diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> new file mode 100644
> index ..3b6271a8be02
> --- /dev/null
> +++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> @@
Hi Neil,
On Tue, Feb 12, 2019 at 4:16 PM Neil Armstrong wrote:
>
> This adds support for the shared USB3 + PCIE PHY found in the
> Amlogic G12A SoC Family.
>
> It supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of
> the board.
>
> Selection is done by the #phy-cells, making the
Hi Neil,
On Tue, Feb 12, 2019 at 4:15 PM Neil Armstrong wrote:
[...]
> +
> +Example device nodes:
> + usb: usb@ffe09000 {
> + compatible = "amlogic,meson-g12a-usb-ctrl";
> + reg = <0x0 0xffe09000 0x0 0xa0>;
> + interrupts = ;
Hi Neil,
thank you for working on this!
I have few questions and comments below, but overall it looks good :)
On Tue, Feb 12, 2019 at 4:17 PM Neil Armstrong wrote:
>
> Adds support for Amlogic G12A USB Control Glue HW.
>
> The Amlogic G12A SoC Family embeds 2 USB Controllers :
> - a DWC3 IP conf
Hi Neil,
> > +static int dwc3_meson_g12a_debugfs_init(struct dwc3_meson_g12a *priv)
> > +{
> > + priv->root = debugfs_create_dir("dwc3-meson-g12a", NULL);
> > + if (IS_ERR(priv->root))
> > + return PTR_ERR(priv->root);
> > +
> > + debugfs_create_file("mode_force", 0
Hi Neil,
On Mon, Mar 4, 2019 at 11:38 AM Neil Armstrong wrote:
>
> Add the Amlogic G12A Family USB3 + PCIE Combo PHY Bindings.
>
> This PHY can provide exclusively USB3 or PCIE support on shared I/Os.
>
> Signed-off-by: Neil Armstrong
> Reviewed-by: Martin Blumenstingl
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