Hi Juan,
On Tue, Nov 21, 2017 at 12:24:01PM +0100, Juan Zea wrote:
> Please excuse me... I have reported two different problems in this post,
> and I think things are mixing up a bit. My bad. I've found two different
> problems:
>
> 1.- When compiling vhci driver with multiple hubs (in latest
Hi Shuah,
On Tue, Nov 21, 2017 at 07:33:41AM -0700, Shuah Khan wrote:
>
> Thanks for finding the problem. usb2 devices don't work at all with the
> offending commit: 03cd00d538a6feb0492cd153edf256ef7d7bd95e
>
> I have been debugging on 4.12 and this bad commit. Low speed devices can be
> attache
On 11/21/2017 3:06 PM, Rob Herring wrote:
[..]
>> I like where you are going with this. Are you saying that I could read for a
>> device property read from firmware (for DTB or ACPI) like DWC3 does for
>> "snps,hird-threshold"?
>
> Is that for the same thing? If so, drop the vendor prefix and us
On Tue, Nov 21, 2017 at 1:49 PM, Adam Wallis wrote:
> On 11/21/2017 2:11 PM, Rob Herring wrote:
>> On Tue, Nov 21, 2017 at 12:18:09PM -0500, Adam Wallis wrote:
>>> Certain systems may run with CPUs at a very slow frequency. This
>>> patch adds a quirk bit that can be used to relax certain timings,
On 11/21/2017 2:11 PM, Rob Herring wrote:
> On Tue, Nov 21, 2017 at 12:18:09PM -0500, Adam Wallis wrote:
>> Certain systems may run with CPUs at a very slow frequency. This
>> patch adds a quirk bit that can be used to relax certain timings, etc.
>>
>> This quirk might be needed for other fields in
On Tue, Nov 21, 2017 at 12:18:09PM -0500, Adam Wallis wrote:
> Certain systems may run with CPUs at a very slow frequency. This
> patch adds a quirk bit that can be used to relax certain timings, etc.
>
> This quirk might be needed for other fields in the future, but
> initially, it will be used o
On Tue, Nov 21, 2017 at 02:12:12PM +, Adam Thomson wrote:
> The expectation in the FUSB302 driver is that a TX_SUCCESS event
> should occur after a message has been sent, but before a GCRCSENT
> event is raised to indicate successful receipt of a message from
> the partner. However in some circ
On systems that allow CPUs to run at an extremely reduced frequency,
it is possible to create an "interrupt" storm by USB settings that are not
ideal at these speeds. This patch series introduces a quirk bit that currently
only touches the Interrupt Control register but might be used in the future
Certain systems may run with CPUs at a very slow frequency. This
patch adds a quirk bit that can be used to relax certain timings, etc.
This quirk might be needed for other fields in the future, but
initially, it will be used only on the IRQ control register to allow
firmare to control the value o
Check sysdev to see if the relaxed timing quirk ("quirk-relaxed-timing")
is set.
Signed-off-by: Adam Wallis
---
drivers/usb/host/xhci-plat.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 09f164f..ea221f3 100644
--- a/driv
> -Original Message-
> From: Vignesh R [mailto:vigne...@ti.com]
> Sent: Tuesday, November 21, 2017 12:48 AM
> To: Roger Quadros
> Cc: Chris Welch ; linux-usb@vger.kernel.org;
> linux-...@vger.kernel.org; Joao Pinto ; KISHON VIJAY
> ABRAHAM
> Subject: Re: xhci_hcd HC died; cleaning up wi
On 11/21/2017 04:24 AM, Juan Zea wrote:
>> - Mensaje original -
>> De: "Yuyang Du"
>> Para: "Shuah Khan"
>> CC: "Juan Zea" , sh...@kernel.org, "Bjørn Mork"
>> , linux-usb@vger.kernel.org, "Valentina Manea"
>>
>> Enviados: Martes, 21 de Noviembre 2017 8:45:33
>> Asunto: Re: usbip port n
On 21 November 2017 14:18, Heikki Krogerus wrote:
> On Tue, Nov 21, 2017 at 01:51:41PM +, Adam Thomson wrote:
> > > These don't apply on top of Badhri's series:
> > > http://www.spinics.net/lists/kernel/msg2649921.html
> >
> > Hi Heikki,
> >
> > When I submitted these I was aware of Badhri's p
On Tue, Nov 21, 2017 at 01:51:41PM +, Adam Thomson wrote:
> > These don't apply on top of Badhri's series:
> > http://www.spinics.net/lists/kernel/msg2649921.html
>
> Hi Heikki,
>
> When I submitted these I was aware of Badhri's patch set but at the time they
> hadn't been approved or pulled,
The expectation in the FUSB302 driver is that a TX_SUCCESS event
should occur after a message has been sent, but before a GCRCSENT
event is raised to indicate successful receipt of a message from
the partner. However in some circumstances it is possible to see
the hardware raise a GCRCSENT event be
On 21 November 2017 14:08, Adam Thomson wrote:
> Subject: [PATCH] typec: tcpm: fusb302: Resolve out of order messaging events
Sorry. Finger trouble. Will resend with correct 'v3' title
> The expectation in the FUSB302 driver is that a TX_SUCCESS event
> should occur after a message has been sent
The expectation in the FUSB302 driver is that a TX_SUCCESS event
should occur after a message has been sent, but before a GCRCSENT
event is raised to indicate successful receipt of a message from
the partner. However in some circumstances it is possible to see
the hardware raise a GCRCSENT event be
On 21 November 2017 13:36, Heikki Krogerus write:
> Hi Adam,
>
> On Tue, Nov 14, 2017 at 11:44:41AM +, Adam Thomson wrote:
> > This patch set adds sink side support for the PPS feature introduced in the
> > USB PD 3.0 specification.
> >
> > The source PPS supply is represented using the Power
Hi Adam,
On Tue, Nov 14, 2017 at 11:44:41AM +, Adam Thomson wrote:
> This patch set adds sink side support for the PPS feature introduced in the
> USB PD 3.0 specification.
>
> The source PPS supply is represented using the Power Supply framework to
> provide
> access and control APIs for de
On 11/20/2017 4:48 PM, Stefan Wahren wrote:
> Hi Minas,
>
> Am 20.11.2017 um 12:59 schrieb Minas Harutyunyan:
>> Hi Stefan,
>> Looks like I know cause of issue... but I'm overloaded today and will able
>> to check it tomorrow. Sorry for delay.
>
> thanks for your reply. There is no need to hurry
> - Mensaje original -
> De: "Yuyang Du"
> Para: "Shuah Khan"
> CC: "Juan Zea" , sh...@kernel.org, "Bjørn Mork"
> , linux-usb@vger.kernel.org, "Valentina Manea"
>
> Enviados: Martes, 21 de Noviembre 2017 8:45:33
> Asunto: Re: usbip port number limits
>
> On Wed, Nov 15, 2017 at 07:58:
From: Sebastian Sjoholm
Date: Mon, 20 Nov 2017 19:05:17 +0100
> Quectel BG96 is an Qualcomm MDM9206 based IoT modem, supporting both
> CAT-M and NB-IoT. Tested hardware is BG96 mounted on Quectel development
> board (EVB). The USB id is added to qmi_wwan.c to allow QMI
> communication with the
From: Vivek Gautam
Pipe clock comes out of the phy and is available as long as
the phy is turned on. Clock controller fails to gate this
clock after the phy is turned off and generates a warning.
/ # [ 33.048561] gcc_usb3_phy_pipe_clk status stuck at 'on'
[ 33.048585] [ cut here
From: Vivek Gautam
Move from using array of clocks to clk_bulk_* APIs that
are available now.
Signed-off-by: Vivek Gautam
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 50 -
1 file changed, 16 insertions(+), 34 deletions(-)
diff --gi
PHY block or asynchronous reset requires signal
to be asserted before de-asserting. Driver is only
de-asserting signal which is already low, hence
reset operation is a no-op. Fix this by asserting
signal first. Also, resetting requires PHY clocks
to be turned ON only after reset is finished. Fix
th
PHY must be powered on before turning ON clocks and
attempting to initialize it. Driver is exposing
separate init and power_on routines for this.
Apparently USB dwc3 core driver performs power-on after
init. Also, poweron and init for QMP PHY need to be
executed together always, hence remove powero
PHY must be powered on before turning ON clocks and
attempting to initialize it. Driver is exposing
separate init and power_on routines for this.
Apparently USB dwc3 core driver performs power-on
after init. Also, poweron and init for QUSB2 PHY
need to be executed together always, hence remove
powe
Driver is currently performing PHY reset after starting
SERDES/PCS. As per hardware datasheet reset must be done
before starting PHY. Hence, update the sequence.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff -
New version of QUSB2 PHY has some registers offset changed.
Add support to have register layout for a target and update
the same in phy_configuration.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 131 --
1 file changed, 95 insertions(+),
Update generic compatible string for QUSB2 V2 PHY. This will allow
all targets using QUSB2 V2 use same string.
Acked-by: Rob Herring
Signed-off-by: Manu Gautam
---
Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Do
New revision (v3) of QMP PHY uses different offsets
for almost all of the registers. Hence, move these
definitions to header file so that updated offsets
can be added for QMP v3.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 119 +--
drivers/phy
Registers offsets for QMP V3 PHY are changed from
previous versions (1/2), update same in header file.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.h | 149
1 file changed, 149 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.
Update compatible string and clock names for QMP version V3
USB PHY.
Acked-by: Rob Herring
Signed-off-by: Manu Gautam
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom-qm
QCOM USB PHYs can monitor resume/remote-wakeup event in
suspended state. However PHY driver must know current
operational speed of PHY in order to set correct polarity of
wakeup events for detection. E.g. QUSB2 PHY monitors DP/DM
signals depending on speed is LS or FS/HS to detect resume.
Similarly
QMP V3 USB3 PHY is a DisplayPort (DP) and USB combo PHY
with dual RX/TX lanes to support type-c. There is a
separate block DP_COM for configuration related to type-c
or DP. Add support for dp_com region and secondary rx/tx
lanes initialization.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm
Disable clocks and enable DP/DM wakeup interrupts when
suspending PHY.
Core driver should notify speed to PHY driver to enable
appropriate DP/DM wakeup interrupts polarity in suspend state.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 181 +++
Disable clocks and enable PHY autonomous mode to detect
wakeup events when PHY is suspended.
Core driver should notify speed to PHY driver to enable
LFPS and/or RX_DET interrupts.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 185 +++-
drive
Use register layout to add additional registers present
on QUSB2 PHY V2 version for PHY initialization.
Other than new registers on V2, following two register's
offset and bit definitions are different: POWERDOWN control
and PLL_STATUS.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qco
QUSB-v2 and QMP-v3 USB PHYs are present on Qualcomm's 14nm
and 10nm SOCs.
This patch series adds support for runtime PM for these
USB PHYs and adds fixes in drivers to follow PHY reset and
initialization sequence as per hardware programming manual.
Changes since v2:
- Drop sw-vbus override related
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