On Wed, Apr 27, 2022 at 07:49:01PM -0300, Guilherme G. Piccoli wrote:
> Many other place in the kernel prefer the latter, so let's keep
> it consistent in MIPS code as well. Also, removes a useless header.
>
> Cc: Thomas Bogendoerfer
> Signed-off-by: Guilherme G. Piccoli
&g
account that the changing bits
> are in a different bit position depending on the CPU model. In addition,
> we previously were falling back to 0 for ancient CPUs that Linux does
> not support anyway; remove that dead path entirely.
>
> Cc: Thomas Gleixner
> Cc: Arnd Bergmann
> Cc:
On Fri, Apr 15, 2022 at 01:26:48PM +0100, Maciej W. Rozycki wrote:
> Hi Jason,
>
> > > It depends on the exact system. Some have a 32-bit high-resolution
> > > counter in the chipset (arch/mips/kernel/csrc-ioasic.c) giving like 25MHz
> > > resolution, some have nothing but jiffies.
> >
> > Al
better than returning zero all the time.
>
> Cc: Thomas Gleixner
> Cc: Arnd Bergmann
> Cc: Thomas Bogendoerfer
> Signed-off-by: Jason A. Donenfeld
> ---
> arch/mips/include/asm/timex.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/mips/inc