Hi Cyrille,
Thanks for the feedback. See my comments in line below.
Matthew Gerlach
On Tue, 10 Oct 2017, Cyrille Pitchen wrote:
Hi Matthew
NAK for this patch
Le 20/09/2017 à 20:28, matthew.gerl...@linux.intel.com a écrit :
From: Matthew Gerlach
This patch is a work around for some
From: Matthew Gerlach
This patch set adds a spi-nor flash driver for the Altera ASMI Parallel II
IP Core. This driver was created based on feedback from Marek Vasut,
Cyrill Pitchen, and Michal Suchanek regarding Version 2 of the Altera
Quadspi Controller: https://lkml.org/lkml/2017/6/26/518
From: Matthew Gerlach
Device Tree bindings for Altera ASMI Parallel II IP Core
connected to a flash chip.
Signed-off-by: Matthew Gerlach
Acked-by: Rob Herring
---
v2:
Made substitutions suggested by Rob Herring.
Emphasize driver expects controller is connected to spi-nor flash.
v3
From: Matthew Gerlach
This patch adds support for a spi-nor, platform driver for the
Altera ASMI Parallel II IP Core. The intended use case is to be able
to update the flash used to load a FPGA at power up with mtd-utils.
Signed-off-by: Matthew Gerlach
---
v2:
minor checkpatch fixing by
On Thu, 25 Jan 2018, Alan Tull wrote:
Hi Alan,
I seem to remember issue coming up a couple of times.
I think this comment will be very helpful.
Matthew Gerlach
Add a comment to the header of fpga_region_program_fpga()
regarding locking of the bridges.
Signed-off-by: Alan Tull
---
drivers
consider new hardware implementations as well.
Full disclosure, I am particularly interested in porting to a new hw
implementation for partial reconfiguration.
Please see some comments below.
Matthew Gerlach
On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
Hi Hao,
We are going to want to be able use
On Mon, 12 Mar 2018, Wu Hao wrote:
Hi Hao,
Please see my two comments inline.
Thanks,
Matthew Gerlach
On Sun, Mar 11, 2018 at 01:09:31PM -0700, matthew.gerl...@linux.intel.com wrote:
On Mon, 5 Mar 2018, Alan Tull wrote:
Hi Hao,
I do think we should consider different hw
On Wed, 24 Oct 2018, Moritz Fischer wrote:
Hi Anatolij, Andreas,
On Tue, Oct 23, 2018 at 06:46:47PM +, Andreas Puhm wrote:
Hi Anatolij,
The CvP docs says that on some FPGAs (e.g. Arria 10) the assertion of CVP
status can take up to 500ms. However it is not clear whether this delay
mig
From: Matthew Gerlach
Gracefully ignore misconfigured port entries encountered in
incorrect FPGA images.
Signed-off-by: Matthew Gerlach
---
drivers/fpga/dfl-pci.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl
On Tue, 20 Apr 2021, Tom Rix wrote:
On 4/20/21 10:27 AM, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
Gracefully ignore misconfigured port entries encountered in
incorrect FPGA images.
Signed-off-by: Matthew Gerlach
---
drivers/fpga/dfl-pci.c | 16 +++-
1
ing
I also confirmed with HW engineers. The original specification was
not precise. The code should have been doing this all along.
Matthew Gerlach
hasn't been an issue for the current PAC products, as proven by our testing.
However, with OFS we cannot anticipate what the timing will be
Reviewed-by: Matthew Gerlach
On Thu, 4 Feb 2021, Russ Weight wrote:
Port enable is not complete until ACK = 0. Change
__afu_port_enable() to guarantee that the enable process
is complete by polling for ACK == 0.
Reviewed-by: Tom Rix
Signed-off-by: Russ Weight
---
v4:
- Added a dev_warn
quote ends without a blank line; unexpected unindent.
Rectify ReST formatting in ./Documentation/fpga/dfl.rst.
Signed-off-by: Lukas Bulwahn
Acked-by: Moritz Fischer
Acked-by: Matthew Gerlach
---
applies cleanly on next-20210111
Moritz, Matthew, please ack.
Greg, please pick this doc fixup to
From: Matthew Gerlach
This patch set adds Device Feature List (DFL) bus support for
the Altera SPI Master controller.
Patch 1 separates spi-altera.c into spi-altera-core.c and
spi-altera-platform.c.
Patch 2 adds spi-altera-dfl.c.
Matthew Gerlach (2):
spi: altera: separate core code from
From: Matthew Gerlach
In preparation of adding support for a new bus type,
separate the core spi-altera code from the platform
driver code.
Signed-off-by: Matthew Gerlach
---
drivers/spi/Kconfig | 9 +-
drivers/spi/Makefile | 3 +-
drivers/spi/spi-altera-core.c
From: Matthew Gerlach
This patch adds a Device Feature List (DFL) bus driver for the
Altera SPI Master controller. The SPI master is connected to an
Intel SPI Slave to Avalon Bridge inside an Intel MAX10
BMC Chip.
Signed-off-by: Matthew Gerlach
---
v3: Instantiate SPI device instead of
On Fri, 9 Apr 2021, Wu, Hao wrote:
On Fri, Apr 09, 2021 at 12:02:47PM +0800, Wu, Hao wrote:
+
+static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
+{
+struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
+
+platform_device_unregister(aspi->altr_spi);
+}
+
+#define FME_FEAT
From: Matthew Gerlach
Like the Intel N3000 card, the Intel D5005 has a MAX10 based
BMC. This commit adds support for the D5005 sensors that are
monitored by the MAX10 BMC.
Signed-off-by: Matthew Gerlach
Signed-off-by: Russ Weight
Acked-by: Lee Jones
---
v2: change variable name from
From: Matthew Gerlach
This patch set adds support for the Board Management Controller (BMC)
of an Intel D5005 card. The BMC support requires a Device Feature
List (DFL) bus driver for the Altera SPI Master controller and hwmon
support for the sensors monitored by the BMC.
Patch 1 adds a dfl
From: Matthew Gerlach
This patch adds a Device Feature List (DFL) bus driver for the
Altera SPI Master controller. The SPI master is connected to an
Intel SPI Slave to Avalon Master Bridge inside an Intel MAX10
BMC Chip.
Signed-off-by: Matthew Gerlach
---
v2: moved drivers/fpga/dfl-spi
On Wed, 14 Apr 2021, Mark Brown wrote:
On Tue, Apr 13, 2021 at 03:58:34PM -0700, matthew.gerl...@linux.intel.com wrote:
+++ b/drivers/spi/spi-altera-dfl.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DFL bus driver for Altera SPI Master
+ *
Please make the entire comment
: Matthew Gerlach
---
drivers/fpga/dfl-pci.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
index 04e47e2..b44523e 100644
--- a/drivers/fpga/dfl-pci.c
+++ b/drivers/fpga/dfl-pci.c
@@ -69,14 +69,16 @@ static void
Hi Moritz,
On Mon, 5 Apr 2021, Moritz Fischer wrote:
Hi Matthew,
On Mon, Apr 05, 2021 at 04:53:00PM -0700, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
This patch adds DFL bus driver for the Altera SPI Master
controller. The SPI master is connected to an Intel SPI Slave
Hi Yilun,
On Tue, 6 Apr 2021, Xu Yilun wrote:
On Mon, Apr 05, 2021 at 04:53:01PM -0700, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
Like the Intel N3000 card, the Intel D5005 has a MAX10 based
BMC. This commit adds support for the D5005 sensors that are
monitored by the
From: Russ Weight
This patch adds the approved PCI Express Device IDs for the
PF and VF for the card for D5005 PAC cards.
Signed-off-by: Russ Weight
Signed-off-by: Matthew Gerlach
---
drivers/fpga/dfl-pci.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git
From: Matthew Gerlach
This patch set adds basic support for the Intel D5005 card to the
dfl driver framework.
Patch 1 adds the PCIe device id of the D5005 to the dfl-pci id table.
Patch 2 adds a dfl driver for the Altera SPI Master which is connected
to the board's BMC.
Patch 3 adds
From: Matthew Gerlach
This patch adds DFL bus driver for the Altera SPI Master
controller. The SPI master is connected to an Intel SPI Slave to
Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
Signed-off-by: Matthew Gerlach
---
drivers/fpga/Kconfig | 9 ++
drivers/fpga
From: Matthew Gerlach
Like the Intel N3000 card, the Intel D5005 has a MAX10 based
BMC. This commit adds support for the D5005 sensors that are
monitored by the MAX10 BMC.
Signed-off-by: Matthew Gerlach
Signed-off-by: Russ Weight
---
drivers/hwmon/intel-m10-bmc-hwmon.c | 122
On Tue, 17 Nov 2020, Wu, Hao wrote:
Subject: [PATCH 1/2] fpga: dfl: refactor cci_enumerate_feature_devs()
From: Matthew Gerlach
In preparation of looking for dfls based on a vendor
specific pcie capability, move code that assumes
Bar0/offset0 as start of DFL to its own function.
Signed
On Tue, 17 Nov 2020, Xu Yilun wrote:
On Mon, Nov 16, 2020 at 05:25:52PM -0800, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
specific capability can be used to specify the start of a
number of DFLs.
Signed-off-by
On Tue, 17 Nov 2020, Wu, Hao wrote:
Subject: [PATCH 2/2] fpga: dfl: look for vendor specific capability
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
specific capability can be used to specify the start of a
number of DFLs.
Signed-off-by: Matthew Gerlach
On Tue, 17 Nov 2020, Tom Rix wrote:
On 11/16/20 5:25 PM, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
specific capability can be used to specify the start of a
number of DFLs.
Signed-off-by: Matthew Gerlach
On Wed, 18 Nov 2020, Wu, Hao wrote:
On Tue, 17 Nov 2020, Wu, Hao wrote:
[...]
Open discussion
===
diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
index b1b157b41942..5418e8bf2496 100644
--- a/drivers/fpga/dfl-pci.c
+++ b/drivers/fpga/dfl-pci.c
@@ -27,6 +27,13 @@
From: Matthew Gerlach
The start of a Device Feature List (DFL) is currently assumed to be at
Bar0/Offset 0 on the PCIe bus by drivers/fpga/dfl-pci.c. This patchset
adds support for the start one or more DFLs to be specified in a
Vendor-Specific Capability (VSEC) structure in PCIe config space
From: Matthew Gerlach
In preparation of looking for dfls based on a vendor
specific pcie capability, move code that assumes
Bar0/offset0 as start of DFL to its own function.
Signed-off-by: Matthew Gerlach
---
v2: remove spurious blank lines
rename find_dfl_in_bar0 to find_dfls_by_default
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
specific capability can be used to specify the start of a
number of DFLs.
Signed-off-by: Matthew Gerlach
---
v2: Update documentation for clarity.
Clean up macro names.
Use GENMASK.
Removed spurious
On Sat, 28 Nov 2020, Wu, Hao wrote:
Subject: [PATCH v3 1/2] fpga: dfl: refactor cci_enumerate_feature_devs()
From: Matthew Gerlach
In preparation of looking for dfls based on a vendor
specific pcie capability, move code that assumes
Bar0/offset0 as start of DFL to its own function.
as
On Sat, 28 Nov 2020, Wu, Hao wrote:
Subject: [PATCH v3 2/2] fpga: dfl: look for vendor specific capability
Maybe we can change the title a little bit, what about
fpga: dfl-pci: locate DFLs by PCIe vendor specific capability
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR
On Sat, 21 Nov 2020, Moritz Fischer wrote:
Hi Matthew,
On Wed, Nov 18, 2020 at 11:01:51AM -0800, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
specific capability can be used to specify the start of a
number of DFLs
From: Matthew Gerlach
The start of a Device Feature List (DFL) is currently assumed to be at
Bar0/Offset 0 on the PCIe bus by drivers/fpga/dfl-pci.c. This patchset
adds support for the start one or more DFLs to be specified in a
Vendor-Specific Capability (VSEC) structure in PCIe config space
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
specific capability can be used to specify the start of a
number of DFLs.
Signed-off-by: Matthew Gerlach
---
v3: Add text and ascii art to documentation.
Ensure not to exceed PCIe config space in loop.
v2
From: Matthew Gerlach
In preparation of looking for dfls based on a vendor
specific pcie capability, move code that assumes
Bar0/offset0 as start of DFL to its own function.
Signed-off-by: Matthew Gerlach
---
v3: no change
v2: remove spurious blank lines
rename find_dfl_in_bar0 to
vendor specific capability
Maybe we can change the title a little bit, what about
fpga: dfl-pci: locate DFLs by PCIe vendor specific capability
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
specific capability can be used to specify the start of a
number of DFLs
On Wed, 2 Dec 2020, Wu, Hao wrote:
+ }
+
+ offset = dfl_res & PCI_VNDR_DFLS_RES_OFF_MASK;
+ if (offset >= len) {
+ dev_err(&pcidev->dev, "%s bad
offset %u >= %pa\n",
+ __func__, offset, &len);
+
From: Matthew Gerlach
The start of a Device Feature List (DFL) is currently assumed to be at
Bar0/Offset 0 on the PCIe bus by drivers/fpga/dfl-pci.c. This patchset
adds support for the start one or more DFLs to be specified in a
Vendor-Specific Capability (VSEC) structure in PCIe config space
From: Matthew Gerlach
A PCIe vendor specific extended capability is introduced by Intel to
specify the start of a number of DFLs.
Signed-off-by: Matthew Gerlach
---
v4: Clarify PCI vs. PCIe in documentation
Various cleanup suggested by hao...@intel.com
Document and enforce specifying a
From: Matthew Gerlach
In preparation of looking for dfls based on a vendor specific pci
capability, move the code for the default method of finding the first
dfl at offset 0 of Bar 0 to its own function.
Signed-off-by: Matthew Gerlach
Acked-by: Wu Hao
---
v4: add comment
squash local
On Wed, 20 Jan 2021, Pan Bian wrote:
Release master that have been previously allocated if the number of
chipselect is invalid.
Fixes: 8e04187c1bc7 ("spi: altera: add SPI core parameters support via platform
data.")
Signed-off-by: Pan Bian
Acked-by: Matthew Gerlach
---
drive
Hi Yilun,
You raise some very interesting questions. Please see
my comments below.
Matthew
On Tue, 28 Apr 2020, Xu Yilun wrote:
Hi,
I wonder if an updating of FPGA Flash (but cannot reload) could be
implemented as fpga-mgr?
I have the pcie based FPGA card. The bitstream for FPGA static regi
From: Matthew Gerlach
This set of patches implements a fpga-mgr driver for the Altera Partial
Reconfiguration IP. The driver depends on a patch from Alan Tull that
adds a config complete timeout. The driver code itself is divided into
core functions and functions to implement a platform driver
From: Alan Tull
Adding timeout for maximum allowed time for FPGA to go to
operating mode after a FPGA region has been programmed.
Signed-off-by: Alan Tull
---
drivers/fpga/fpga-region.c| 3 +++
include/linux/fpga/fpga-mgr.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/fp
From: Matthew Gerlach
Device Tree bindings for Altera Partial Reconfiguration IP.
Signed-off-by: Matthew Gerlach
Acked-by: Rob Herring
---
v5:
fix comment as suggested by Rob Herring
added Acked-by: Rob Herring
v4: v3 patch set mistakenly sent out labeled as v4
v3: s/altr,pr-ip/altr
From: Matthew Gerlach
This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.
Signed-off-by: Matthew Gerlach
---
v6:
add MODULE_LICENSE/DESCRIPTION/AUTHOR as suggested by Anatolij Gustschin
v5: fix comment as suggested by Rob
From: Matthew Gerlach
Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component. It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.
Signed-off-by: Matthew Gerlach
---
v6:
Suggestions
On Tue, 21 Mar 2017, Anatolij Gustschin wrote:
Hi Matthew,
Hi Anatolij,
On Fri, 10 Mar 2017 11:40:25 -0800
matthew.gerl...@linux.intel.com matthew.gerl...@linux.intel.com wrote:
...
+int alt_pr_unregister(struct device *dev)
+{
+ dev_dbg(dev, "%s\n", __func__);
+
+ fpga_mgr_u
On Sat, 18 Mar 2017, Anatolij Gustschin wrote:
Hi Matthew,
Hi Anatolij,
Thanks for all the feedback. I will create another patch set
incorporating your suggestions.
On Fri, 10 Mar 2017 11:40:27 -0800
matthew.gerl...@linux.intel.com matthew.gerl...@linux.intel.com wrote:
...
+#inclu
On Sat, 18 Mar 2017, Anatolij Gustschin wrote:
Hi Matthew,
Hi Anatolij,
More good feedback. See below.
thanks for the patches. Please see some comments below.
On Fri, 10 Mar 2017 11:40:25 -0800
matthew.gerl...@linux.intel.com matthew.gerl...@linux.intel.com wrote:
...
+ if (!(
On Thu, 9 Mar 2017, yi1...@linux.intel.com wrote:
From: Yi Li
Hi Yi,
This functionality is extremely helpful. I am working with a
firmware image of about 90 MBs, and even using scatter-gather instead of a
continguous piece of memory is a lot of memory.
Matthew Gerlach
As the FPGA
On Thu, 9 Mar 2017, yi1...@linux.intel.com wrote:
From: Yi Li
Hi Yi,
Just one question below.
Matthew Gerlach
Add function to load firmware in multiple chucks instead of
loading the whole big firmware file at once.
Signed-off-by: Yi Li
---
drivers/base/firmware_class.c | 128
From: Matthew Gerlach
Device Tree bindings for Altera Partial Reconfiguration IP.
Signed-off-by: Matthew Gerlach
Acked-by: Rob Herring
---
v5:
fix comment as suggested by Rob Herring
added Acked-by: Rob Herring
v4: v3 patch set mistakenly sent out labeled as v4
v3: s/altr,pr-ip/altr
From: Matthew Gerlach
This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.
Signed-off-by: Matthew Gerlach
---
v5: fix comment as suggested by Rob Herring
v4: v3 patch set mistakenly sent out labeled as v4
v3:
s/altr,pr-ip/altr
From: Alan Tull
Adding timeout for maximum allowed time for FPGA to go to
operating mode after a FPGA region has been programmed.
Signed-off-by: Alan Tull
---
drivers/fpga/fpga-region.c| 3 +++
include/linux/fpga/fpga-mgr.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/fp
From: Matthew Gerlach
This set of patches implements a fpga-mgr driver for the Altera Partial
Reconfiguration IP. The driver depends on a patch from Alan Tull that
adds a config complete timeout. The driver code itself is divided into
core functions and functions to implement a platform driver
From: Matthew Gerlach
Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component. It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.
Signed-off-by: Matthew Gerlach
---
v5:
Fix comment
On Fri, 10 Mar 2017, Li, Yi wrote:
Hi Matthew
Hi Yi,
On 3/10/2017 11:44 AM, matthew.gerl...@linux.intel.com wrote:
On Thu, 9 Mar 2017, yi1...@linux.intel.com wrote:
From: Yi Li
Hi Yi,
Just one question below.
Matthew Gerlach
Add function to load firmware in multiple chucks
wrote:
From: Yi Li
Hi Yi,
Just one question below.
Matthew Gerlach
Add function to load firmware in multiple chucks instead of
loading the whole big firmware file at once.
Signed-off-by: Yi Li
---
drivers/base/firmware_class.c | 128
++
include
On Mon, 27 Feb 2017, Moritz Fischer wrote:
Hi Matthew,
small nit inline.
On Mon, Feb 27, 2017 at 12:03 PM, wrote:
From: Matthew Gerlach
This patch separates the core Freeze Bridge
driver code from the platform driver code.
The intent is to allow the core driver code
to be used without
From: Matthew Gerlach
Device Tree bindings for Altera Partial Reconfiguration IP.
v3: s/altr,pr-ip/altr,a10-pr-ip/
v2: s/Reconfiguraion/Reconfiguration/
Signed-off-by: Matthew Gerlach
---
Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12
1 file
From: Alan Tull
Adding timeout for maximum allowed time for FPGA to go to
operating mode after a FPGA region has been programmed.
Signed-off-by: Alan Tull
---
drivers/fpga/fpga-region.c| 3 +++
include/linux/fpga/fpga-mgr.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/fp
From: Matthew Gerlach
Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component. It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.
v3:
s/alt_pr_probe/alt_pr_register/
s
From: Matthew Gerlach
This set of patches implements a fpga-mgr driver for the Altera Partial
Reconfiguration IP. The driver depends on a patch from Alan Tull that
adds a config complete timeout. The driver code itself is divided into
core functions and functions to implement a platform driver
From: Matthew Gerlach
This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.
v3:
s/altr,pr-ip/altr,a10-pr-ip/
s/alt_pr_probe/alt_pr_register/
s/alt_pr_remove/alt_pr_unregister/
fix error found by kbuild robot with more
e can parse a
device tree blob. I also think someone mentioned the FIT format which is
closely related to device tree format.
Matthew Gerlach
[raw bitfile follows, start byte in the file is aligned for DMA]
I can publish a version of my python script which produces these files
from typical
From: Matthew Gerlach
This set of patches implements a fpga-mgr driver for the Altera Partial
Reconfiguration IP. The driver depends on a patch from Alan Tull that
adds a config complete timeout. The driver code itself is divided into
core functions and functions to implement a platform
From: Matthew Gerlach
Device Tree bindings for Altera Partial Reconfiguraion IP?
Signed-off-by: Matthew Gerlach
---
Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12
1 file changed, 12 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr
From: Matthew Gerlach
This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.
Signed-off-by: Matthew Gerlach
---
drivers/fpga/Kconfig | 7
drivers/fpga/Makefile | 1 +
drivers/fpga/altera-pr-ip
From: Matthew Gerlach
Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component. It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.
Signed-off-by: Matthew Gerlach
---
drivers/fpga/Kconfig
From: Alan Tull
Adding timeout for maximum allowed time for FPGA to go to
operating mode after a FPGA region has been programmed.
Signed-off-by: Alan Tull
---
drivers/fpga/fpga-region.c| 3 +++
include/linux/fpga/fpga-mgr.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/fp
Hi Alan,
On Wed, 15 Feb 2017, Alan Tull wrote:
Currently fpga-mgr.c has three methods for loading FPGA's depending on how
the FPGA image is presented: in a sg table, as a single buffer, or as a
firmware file. This commit adds these parameters to the fpga_image_info
stuct and adds a single fun
Hi Alan,
On Wed, 15 Feb 2017, Alan Tull wrote:
Currently if a user applies > 1 overlays to a region
and removes them, we get a slow warning from devm_kfree.
because the pointer to the FPGA image info was overwritten.
This commit adds a list to keep track of overlays applied
to each FPGA regi
Hi Moritz,
Thanks for the feedback.
On Thu, 16 Feb 2017, Moritz Fischer wrote:
Hi Matthew,
On Wed, Feb 15, 2017 at 1:10 PM, wrote:
+static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ u32 i;
+
+
From: Matthew Gerlach
Device Tree bindings for Altera Partial Reconfiguration IP.
v2: s/Reconfiguraion/Reconfiguration/
Signed-off-by: Matthew Gerlach
---
Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12
1 file changed, 12 insertions(+)
create
From: Matthew Gerlach
This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.
v2: s/altr,pr-ip-core/altr,pr-ip/
Signed-off-by: Matthew Gerlach
---
drivers/fpga/Kconfig | 7
drivers/fpga
From: Alan Tull
Adding timeout for maximum allowed time for FPGA to go to
operating mode after a FPGA region has been programmed.
Signed-off-by: Alan Tull
---
drivers/fpga/fpga-region.c| 3 +++
include/linux/fpga/fpga-mgr.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/fp
From: Matthew Gerlach
This set of patches implements a fpga-mgr driver for the Altera Partial
Reconfiguration IP. The driver depends on a patch from Alan Tull that
adds a config complete timeout. The driver code itself is divided into
core functions and functions to implement a platform
From: Matthew Gerlach
Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component. It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.
Signed-off-by: Matthew Gerlach
---
drivers/fpga/Kconfig
On Mon, 27 Feb 2017, Rob Herring wrote:
Hi Rob,
On Wed, Feb 15, 2017 at 01:10:37PM -0800, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
Device Tree bindings for Altera Partial Reconfiguraion IP?
Signed-off-by: Matthew Gerlach
---
Documentation/devicetree/bindings/fpga
From: Matthew Gerlach
This patch separates the core Freeze Bridge
driver code from the platform driver code.
The intent is to allow the core driver code
to be used without requiring platform driver support.
Signed-off-by: Matthew Gerlach
---
drivers/fpga/Kconfig | 7
work, which could be related to using a fairly old 3.10 kernel.
Matthew Gerlach
I really need to take another look at how non-dt systems enumerate to
give better feedback on this.
Cheers,
Moritz
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This looks like a a good change to me.
Tested-by: Matthew Gerlach
On Thu, 7 May 2020, Gustavo A. R. Silva wrote:
The current codebase makes use of the zero-length array language
extension to the C90 standard, but the preferred mechanism to declare
variable-length types such as these ones
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
specific capability can be used to specify the start of a
number of DFLs.
Signed-off-by: Matthew Gerlach
---
Documentation/fpga/dfl.rst | 10 +
drivers/fpga/dfl-pci.c | 88
From: Matthew Gerlach
The start of a Device Feature List (DFL) is currently assumed to be at
Bar0/Offset 0 on the PCIe bus by drivers/fpga/dfl-pci.c. This patchset
adds support for the start of one or more DFLs to be specified in a
Vendor-Specific Capability (VSEC) structure in PCIe config
From: Matthew Gerlach
In preparation of looking for dfls based on a vendor
specific pcie capability, move code that assumes
Bar0/offset0 as start of DFL to its own function.
Signed-off-by: Matthew Gerlach
---
drivers/fpga/dfl-pci.c | 86 --
1 file
On Wed, 12 Apr 2017, kbuild test robot wrote:
Hi Tobias,
Hi Tobias,
This is very interesting issue brought up by your patch that turns
on COMPILE_TEST in drivers/fpga/Kconfig. See my comment below.
Matthew Gerlach
[auto build test WARNING on linus/master]
[also build test WARNING on
rface or something else? Do you
use the sof or an rbf file?
Thanks,
Matthew Gerlach
Changes in v3:
- removed V-series from description (since the driver works
also with Arria-10). Also renamed functions, config option
and driver file name. Changed module description in Kconfig
- dr
On Mon, 3 Apr 2017, Alan Tull wrote:
On Thu, Mar 30, 2017 at 7:08 AM, Wu Hao wrote:
From: Kang Luwei
Partial Reconfiguration (PR) is the most important function for FME. It
allows reconfiguration for given Port/Accelerated Function Unit (AFU).
This patch adds support for PR sub feature. I
From: Matthew Gerlach
The value in the version register of the altera freeze bridge
controller changed from the beta value of 2 to the
value of 0xad03 in the official release of the IP.
This patch supports the old and new version numbers
without printing an warning.
Signed-off-by: Matthew
On Wed, 5 Apr 2017, Moritz Fischer wrote:
Hi Matthew,
Hi Moritz,
On Wed, Apr 5, 2017 at 12:05 PM, wrote:
From: Matthew Gerlach
The value in the version register of the altera freeze bridge
controller changed from the beta value of 2 to the
value of 0xad03 in the official
From: Matthew Gerlach
The value in the version register of the altera freeze bridge
controller changed from the beta value of 2 to the
value of 0xad03 in the official release of the IP.
This patch supports the old and new version numbers, and the
driver's probe function will fail if ne
On Thu, 30 Mar 2017, Wu Hao wrote:
Hi Wu Hao,
Great documentation. I'm looking forward to diving into the rest of the
patches. Please see my comments inline.
Matthew Gerlach
Add a document for Intel FPGA driver overview.
Signed-off-by: Enno Luebbers
Signed-off-by: Xiao Guan
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