From: Matthew Gerlach <matthew.gerl...@linux.intel.com> The start of a Device Feature List (DFL) is currently assumed to be at Bar0/Offset 0 on the PCIe bus by drivers/fpga/dfl-pci.c. This patchset adds support for the start of one or more DFLs to be specified in a Vendor-Specific Capability (VSEC) structure in PCIe config space. If no such VSEC structure exists, then the start of the DFL is assumed to be Bar0/Offset 0 for backward compatibility.
Matthew Gerlach (2): fpga: dfl: refactor cci_enumerate_feature_devs() fpga: dfl: look for vendor specific capability Documentation/fpga/dfl.rst | 10 +++ drivers/fpga/dfl-pci.c | 168 +++++++++++++++++++++++++++++-------- 2 files changed, 143 insertions(+), 35 deletions(-) -- 2.25.2
