Hi David,
Could you please help to review this patch set.
This patch set is very importmant for fsl-quadspi driver.
Thanks.
Thursday, June 30, 2016 9:54 AM Yunhui Cui wrote:
> Hi Brian and Han,
> Could you please give me some comments about this patch set v2 ?
>
> Thanks
>
&g
From: Yunhui Cui
Add some lut_tables to support quad mode for flash n25q128
on the board ls1021a-twr and solve flash Spansion and Micron
command conflict.
In switch {}, The value of command SPINOR_OP_RD_EVCR and
SPINOR_OP_SPANSION_RDAR is the same. They have to share
the same seq_id
Hi all,
I will send another patch set to replace this patch set. This patch set need
not be reviewed more, Many thanks!
Thanks
Yunhui
-Original Message-
From: Bean Huo 霍斌斌 (beanhuo) [mailto:bean...@micron.com]
Sent: Monday, March 21, 2016 10:56 AM
To: Yunhui Cui; Yunhui Cui
Cc: linux
This patch set added the basic support for ls1021-twr/ls2080a-qds.
There is a hardware feature that qspi_amba_base is added
internally by SOC design on ls2080a. So as to software, the driver
need support to the feature.
Signed-off-by: Yunhui Cui
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 24 ++--
1 file changed, 22
There are some read modes for flash, such as NORMAL, FAST,
QUAD, DDR QUAD. These modes will use the identical lut table base
So rename SEQID_QUAD_READ to SEQID_READ.
Signed-off-by: Yunhui Cui
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 8
1 file changed, 4
We can get the read/write/erase opcode from the spi nor framework
directly. This patch uses the information stored in the SPI-NOR to
remove the hardcode in the fsl_qspi_init_lut().
Signed-off-by: Yunhui Cui
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 40
From: Yunhui Cui
Add extra info in LUT table to support some special requerments.
Spansion S25FS-S family flash need some special operations.
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 44 +--
include/linux/mtd/spi-nor.h | 4
From: Yunhui Cui
A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data
Affects: QuadSPI
Description: With AHB buffer prefetch enabled, the QuadSPI may return
incorrect data on the AHB
interface. The buffer pre-fetch is enabled if the fetch size as
configured either in the LUT or
From: Yunhui Cui
The qspi driver add generic fast-read mode for different
flash venders. There are some different board flash work on
different mode, such fast-read, quad-mode.
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 21 -
1 file changed, 16
From: Yunhui Cui
There is a hardware feature that qspi_amba_base is added
internally by SOC design on ls2080a. so memmap_phy need not
be added in driver. If memmap_phy is added, the flash A1
addr space is [0, memmap_phy] which far more than flash size.
The AMBA memory will be divided into four
From: Yunhui Cui
With the physical sectors combination, S25FS-S family flash
requires some special operations for read/write functions.
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/spi-nor.c | 59 +++
1 file changed, 59 insertions(+)
diff --git a
7 nor->flash_read = SPI_NOR_DUAL;
1428 }
Thanks
Yunhui
-Original Message-
From: Han Xu [mailto:xhnj...@gmail.com]
Sent: Saturday, February 27, 2016 12:32 AM
To: Yunhui Cui
Cc: Yunhui Cui; dw...@infradead.org; computersforpe...@gmail.com;
han...@freescal
ated by DT, use it */
if (of_property_read_bool(np, "m25p,fast-read"))
nor->flash_read = SPI_NOR_FAST;
Thanks
Yunhui
-Original Message-
From: Han Xu [mailto:xhnj...@gmail.com]
Sent: Thursday, February 18, 2016 2:08 AM
To: Yunhui
On Thu, Apr 24, 2016 at 06:37:01 AM +0800, Han Xu wrote:
>
> From: Yunhui Cui
> Sent: Wednesday, April 13, 2016 9:50 PM
> To: dw...@infradead.org; computersforpe...@gmail.com;
> han...@freescale.com
> Cc: linux-kernel@vger
> -Original Message-
> From: Han Xu
> Sent: Thursday, April 21, 2016 11:48 PM
> To: Yunhui Cui; Yunhui Cui; dw...@infradead.org;
> computersforpe...@gmail.com; han...@freescale.com
> Cc: linux-kernel@vger.kernel.org; linux-...@lists.infradead.org; linux-
> arm-ker..
There are some read modes for flash, such as NORMAL, FAST,
QUAD, DDR QUAD. These modes will use the identical lut table base
So rename SEQID_QUAD_READ to SEQID_READ.
Signed-off-by: Yunhui Cui
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 8
1 file changed, 4
From: Yunhui Cui
The qspi driver add generic fast-read mode for different
flash venders. There are some different board flash work on
different mode, such fast-read, quad-mode.
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 21 -
1 file changed, 16
We can get the read/write/erase opcode from the spi nor framework
directly. This patch uses the information stored in the SPI-NOR to
remove the hardcode in the fsl_qspi_init_lut().
Signed-off-by: Yunhui Cui
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 40
From: Yunhui Cui
Add some lut_tables to support quad mode for flash n25q128
on the board ls1021a-twr and solve flash Spansion and Micron
command conflict.
In switch {}, The value of command SPINOR_OP_RD_EVCR and
SPINOR_OP_SPANSION_RDAR is the same. They have to share
the same seq_id
From: Yunhui Cui
With the physical sectors combination, S25FS-S family flash
requires some special operations for read/write functions.
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/spi-nor.c | 59 +++
1 file changed, 59 insertions(+)
diff --git a
From: Yunhui Cui
A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data
Affects: QuadSPI
Description: With AHB buffer prefetch enabled, the QuadSPI may return
incorrect data on the AHB
interface. The buffer pre-fetch is enabled if the fetch size as
configured either in the LUT or
There is a hardware feature that qspi_amba_base is added
internally by SOC design on ls2080a. So as to software, the driver
need support to the feature.
Signed-off-by: Yunhui Cui
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 24 ++--
1 file changed, 22
From: Yunhui Cui
Add extra info in LUT table to support some special requerments.
Spansion S25FS-S family flash need some special operations.
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 44 +--
include/linux/mtd/spi-nor.h | 4
> -Original Message-
> From: Han Xu
> Sent: Friday, April 22, 2016 12:49 PM
> To: Yunhui Cui; Yunhui Cui; dw...@infradead.org;
> computersforpe...@gmail.com; han...@freescale.com
> Cc: linux-kernel@vger.kernel.org; linux-...@lists.infradead.org; linux-
> arm-ker..
From: Yunhui Cui
There is a hardware feature that qspi_amba_base is added
internally by SOC design on ls2080a. so memmap_phy need not
be added in driver. If memmap_phy is added, the flash A1
addr space is [0, memmap_phy] which far more than flash size.
The AMBA memory will be divided into four
Hi All,
Thanks for your suggestions before.
Could you help me to review this patch set if you are free?
Thanks
Yunhui
-Original Message-
From: Yunhui Cui [mailto:b56...@freescale.com]
Sent: Thursday, March 03, 2016 2:54 PM
To: dw...@infradead.org; computersforpe...@gmail.com; han
-
From: Bean Huo 霍斌斌 (beanhuo) [mailto:bean...@micron.com]
Sent: Thursday, March 03, 2016 9:39 PM
To: Yunhui Cui
Cc: linux-...@lists.infradead.org; dw...@infradead.org;
computersforpe...@gmail.com; han...@freescale.com;
linux-kernel@vger.kernel.org; linux-...@lists.infradead
Hi Shawn,
Many thanks !
Thanks
Yunhui
-Original Message-
From: Shawn Guo [mailto:shawn...@kernel.org]
Sent: Wednesday, April 13, 2016 9:53 AM
To: Yunhui Cui
Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com;
ijc+devicet...@hellion.org.uk; ga...@codeaurora.org; Yao Yuan
On August 06, 2016 10:27 PM, Jagan Teki wrote:
> On 22 April 2016 at 12:09, Yunhui Cui wrote:
> > From: Yunhui Cui
> >
> > With the physical sectors combination, S25FS-S family flash requires
> > some special operations for read/write functions.
> &
From: Yunhui Cui
Add extra info in LUT table to support some special requerments.
Spansion S25FS-S family flash need some special operations.
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 44 +--
include/linux/mtd/spi-nor.h | 4
There is a hardware feature that qspi_amba_base is added
internally by SOC design on ls2080a. So as to software, the driver
need support to the feature.
Signed-off-by: Yunhui Cui
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 24 ++--
1 file changed, 22
From: Yunhui Cui
Add some lut_tables to support quad mode for flash n25q128
on the board ls1021a-twr and solve flash Spansion and Micron
command conflict.
In switch {}, The value of command SPINOR_OP_RD_EVCR and
SPINOR_OP_SPANSION_RDAR is the same. They have to share
the same seq_id
From: Yunhui Cui
With the physical sectors combination, S25FS-S family flash
requires some special operations for read/write functions.
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/spi-nor.c | 56 +++
1 file changed, 56 insertions(+)
diff --git a
There are some read modes for flash, such as NORMAL, FAST,
QUAD, DDR QUAD. These modes will use the identical lut table base
So rename SEQID_QUAD_READ to SEQID_READ.
Signed-off-by: Yunhui Cui
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 8
1 file changed, 4
We can get the read/write/erase opcode from the spi nor framework
directly. This patch uses the information stored in the SPI-NOR to
remove the hardcode in the fsl_qspi_init_lut().
Signed-off-by: Yunhui Cui
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 40
From: Yunhui Cui
The qspi driver add generic fast-read mode for different
flash venders. There are some different board flash work on
different mode, such fast-read, quad-mode.
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 21 -
1 file changed, 16
From: Yunhui Cui
A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data
Affects: QuadSPI
Description: With AHB buffer prefetch enabled, the QuadSPI may return
incorrect data on the AHB
interface. The buffer pre-fetch is enabled if the fetch size as
configured either in the LUT or
From: Yunhui Cui
There is a hardware feature that qspi_amba_base is added
internally by SOC design on ls2080a. so memmap_phy need not
be added in driver. If memmap_phy is added, the flash A1
addr space is [0, memmap_phy] which far more than flash size.
The AMBA memory will be divided into four
Hi Brian and Han,
Could you please give me some comments about this patch set v2 ?
Thanks
> -Original Message-
> From: Yunhui Cui [mailto:b56...@freescale.com]
> Sent: Friday, April 22, 2016 2:40 PM
> To: dw...@infradead.org; computersforpe...@gmail.com;
> han...@fre
From: Yunhui Cui
The qspi driver add generic fast-read mode for different
flash venders. There are some different board flash work on
different mode, such fast-read, quad-mode.
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 21 -
1 file changed, 16
There are some read modes for flash, such as NORMAL, FAST,
QUAD, DDR QUAD. These modes will use the identical lut table base
So rename SEQID_QUAD_READ to SEQID_READ.
Signed-off-by: Yunhui Cui
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 8
1 file changed, 4
We can get the read/write/erase opcode from the spi nor framework
directly. This patch uses the information stored in the SPI-NOR to
remove the hardcode in the fsl_qspi_init_lut().
Signed-off-by: Yunhui Cui
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 40
From: Yunhui Cui
For Micron family ,The status register write enable/disable bit,
provides hardware data protection for the device.
When the enable/disable bit is set to 1, the status register
nonvolatile bits become read-only and the WRITE STATUS REGISTER
operation will not execute.
Signed-off
斌 (beanhuo) [mailto:bean...@micron.com]
Sent: Monday, March 21, 2016 10:56 AM
To: Yunhui Cui; Yunhui Cui
Cc: linux-...@lists.infradead.org; dw...@infradead.org;
computersforpe...@gmail.com; han...@freescale.com;
linux-kernel@vger.kernel.org; linux-...@lists.infradead.org;
linux-arm-ker...@lists.infradea
al Message-
From: Han Xu [mailto:xhnj...@gmail.com]
Sent: Tuesday, March 01, 2016 4:17 AM
To: Yunhui Cui
Cc: Yunhui Cui; dw...@infradead.org; computersforpe...@gmail.com;
han...@freescale.com; linux-...@lists.infradead.org;
linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
This patch adds dts nodes for DSPI on LS1043A-RDB.
Signed-off-by: Yunhui Cui
Signed-off-by: Yuan Yao
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
b/arch/arm64/boot/dts
There are some read modes for flash, such as NORMAL, FAST,
QUAD, DDR QUAD. These modes will use the identical lut table base
So rename SEQID_QUAD_READ to SEQID_READ.
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 8
1 file changed, 4 insertions(+), 4 deletions
We can get the read/write/erase opcode from the spi nor framework
directly. This patch uses the information stored in the SPI-NOR to
remove the hardcode in the fsl_qspi_init_lut().
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 40 ---
1
For Micron family ,The status register write enable/disable bit,
provides hardware data protection for the device.
When the enable/disable bit is set to 1, the status register
nonvolatile bits become read-only and the WRITE STATUS REGISTER
operation will not execute.
Signed-off-by: Yunhui Cui
The qspi driver add generic fast-read mode for different
flash venders. There are some different board flash work on
different mode, such fast-read, quad-mode.
So we have to modify the third entrace parameter of spi_nor_scan().
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c
Hi Cyrille,
Thanks for your suggestions very much, I'll resend version 2 patch set.
Best Regards
Yunhui
-Original Message-
From: Cyrille Pitchen [mailto:cyrille.pitc...@atmel.com]
Sent: Friday, January 29, 2016 10:51 PM
To: Yunhui Cui; dw...@infradead.org; computersforpe...@gmai
This patch set depend on the patch:
{
https://patchwork.ozlabs.org/patch/545926/
LS1021a also support Freescale Quad SPI controller.
Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
selectable for LS1021A SOC hardwares.
}
There is a N25Q128 flash on LS1021ATWR.
This patch test on
We can get the read/write/erase opcode from the spi nor framework
directly. This patch uses the information stored in the SPI-NOR to
remove the hardcode in the fsl_qspi_init_lut().
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 40 ---
1
There are some read modes for flash, such as NORMAL, FAST,
QUAD, DDR QUAD. These modes will use the identical lut table base
So rename SEQID_QUAD_READ to SEQID_READ.
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 8
1 file changed, 4 insertions(+), 4 deletions
The qspi driver add generic fast-read mode for different
flash venders, including Micron family. Also add some special
operations for Micron flash read/write in spi-nor.c.
Signed-off-by: Yunhui Cui
---
drivers/mtd/spi-nor/fsl-quadspi.c | 27 +--
drivers/mtd/spi-nor/spi
mands (20h or 21h) separately.
>
> So better to erase the whole flash using 4K sector erase instead of
> detecting these family parts again and do two different erase operations.
>
> Cc: Brian Norris
> Cc: Yunhui Cui
> Cc: Michael Trimarchi
> Signed-off-by: Jagan Teki
>
On August 16, 2016 2:03 AM, Leo wrote:
> On Fri, Apr 22, 2016 at 1:39 AM, Yunhui Cui wrote:
> > From: Yunhui Cui
> >
> > With the physical sectors combination, S25FS-S family flash requires
> > some special operations for read/write functions.
> &
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