On 05/07/2014 01:20 PM, Peter Ujfalusi wrote:
Hi,
Changes since v1:
- ATL binding documentation and driver has been separated.
Audio Tracking Logic is designed to be used by HD Radio applications to
synchronize the audio output clocks to the baseband clock. ATL can be also
used to track errors
On 02/14/2014 01:13 AM, Tony Lindgren wrote:
* Nishanth Menon [140205 01:06]:
omap3_noncore_dpll_set_rate forces a reparent to the same clk_ref
for every call that takes place. This is an can be done only if a change
is detected.
Signed-off-by: Nishanth Menon
Would like to see acks on this
r Ujfalusi
Acked-by: Tero Kristo
---
arch/arm/boot/dts/omap54xx-clocks.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi
b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index d784ff5d3904..86fc507a0567 100644
--- a/arch/ar
On 04/30/2014 02:41 PM, Peter Ujfalusi wrote:
In OMAP5 bit 8 in PRCM registers are not defined (Reserved) unlike their
counterpart in OMAP4.
It is better to not write to these bits.
Yeah, looks like this bug was copied over from the legacy clock data.
Acked-by: Tero Kristo
Signed-off-by
On 04/26/2014 02:02 AM, Joel Fernandes wrote:
From: Lokesh Vutla
DES IP already has main and interface clk as des_fck.
Node for des_fck is missing in clk tree. Adding the same.
Signed-off-by: Lokesh Vutla
Signed-off-by: Joel Fernandes
---
arch/arm/boot/dts/omap44xx-clocks.dtsi |8 +
: Rajendra Nayak
Cc: Tero Kristo
Cc: Paul Walmsley
Signed-off-by: Keerthy
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index
On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
From: Keerthy
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Why? Needs a better changelog also.
-Tero
Cc: Rajendra Nayak
Cc: Tero Kristo
Cc: Paul Walmsley
Signed-off-by: Keerthy
Signed
good to me.
-Tero
Cc: Tony Lindgren
Cc: Rajendra Nayak
Cc: Tero Kristo
Cc: Paul Walmsley
Cc: Tony Lindgren
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Kumar Gala
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |8
1 file changed
register offset wrong on these? Should be
0x13b8, no, or is my TRM version wrong?
-Tero
Cc: Rajendra Nayak
Cc: Tero Kristo
Cc: Paul Walmsley
Cc: Tony Lindgren
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Kumar Gala
Signed-off-by: Keerthy
Signed-off-by: Kishon Vijay Abraham I
On 05/29/2014 12:47 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-05-19 05:23:10)
On 05/19/2014 02:25 PM, Julia Lawall wrote:
From: Julia Lawall
Add a returned error code in the MAX_APLL_WAIT_TRIES case. Remove the
updating of the return variable r to 0 if MAX_APLL_WAIT_TRIES is not
On 06/16/2014 12:32 PM, Dan Carpenter wrote:
There is a cut and paste bug here which will lead to memory corruption
because we don't allocate enough data.
Fixes: 4d008589e271 ('CLK: TI: APLL: add support for omap2 aplls')
Signed-off-by: Dan Carpenter
Thanks, queued for 3.16-rc fixes.
-Tero
On 06/19/2014 04:00 PM, Kishon Vijay Abraham I wrote:
Hi Tero,
On Thursday 19 June 2014 04:42 PM, Tero Kristo wrote:
On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
From: Keerthy
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Why? Needs a
On 06/19/2014 04:23 PM, Kishon Vijay Abraham I wrote:
Hi Tero,
On Thursday 19 June 2014 04:46 PM, Tero Kristo wrote:
On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
Added missing 32khz clock used by PCIe PHY.
The documention for this node can be found @ ../bindings/clock/ti/gate.txt
On 06/19/2014 03:45 PM, Kishon Vijay Abraham I wrote:
Hi Tero,
On Thursday 19 June 2014 04:40 PM, Tero Kristo wrote:
On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
From: Keerthy
Add divider table to optfclk_pciephy_div clock. The Documentation
for divider clock can be found at
On 07/29/2014 09:27 AM, Mike Turquette wrote:
Quoting Peter Ujfalusi (2014-07-14 03:10:28)
On 05/06/2014 04:39 PM, Peter Ujfalusi wrote:
Tero: can I have your ack for this patch or do you have further concerns?
Yea looks good to me, except for the fact that there is some work on getting
defau
On 03/07/2014 03:09 PM, Roger Quadros wrote:
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Also program USB_DLL_M2 output to half rate.
CC: Mike Turquette
CC: Tero Kristo
Signed-off-by: Roger Quadros
---
drivers/clk/ti/clk-7xx.c | 11 +++
1 file
On 06/26/2014 05:22 PM, Roger Quadros wrote:
+Tero
On 06/26/2014 12:36 PM, Roger Quadros wrote:
On 06/26/2014 10:31 AM, Tony Lindgren wrote:
* Nishanth Menon [140625 15:29]:
On 06/25/2014 07:56 AM, Roger Quadros wrote:
The SATA and USB PHYs need the 1.8V and 3.3V supplies.
The PHY drivers/f
On 05/23/2014 04:34 AM, Mike Turquette wrote:
Quoting Sylwester Nawrocki (2014-04-11 05:25:49)
+==Assigned clock parents and rates==
+
+Some platforms require static initial configuration of parts of the clocks
+controller. Such a configuration can be specified in a clock consumer node
+through
On 05/16/2014 01:45 PM, Nishanth Menon wrote:
Hi,
This patch series has been carried over in vendor kernel for quiet
few years now.
Unfortunately, it was very recently re-discovered and upstream kernel
is noticed to be broken for OMAP5 1.5GHz - at least we are operating
DPLL at frequency higher
On 05/24/2014 12:07 AM, Mike Turquette wrote:
Quoting Nishanth Menon (2014-05-16 03:45:57)
Hi,
This patch series has been carried over in vendor kernel for quiet
few years now.
Unfortunately, it was very recently re-discovered and upstream kernel
is noticed to be broken for OMAP5 1.5GHz - at l
running PTP.
clockcheck: clock jumped backward or running slower than expected!
By selecting dpll_core_m5_ck as the clocksource fixes this issue.
In AM335x dpll_core_m5_ck is the default clocksource.
Signed-off-by: George Cherian
Acked-by: Tero Kristo
---
drivers/clk/ti/clk-43xx.c | 16
promised to pull this with rc-fixes. So, for that purpose:
Acked-by: Tero Kristo
---
arch/arm/boot/dts/dra7.dtsi | 11 +++
arch/arm/boot/dts/dra7xx-clocks.dtsi | 16
2 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/dra7
On 01/28/2014 11:48 AM, Tomi Valkeinen wrote:
On 2014-01-28 11:35, Christoph Fritz wrote:
On Tue, 2014-01-28 at 11:04 +0200, Tomi Valkeinen wrote:
On 2014-01-27 20:41, Christoph Fritz wrote:
On Mon, 2014-01-27 at 19:30 +0200, Ivaylo Dimitrov wrote:
linux-next-20140124 DSS is broken on N900 -
s modelled
improperly in the dts files. I don't have access to omap36xx hardware
myself, but give a try for the following patch:
From: Tero Kristo
Date: Wed, 29 Jan 2014 11:03:46 +0200
Subject: [PATCH] ARM: dts: omap36xx: fix omap96m_alwon_fck
OMAP36xx has different hardware impleme
On 01/29/2014 11:38 AM, Tomi Valkeinen wrote:
On 2014-01-29 11:29, Ivaylo Dimitrov wrote:
On 29.01.2014 11:10, Tero Kristo wrote:
It looks like the omap36xx version of the omap96m_alwon_fck is modelled
improperly in the dts files. I don't have access to omap36xx hardware
myself, but g
On 01/29/2014 01:21 PM, Christoph Fritz wrote:
On Tue, 2014-01-28 at 18:02 +0100, Christoph Fritz wrote:
On Tue, 2014-01-28 at 15:40 +0200, Tero Kristo wrote:
Due to a regression since next-20140122 the following errors are present:
- pin sys_clkout2, which gets configured to 24 Mhz by
On 01/29/2014 01:21 PM, Christoph Fritz wrote:
On Tue, 2014-01-28 at 18:02 +0100, Christoph Fritz wrote:
On Tue, 2014-01-28 at 15:40 +0200, Tero Kristo wrote:
Due to a regression since next-20140122 the following errors are present:
- pin sys_clkout2, which gets configured to 24 Mhz by
regmap_debugfs_early list is created for
this purpose which is parsed later in the boot.
Signed-off-by: Tero Kristo
---
drivers/base/regmap/regmap-debugfs.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/base/regmap/regmap-debugfs.c
b/drivers/base
On 10/24/2013 12:18 PM, Mark Brown wrote:
On Thu, Oct 24, 2013 at 12:07:48PM +0300, Tero Kristo wrote:
+ if (!regmap_debugfs_root) {
+ struct regmap_debugfs_node *node;
+ node = kzalloc(sizeof(*node), GFP_KERNEL);
+ if (!node
regmap_debugfs_early list is created for
this purpose which is parsed later in the boot.
Signed-off-by: Tero Kristo
---
drivers/base/regmap/regmap-debugfs.c | 57 +++---
1 file changed, 52 insertions(+), 5 deletions(-)
diff --git a/drivers/base/regmap/regmap-debugfs.c
On 08/18/2014 07:56 PM, Nishanth Menon wrote:
Hi,
The following patches are based on v3.17-rc1
Prior to this series: http://slexy.org/view/s20QH6PW4x (notice the /0 div error
spam at initial boot log)
After this series: http://slexy.org/view/s20tPNXPf4
Yeah, valid findings. However, you did no
: Tero Kristo
To: Mike Turquette
Reported-by: Nishanth Menon
---
drivers/clk/clk.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index b76fa69..bacc06f 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1467,6 +1467,7
On 07/31/2014 04:49 PM, Felipe Balbi wrote:
Hi,
On Thu, Jul 31, 2014 at 10:57:09AM +0300, Tero Kristo wrote:
On 07/31/2014 09:28 AM, Tony Lindgren wrote:
* Felipe Balbi [140730 09:23]:
Hi,
On Wed, Jul 30, 2014 at 10:45:41AM -0500, Nishanth Menon wrote:
On Wed, Jul 30, 2014 at 9:40 AM
Hi Tomeu,
Please add a changelog to this patch. Also, just replace the
clk-private.h includes with clk-provider.h, do not add the include to
the generic header. Rest of the kernel does that where needed.
Other than that, looks good to me.
-Tero
On 10/03/2014 06:51 PM, Tomeu Vizoso wrote:
S
On 09/30/2014 10:03 PM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-30 01:48:49)
On 09/30/2014 10:07 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-29 01:09:24)
On 09/27/2014 02:24 AM, Mike Turquette wrote:
Quoting Tero Kristo (2014-09-26 00:18:55)
On 09/26/2014 04:35 AM
On 09/30/2014 09:16 PM, Tony Lindgren wrote:
* Tero Kristo [140930 00:41]:
On 09/30/2014 09:54 AM, Mike Turquette wrote:
Quoting Stephen Boyd (2014-09-29 18:40:23)
On 09/29/14 11:17, Tomeu Vizoso wrote:
Also moves clock state to struct clk_core, but takes care to change as little
API as
On 07/27/2015 01:27 PM, Roger Quadros wrote:
Hi,
This series cleans up the scm_conf node.
v2:
- split patch. use only core_sma_sw registers for the new scm_conf child.
Series looks ok to me, so:
Acked-by: Tero Kristo
cheers,
-roger
Roger Quadros (3):
ARM: dts: dra7: Remove ctrl_core
uct.
Anyway, I guess we can fix the ssi/usb clocks later if we find some
issues with them, its been at least 3 years since these have been used.
-Tero
Cc: Tero Kristo
Signed-off-by: Stephen Boyd
---
drivers/clk/ti/clk-3xxx.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/dr
-3xxx.c | 10 --
drivers/clk/ti/clk.c | 6 --
2 files changed, 4 insertions(+), 12 deletions(-)
For the whole set:
Acked-by: Tero Kristo
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On 28/04/16 12:12, H. Nikolaus Schaller wrote:
Hi Tero,
Am 28.04.2016 um 10:03 schrieb Tero Kristo :
On 27/04/16 17:35, H. Nikolaus Schaller wrote:
HI,
Am 27.04.2016 um 16:23 schrieb Peter Ujfalusi :
On 04/27/2016 05:10 PM, Tero Kristo wrote:
On 27/04/16 16:10, H. Nikolaus Schaller wrote
On 09/05/16 14:18, H. Nikolaus Schaller wrote:
Hi,
Am 28.04.2016 um 15:23 schrieb Tero Kristo :
On 28/04/16 12:12, H. Nikolaus Schaller wrote:
Hi Tero,
Am 28.04.2016 um 10:03 schrieb Tero Kristo :
On 27/04/16 17:35, H. Nikolaus Schaller wrote:
HI,
Am 27.04.2016 um 16:23 schrieb Peter
On 09/05/16 16:52, Peter Ujfalusi wrote:
On 05/09/16 15:46, Peter Ujfalusi wrote:
On 05/09/16 15:32, Peter Ujfalusi wrote:
On 05/09/16 15:10, Peter Ujfalusi wrote:
finally I found some time to apply your patches. Sorry for the long time.
Unfortunately, it does not work. Neither on omap5evm n
On 02/05/16 20:12, J.D. Schroeder wrote:
From: "J.D. Schroeder"
This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck) frequency
from the precise 32kHz frequency (i.e., 32.768 kHz) to a more
accurate frequency of ~34.6 kHz. Actual measured frequencies of the
clock vary from processor to pr
On 03/05/16 19:43, Tony Lindgren wrote:
* J.D. Schroeder [160503 06:32]:
On 05/03/2016 03:16 AM, Tero Kristo wrote:
On 02/05/16 20:12, J.D. Schroeder wrote:
From: "J.D. Schroeder"
This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck) frequency
from the precise 32kHz freq
On 03/05/16 20:49, J.D. Schroeder wrote:
On 05/03/2016 12:32 PM, Tero Kristo wrote:
Personally I would not recommend using this clock for any timing sensitive
applications. May I ask why you are interested in the exact clock rate of this
clock anyway?
I'm not interested in using this
On 25/05/16 19:09, Nishanth Menon wrote:
On 05/25/2016 07:53 AM, Ravikumar Kattekola wrote:
DRA72x devices have a sixth i2c ocntroller instance.
Following patches add the required hwmod structure and
device tree nodes.
Reference doc: DRA72x TRM [ SPRUHP2Q ]
Tested on :
DRA72x Rev B EVM
Raviku
nce in our
clock data across SoCs. Good catch.
Acked-by: Tero Kristo
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index d0bae06..9d1a
On 26/04/16 20:54, J.D. Schroeder wrote:
From: "J.D. Schroeder"
This commit fixes the 32kHz clock (sys_32k_ck) calculation to be
correctly based on the SYS_CLK1 (sys_clkin1) frequency. Based on the
TRM CTRL_CORE_BOOTSTRAP[9:8] SPEEDSELECT, set by the SYSBOOT[9:8]
board jumpers according to the
On 26/04/16 20:54, J.D. Schroeder wrote:
From: "J.D. Schroeder"
This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck) frequency
from the precise 32kHz frequency (i.e., 32.768 kHz) to the more
accurate frequency of ~34.6 kHz. Actual measured frequencies of the
clock vary from board to boar
On 27/04/16 09:04, H. Nikolaus Schaller wrote:
Am 26.04.2016 um 19:27 schrieb Tony Lindgren :
Tero,
* H. Nikolaus Schaller [160418 11:23]:
OMAP5 has a register to control if the ckobuffer is enabled
and defines the polarity. ckobuffer is required to drive a twl6040
with the system clock. He
shouldn't remove the old entries.
Signed-off-by: Franklin S Cooper Jr
Acked-by: Stephen Boyd
I don't like adding new clock aliases to the list as I am trying to get
rid of them, but in this case we can't avoid it I believe. Thus,
Acked-by: Tero Kristo
---
drivers/clk/ti
On 27/04/16 16:10, H. Nikolaus Schaller wrote:
Am 27.04.2016 um 14:31 schrieb Tero Kristo :
On 27/04/16 09:04, H. Nikolaus Schaller wrote:
Am 26.04.2016 um 19:27 schrieb Tony Lindgren :
Tero,
* H. Nikolaus Schaller [160418 11:23]:
OMAP5 has a register to control if the ckobuffer is
On 27/04/16 17:06, J.D. Schroeder wrote:
On 04/27/2016 06:40 AM, Tero Kristo wrote:
On 26/04/16 20:54, J.D. Schroeder wrote:
This commit fixes the 32kHz clock (sys_32k_ck) calculation to be
correctly based on the SYS_CLK1 (sys_clkin1) frequency. Based on the
TRM CTRL_CORE_BOOTSTRAP[9:8
On 27/04/16 17:35, H. Nikolaus Schaller wrote:
HI,
Am 27.04.2016 um 16:23 schrieb Peter Ujfalusi :
On 04/27/2016 05:10 PM, Tero Kristo wrote:
On 27/04/16 16:10, H. Nikolaus Schaller wrote:
Am 27.04.2016 um 14:31 schrieb Tero Kristo :
On 27/04/16 09:04, H. Nikolaus Schaller wrote:
Am
On 12/08/2015 06:57 PM, Tony Lindgren wrote:
* Tony Lindgren [151201 15:43]:
The timer clock aliases are needed early on dm814x. Let's also
add the aliases for the interconnects and MMC.
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: Tero Kristo
Signed-off-by: Tony Lindgren
Anybody fro
On 12/08/2015 10:11 PM, Tony Lindgren wrote:
* Tero Kristo [151208 11:25]:
On 12/08/2015 06:57 PM, Tony Lindgren wrote:
Anybody from the clock department care to ack this one?
Sorry been rather busy lately...
I'd like to
get this series into Linux next as it fixes some some i
On 07/17/2015 04:47 PM, Roger Quadros wrote:
scm_conf1 maps the control register address space after the
padconf till the end.
Fix the scm_conf and pmx_core resource lengths. We need to add
4 bytes to include the last 32-bit register space.
Remove the redundant dra7_ctrl_core and dra7_ctrl_gene
On 07/17/2015 04:47 PM, Roger Quadros wrote:
This register is required to be passed to the SATA PHY driver
to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock).
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/a
based on struct
clk_divider.
Signed-off-by: Mike Turquette
[james.ho...@imgtec.com: forward port, fix new uses of width]
Signed-off-by: James Hogan
Tested-by: Shawn Guo
Tested-by: Heiko Stuebner
Reviewed-by: Heiko Stuebner
Cc: "Emilio López"
Cc: Sascha Hauer
Cc: Shawn Guo
Cc: Tero
On 11/14/2014 01:58 AM, Tony Lindgren wrote:
* Paul Walmsley [141113 15:01]:
Hi
On Thu, 13 Nov 2014, Tony Lindgren wrote:
* Tomi Valkeinen [141113 03:33]:
On 12/11/14 17:02, Tony Lindgren wrote:
And, with a quick grep, I see CONTROL_DEVCONF1 touched in multiple
places in the kernel. I wo
On 05/25/2015 05:24 PM, Bartosz Golaszewski wrote:
Hi Tero,
I tried booting a BeagleBone Black Rev C with current git, but got no
output after u-boot's "Starting kernel ...". Bisect points at commit
e3bc5358 ARM: dts: am33xx: add minimal l4 bus layout with control
module support. Let me know if
tl_clk_ops' was not
declared. Should it be static?
drivers/clk/ti/clk-dra7-atl.c:170:39: warning: Using plain integer as NULL
pointer
Cc: Peter Ujfalusi
Cc: Tero Kristo
Signed-off-by: Stephen Boyd
Acked-by: Peter Ujfalusi
Yes looks good to me also.
Acked-by: Tero Kristo
---
dri
t with
my patch and a note that it's based on an earlier patch from you.
FWIW, just gave a try for these two patches on all TI boards I have
access to.
Tested-by: Tero Kristo
I didn't try your evolved patch though, as you don't seem to have made
your mind yet.
-Tero
T
On 05/07/2015 09:18 PM, Stephen Boyd wrote:
On 05/07/15 01:22, Tero Kristo wrote:
On 05/02/2015 02:40 AM, Stephen Boyd wrote:
On 05/01/15 15:07, Heiko Stübner wrote:
Am Freitag, 1. Mai 2015, 13:52:47 schrieb Stephen Boyd:
Instead I guess we could hook it less deep into clk_get_sys, like
in
On 05/13/2015 09:54 AM, Krzysztof Kozlowski wrote:
Hi,
clk_get_sys() may return ERR_PTR but the drivers immediately
dereferenced the return value. This could lead to oops.
I tried only to fix possible ERR_PTR dereference and to not change
the logic. This is why some of the patches look quite c
+--
2 files changed, 118 insertions(+), 13 deletions(-)
Hi Benoit,
Can these fixes be looked into for 3.20-rc?
Seem like valid fixes to me. Tero, care to take a look at these and ack
if OK?
Yes, both are good to go.
Acked-by: Tero Kristo
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, sorry about that.
Acked-by: Tero Kristo
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Please read the FAQ at http://www.tux.org/lkml/
d a define for the fixed SYNTH_PHASE_K instead of using 8.
Cc: Brian Hutchinson
Cc: Matthijs van Duin
Cc: Tero Kristo
Signed-off-by: Tony Lindgren
---
drivers/clk/ti/fapll.c | 134 -
1 file changed, 132 insertions(+), 2 deletions(-)
diff --git
On 03/16/2015 12:40 PM, Peter Ujfalusi wrote:
Hi,
This series will fix the following error during boot (both DT and legacy boot):
[0.307739] omap_hwmod: mcbsp2: _wait_target_ready failed: -16
[0.307769] omap_hwmod: mcbsp2: cannot be enabled for reset (3)
The clock definitions/aliases fo
On 03/14/2015 12:58 AM, Suman Anna wrote:
Hi Tero,
Please find couple of cleanup/fixes on the DT clock aliases
for the GPTimers. Patches are based on 4.0-rc1 and following
is the summary of the changes,
1. Patch 1 is a cleanup for OMAP4
2. Patch 2 fixes the failures for OMAP5 if omap_dm_timer_s
On 03/24/2015 06:37 PM, Tony Lindgren wrote:
* Tony Lindgren [150323 08:58]:
* Tero Kristo [150323 06:25]:
This code is generating these compile time warnings for me:
CC drivers/clk/ti/fapll.o
drivers/clk/ti/fapll.c: In function ‘ti_fapll_synth_set_rate’:
drivers/clk/ti/fapll.c:394
rate constraints patch broke boot for me completely, but sounds
like you reverted it already.
-Tero
Author: Tero Kristo
Date: Mon Feb 2 17:19:17 2015 +0200
ARM: OMAP3+: clock: dpll: fix logic for comparing parent clocks
DPLL code uses reference and bypass cloc
On 02/03/2015 09:03 AM, Tomeu Vizoso wrote:
On 02/02/2015 11:41 PM, Mike Turquette wrote:
Quoting Tero Kristo (2015-02-02 11:32:01)
On 02/01/2015 11:24 PM, Mike Turquette wrote:
Quoting Tomeu Vizoso (2015-01-23 03:03:30)
Moves clock state to struct clk_core, but takes care to change as
On 12/16/2014 04:58 PM, Nishanth Menon wrote:
On 17:05-20141216, Lokesh Vutla wrote:
[...]
@@ -545,6 +546,16 @@ static void __init realtime_counter_init(void)
break;
}
+ if (soc_is_dra7xx()) {
+ reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
+
On 12/17/2014 05:27 PM, Lennart Sorensen wrote:
On Wed, Dec 17, 2014 at 09:22:25AM -0600, Nishanth Menon wrote:
A clock mux might do the job?
value 1, 2 , 3 will imply sysclk1 / 610
value of 0 implies fixed 32768
soemthing like
sys_clk32_crystal {
compatible = "fixed-clock";
On 12/17/2014 05:53 PM, Nishanth Menon wrote:
On 17:45-20141217, Tero Kristo wrote:
On 12/17/2014 05:27 PM, Lennart Sorensen wrote:
On Wed, Dec 17, 2014 at 09:22:25AM -0600, Nishanth Menon wrote:
A clock mux might do the job?
value 1, 2 , 3 will imply sysclk1 / 610
value of 0 implies fixed
On 22/04/16 14:52, Peter Ujfalusi wrote:
On 04/22/16 01:29, Stephen Boyd wrote:
The first issue with converting the McASP to use CCF internally for clock
selection, muxing and rate configuration is that the daVinci platform does not
use CCF at all. Given that the davinci-mcasp driver is used by
other problems (some APIs used during init
will attempt to lock the mutex also, causing deadlock.)
Signed-off-by: Tero Kristo
Reported-by: Tomi Valkeinen
---
drivers/regulator/core.c |2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
On 18/04/16 14:59, Mark Brown wrote:
On Mon, Apr 18, 2016 at 02:49:53PM +0300, Tero Kristo wrote:
suspend_prepare can be called during regulator init time also, where
It can be? That seems unexpected...
regulator_register()
-> set_machine_constraints()
-> suspend_prepare()
Cal
seudo clock naming here. So dropping for now.
The patch is fine for me, I didn't comment anything before as I thought
you already applied it.
Acked-by: Tero Kristo
Regards,
Tony
On 04/01/2016 06:36 PM, Tony Lindgren wrote:
Hi,
* Tony Lindgren [160331 10:04]:
* Keerthy [160331 02:26]:
On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
On 03/31/2016 12:32 AM, Tony Lindgren wrote:
* Tony Lindgren [160330 14:19]:
* Keerthy [160314 05:04]:
This is w.r.t J6
On 11/13/2015 06:29 PM, Neil Armstrong wrote:
Add missing clkdev dmtimer related entries for dm816x.
32Khz and ext sources were missing.
Cc: Brian Hutchinson
Acked-by: Tony Lindgren
Signed-off-by: Neil Armstrong
Your own sign-off should be at the top of the list, fixed this locally
myself.
On 09/14/2015 11:52 AM, Peter Ujfalusi wrote:
Hi Tero,
On 08/24/2015 10:35 AM, Peter Ujfalusi wrote:
The ABE related clocks should be configured via DT and not have it wired
inside of the kernel.
can you take a look at this patch? It will not cause any regression since we
do not have audio su
On 09/30/2015 01:06 PM, Peter Ujfalusi wrote:
Paul,
On 09/27/2015 10:02 AM, Paul Walmsley wrote:
/*
+ * 'mcasp' class
+ *
+ */
+static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
+ .sysc_offs = 0x0004,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes
Hi,
Mostly some cosmetic comments below, other than that seems fine to me.
On 30/07/2019 12:34, Peter Ujfalusi wrote:
From: Grygorii Strashko
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
enable straightforward passing of work between a producer and a consumer.
There
On 24/07/2019 09:47, Tony Lindgren wrote:
* Suman Anna [190723 21:02]:
Hi Tony,
On 7/23/19 6:28 AM, Tony Lindgren wrote:
The ahclkr clkctrl clock bit 28 only exists for mcasp 1 and 2 on dra7.
Otherwise we get the following warning on beagle-x15:
...
@@ -2962,9 +2958,8 @@
On 07/10/2019 18:52, Tony Lindgren wrote:
Hi,
* H. Nikolaus Schaller [191005 16:59]:
Hi all,
with the arrival of v5.4-rc1 some of Tony's sysc patches have arrived
upstream, so we do no longer need them here.
Therefore, I have rebased my drivers/staging/pvr driver [1] and fixed some
more issue
On 07/10/2019 22:24, H. Nikolaus Schaller wrote:
Hi Tero,
Am 07.10.2019 um 21:18 schrieb Tero Kristo :
On 07/10/2019 18:52, Tony Lindgren wrote:
Hi,
* H. Nikolaus Schaller [191005 16:59]:
Please try with Tero's current github branch at github.com/t-kristo/linux-pm.git
5.4-rc1-ipc fro
owever, it is just
cosmetic so I don't mind.
Reviewed-by: Tero Kristo
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
On 01/10/2019 09:16, Peter Ujfalusi wrote:
Update the provider and client documentation with details about the
metadata support.
Signed-off-by: Peter Ujfalusi
Couple of typos below, but they don't really change the readability of
the document so:
Reviewed-by: Tero K
other than that:
Reviewed-by: Tero Kristo
---
drivers/dma/dmaengine.c | 73 ++
include/linux/dmaengine.h | 108 ++
+ * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
+ * driver. The client driver
On 01/10/2019 09:16, Peter Ujfalusi wrote:
It might be good to add some sort of description for the patch. At least
telling what cppi5 actually is and why it is needed for UDMA.
Other than that, looks fine to me.
-Tero
Signed-off-by: Peter Ujfalusi
---
include/linux/dma/ti-cppi5.h | 1049
can affect the latenc/delay
Signed-off-by: Peter Ujfalusi
Reviewed-by: Tero Kristo
---
drivers/dma/dmaengine.h | 8
include/linux/dmaengine.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
index 501c0b063f85
anything
obviously broken, thus:
Reviewed-by: Tero Kristo
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
On 09/10/2019 15:53, H. Nikolaus Schaller wrote:
Am 08.10.2019 um 22:15 schrieb H. Nikolaus Schaller :
Am 08.10.2019 um 10:00 schrieb Tero Kristo :
On 07/10/2019 22:24, H. Nikolaus Schaller wrote:
Hi Tero,
Am 07.10.2019 um 21:18 schrieb Tero Kristo :
On 07/10/2019 18:52, Tony Lindgren
On 09/10/2019 17:23, H. Nikolaus Schaller wrote:
Am 09.10.2019 um 15:55 schrieb Tero Kristo :
On 09/10/2019 15:53, H. Nikolaus Schaller wrote:
Am 08.10.2019 um 22:15 schrieb H. Nikolaus Schaller :
But I can't access the sgx registers and get memory faults. Maybe
my script has a bug a
On 22/10/2019 19:21, Benoit Parrot wrote:
Tony Lindgren wrote on Tue [2019-Oct-22 08:48:16 -0700]:
* Benoit Parrot [191016 18:47]:
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -704,6 +704,60 @@
ti,bit-shift = <8>;
reg
On 09/10/2019 12:57, Faiz Abbas wrote:
Hi,
On 19/09/19 9:02 PM, Faiz Abbas wrote:
The following are dts patches to add MMC/SD Support on TI's J721e base
board.
Patches depend on Lokesh's gpio patches[1] and device exclusivity patches[2].
[1] https://patchwork.kernel.org/cover/11085643/
[2] ht
On 03/10/2019 14:42, Faiz Abbas wrote:
MMC0_SDWP is not connected to the card. Indicate this by adding a
disable-wp flag.
Signed-off-by: Faiz Abbas
---
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-boar
On 05/02/2019 14:25, Roger Quadros wrote:
Tero,
On 11/01/19 11:44, Roger Quadros wrote:
The AM65 SoC has 2MB MSMC RAM. Add this as a mmio-sram
node so drivers can use it via genpool API.
Following areas are marked reserved:
- Lower 128KB for ATF
- 64KB@0xf for SYSFW
- Upper 1MB for cache
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