Add support for the global clock controller found on SC7180
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 10 +-
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc
Hello Stephen,
Thanks for your review.
On 7/16/2019 4:22 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-05-08 11:24:54)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 57dbac9..5bb6d45 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
Hello Stephen,
Thanks for the review.
On 7/16/2019 4:14 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-05-12 20:44:46)
On 5/10/2019 11:24 PM, Stephen Boyd wrote:
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 5562f38..e40e8f8 100644
--- a/drivers/clk/qcom/clk
Hi Stephen,
On 10/10/2019 9:46 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-10-09 02:19:39)
Hi Stephen,
On 10/5/2019 4:50 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-10-04 10:39:31)
Could you please confirm if you are referring to update the below?
I wasn't suggesting
Hi Rob,
Thanks for your comments.
On 9/27/2019 10:57 PM, Rob Herring wrote:
On Wed, Sep 18, 2019 at 03:20:17PM +0530, Taniya Das wrote:
The GCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those. Also update
the compatible for
Hi Stephen,
Thanks for your review.
On 9/19/2019 2:56 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-09-18 02:50:17)
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
new file mode 100644
index
[v1]
* Add driver support for Global Clock controller for SC7180 and also
update device tree bindings for the various clocks supported in the
clock controller.
Taniya Das (5):
clk: qcom: rcg: update the DFS macro for RCG
clk: qcom: common: Return NULL from clk_hw OF provider
dt-bind
The GCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt| 94 --
.../devicetree/bindings/clock/qcom,gcc.yaml | 174 ++
2 files
Return NULL in the cases where the clk_hw is not registered with the
clock provider, but the clock consumer still requests for a clock id.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/common.c b
Add support for the global clock controller found on SC7180
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc
Add device tree bindings for Global clock subsystem clock
controller for Qualcomm Technology Inc's SC7180 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.yaml | 14 ++
include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 ++
2 files changed
Update the init data name for each of the dynamic frequency switch
controlled clock associated with the RCG clock name, so that it can be
generated as per the hardware plan. Thus update the macro accordingly.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h| 2 +-
drivers/clk/qcom
Hi Vinod,
On 10/16/2019 10:55 AM, Vinod Koul wrote:
On 15-10-19, 16:03, Rajendra Nayak wrote:
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+,
+,
+;
+ };
+
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <3840>;
+ clock-output-names = "xo_board";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sle
On 10/17/2019 5:57 PM, Amit Kucheria wrote:
Allow qcom-hw driver to initialise right after the cpufreq and thermal
subsystems are initialised in core_initcall so we get earlier access to
thermal mitigation.
Signed-off-by: Amit Kucheria
Acked-by: Daniel Lezcano
---
Acked-by: Taniya Das
Hi Jeffrey,
On 10/2/2019 6:46 AM, Jeffrey Hugo wrote:
The GPUCC manages the clocks for the Adreno GPU found on MSM8998.
Signed-off-by: Jeffrey Hugo
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/gpucc-msm8998.c | 346 +++
Update the Documentation binding of RPMHCC to YAML schemas.
Add RPMH clocks required to be supported on SC7180.
Taniya Das (3):
dt-bindings: clock: Add YAML schemas for the QCOM RPMHCC clock
bindings
dt-bindings: clock: Introduce RPMHCC bindings for SC7180
clk: qcom: clk-rpmh: Add
The RPMHCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,rpmh-clk.txt| 27
.../devicetree/bindings/clock/qcom,rpmhcc.yaml | 49
Add compatible for SC7180 RPMHCC.
Signed-off-by: Taniya Das
---
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
index
Add support for clock RPMh driver to vote for ARC and VRM managed
clock resources.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rpmh.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 96a36f6..7301c77
Hello Stephen,
On 1/19/2019 12:31 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-01-17 03:19:22)
On 1/15/2019 3:55 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-01-13 22:12:39)
On 1/8/2019 2:34 AM, Stephen Boyd wrote:
As far as I know, I'm not suggesting the use of CLK_IS_CRI
Signed-off-by: Taniya Das
---
drivers/cpufreq/qcom-cpufreq-hw.c | 46 +++
1 file changed, 37 insertions(+), 9 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c
b/drivers/cpufreq/qcom-cpufreq-hw.c
index d83939a..402ce81 100644
--- a/drivers/cpufreq
I have updated with the latest patch series v5.
On 1/18/2019 2:34 AM, Matthias Kaehlcke wrote:
Hi Tanyia,
On Thu, Jan 17, 2019 at 04:29:58PM +0530, Taniya Das wrote:
Add support to read the voltage look up table and populate OPP for all
corresponding CPUS for consumers like the energy model
Thanks for the patch, would incorporate in the next patch series.
On 1/15/2019 5:59 AM, Matthias Kaehlcke wrote:
Hi Taniya,
On Wed, Jan 09, 2019 at 01:37:28PM +0530, Taniya Das wrote:
Add support to read the voltage look up table and populate OPP for all
corresponding CPUS for consumers like
Hello Viresh,
On 1/9/2019 2:24 PM, Viresh Kumar wrote:
On 09-01-19, 13:37, Taniya Das wrote:
@@ -98,6 +107,8 @@ static int qcom_cpufreq_hw_read_lut(struct device *dev,
You are only using this "dev" parameter for dev_dbg(), instead of that
pass cpu_dev pointer.
Sure, will clea
Signed-off-by: Taniya Das
---
drivers/cpufreq/qcom-cpufreq-hw.c | 43 +++
1 file changed, 35 insertions(+), 8 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c
b/drivers/cpufreq/qcom-cpufreq-hw.c
index d83939a..8da5576 100644
--- a/drivers/cpufreq
Signed-off-by: Taniya Das
---
drivers/cpufreq/qcom-cpufreq-hw.c | 41 ---
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c
b/drivers/cpufreq/qcom-cpufreq-hw.c
index d83939a..e006938 100644
--- a/drivers/cpufreq
On 1/17/2019 12:57 PM, Viresh Kumar wrote:
On 17-01-19, 12:38, Taniya Das wrote:
@@ -159,10 +170,18 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy
*policy)
struct device *dev = &global_pdev->dev;
struct of_phandle_args args;
struct device_node
On 1/15/2019 3:55 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-01-13 22:12:39)
On 1/8/2019 2:34 AM, Stephen Boyd wrote:
As far as I know, I'm not suggesting the use of CLK_IS_CRITICAL here.
But removing CLK_IS_CRITICAL and relying on some random bootloader
behavior also looks
On 1/8/2019 2:34 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-01-06 22:26:00)
Hello Stephen,
On 12/21/2018 2:34 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-12-20 03:46:25)
The LPASS clocks has a dependency on the GCC lpass clocks to be enabled
before accessing them and that was
require
the hardware control mode to be enabled explicitly.
3) Update the DFS macro as per the hardware plans.
Taniya Das (3):
clk: qcom: rcg: Return failure for RCG update
clk: qcom: rcg2: Add support for hardware control mode
clk: qcom: rcg: update the DFS macro for RCG
drivers/clk/qcom
Add a flag to indicate to support and enable hardware control mode
of an RCG.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h | 3 +++
drivers/clk/qcom/clk-rcg2.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index
In case of update config failure, return -EBUSY, so that consumers could
handle the failure gracefully.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index
Update the init data name for each of the dynamic frequency switch
controlled clock associated with the RCG clock name, so that it can be
generated as per the hardware plan. Thus update the macro accordingly.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h| 2 +-
drivers/clk/qcom
Hello Stephen,
Thanks for the review.
On 5/9/2019 10:57 PM, Stephen Boyd wrote:
Quoting Taniya Das (2019-05-08 11:24:55)
Update the init data name for each of the dynamic frequency switch
controlled clock associated with the RCG clock name, so that it can be
generated as per the hardware plan
Hello Stephen,
On 5/10/2019 11:24 PM, Stephen Boyd wrote:
Quoting Taniya Das (2019-05-09 19:58:39)
Hello Stephen,
Thanks for the review.
On 5/9/2019 10:57 PM, Stephen Boyd wrote:
Quoting Taniya Das (2019-05-08 11:24:55)
Update the init data name for each of the dynamic frequency switch
]
* New display port clock ops supported for display port clocks.
* Also add support for the display port related branches and RCGs.
Taniya Das (2):
clk: qcom: rcg2: Add support for display port clock ops
clk: qcom : dispcc: Add support for display port clocks
drivers/clk/qcom/Kconfig
SDM845 dispcc supports RCG and CBCRs for display port, so add support for
the same.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/dispcc-sdm845.c | 216 -
include/dt-bindings/clock/qcom,dispcc-sdm845.h | 13 +-
2 files changed, 227 insertions(+), 2
New display port clock ops supported for display port clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig| 1 +
drivers/clk/qcom/clk-rcg.h | 1 +
drivers/clk/qcom/clk-rcg2.c | 81 -
3 files changed, 82 insertions(+), 1 deletion
Hi Stephen,
Thanks for your comments.
On 7/16/2019 4:07 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-05-14 21:20:39)
@@ -128,6 +144,82 @@ enum {
},
};
+static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
+ F(1920, P_BI_TCXO, 1, 0, 0
Hello Stephen,
Thanks for your review.
On 7/16/2019 4:13 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-05-14 21:20:38)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 18bdf34..0de080f 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -15,6 +15,7
related branches and RCGs.
Taniya Das (2):
clk: qcom: rcg2: Add support for display port clock ops
clk: qcom : dispcc: Add support for display port clocks
drivers/clk/qcom/Kconfig | 1 +
drivers/clk/qcom/clk-rcg.h| 1 +
drivers/clk/qcom/clk-rcg2.c
New display port clock ops supported for display port clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig| 1 +
drivers/clk/qcom/clk-rcg.h | 1 +
drivers/clk/qcom/clk-rcg2.c | 77 +
3 files changed, 79 insertions(+)
diff --git a/drivers/clk
SDM845 dispcc supports RCG and CBCRs for display port, so add support for
the same.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/dispcc-sdm845.c | 214 +-
.../dt-bindings/clock/qcom,dispcc-sdm845.h| 13 +-
2 files changed, 225 insertions(+), 2 deletions
On 8/1/2019 1:05 AM, Stephen Boyd wrote:
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.
Cc: Taniya Das
Cc: Andy
Hello Stephen,
On 7/17/2019 4:48 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-07-15 21:19:02)
Hello Stephen,
Thanks for your review.
On 7/16/2019 4:22 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-05-08 11:24:54)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
On 7/17/2019 4:52 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-07-15 21:22:02)
Hello Stephen,
Thanks for the review.
On 7/16/2019 4:14 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-05-12 20:44:46)
On 5/10/2019 11:24 PM, Stephen Boyd wrote:
Why is the clk name changing to not have
Add driver support for Global Clock controller for SC7180 and also update
device tree bindings for the various clocks supported in the clock controller.
Taniya Das (2):
clk: qcom: Add DT bindings for SC7180 gcc clock controller
clk: qcom: Add Global Clock controller (GCC) driver for SC7180
Add support for the global clock controller found on SC7180
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc
Add compatible string and the include file for gcc clock
controller for SC7180.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt| 1 +
include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 ++
2 files changed, 156 insertions(+)
create mode 100644
Add support to read the voltage look up table and populate OPP for all
corresponding CPUS for consumers like the energy model could use the
frequency and voltage from the OPP tables.
Tested-by: Matthias Kaehlcke
Signed-off-by: Taniya Das
---
drivers/cpufreq/qcom-cpufreq-hw.c | 33
On 1/8/2019 5:32 AM, Matthias Kaehlcke wrote:
Hi Taniya.
On Mon, Dec 24, 2018 at 12:29:18AM +0530, Taniya Das wrote:
Could you help validating with the patch below?
...
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c
b/drivers/cpufreq/qcom-cpufreq-hw.c
index 7559b87..23338b2 100644
Hello Bjorn,
I believe on few board variants these clocks could be protected and
would be added to protected-clocks list?
On 3/6/2019 11:21 AM, Bjorn Andersson wrote:
Add the clocks and resets need in order to control the Turing
remoteproc.
Signed-off-by: Bjorn Andersson
---
drivers/clk/q
Hello Stephen,
Thanks for the review comments.
On 8/28/2018 2:41 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-03 05:21:14)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 2b69cf2..7bd940d 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
Hello Stephen,
Thanks for the review comments.
On 8/28/2018 2:44 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-03 05:21:13)
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devic
On 9/6/2018 7:21 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-09-05 11:26:10)
On 8/28/2018 2:41 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-03 05:21:14)
diff --git a/drivers/clk/qcom/lpasscc-sdm845.c
b/drivers/clk/qcom/lpasscc-sdm845.c
new file mode 100644
index 000
Hello Stephen,
On 8/24/2018 12:08 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-08 03:15:26)
On 8/8/2018 11:52 AM, Stephen Boyd wrote:
Binding describes hardware controllable by the OS. That's the reality.
Let's not add mandatory clock bindings for clocks that the O
Hello Matthias,
Thanks for your review comments.
On 8/29/2018 11:31 PM, Matthias Kaehlcke wrote:
Hi Taniya,
On Tue, Jul 24, 2018 at 04:12:50PM +0530, Taniya Das wrote:
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver
nue trying to pinpoint the source of the problem, but it
would be nice to know what tree you're testing against.
Regards,
Amit
[1]
https://git.linaro.org/people/amit.kucheria/kernel.git/log/?h=integration/qcomlt-automerge-result
On Tue, Jul 24, 2018 at 4:12 PM, Taniya Das wrote:
The CPUf
On 9/11/2018 1:00 AM, Matthias Kaehlcke wrote:
On Tue, Jul 24, 2018 at 04:12:50PM +0530, Taniya Das wrote:
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this hardware engine
ted_cpus and added to check for
cpu_mask_empty to return -ENOENT.
* Fixes qcom_cpu_resources_init function
* Remove initialization of 'index'
* Check for valid 'c'
* Removed initialization of 'prev_cc' from 'qcom_read_lut'.
Taniya Das (2):
dt-b
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this hardware engine.
Signed-off-by: Saravana Kannan
Signed-off-by: Taniya Das
---
drivers/cpufreq/Kconfig.arm | 11
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by the hardware engine.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 169 +++
port for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Taniya Das (2):
dt-bindings: clock: Introduce QCOM LPASS clock bindings
clk: qcom: Add lpass clock controller driver for
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt | 2 ++
.../devicetree/bindings/clock/qcom,lpasscc.txt | 31 ++
inclu
tree flag.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-sdm845.c | 35 +++
drivers/clk/qcom/lpasscc-sdm845.c | 195 ++
4 files changed, 240 insertions
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this firmware.
Signed-off-by: Saravana Kannan
Signed-off-by: Taniya Das
---
drivers/cpufreq/Kconfig.arm | 9 ++
drivers
[v2]
* Address comments given in v0 series.
[v1]
* Fixed compilation reported by Amit K.
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this firmware.
Taniya Das (2
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by firmware.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-fw.txt | 68 ++
1
Hello Viresh,
Sure, will do it next time. Hope updating the fixes in this email is
fine. Do let me know in case you need me to send it across again the
series with cover letter updated.
On 5/21/2018 11:35 AM, Viresh Kumar wrote:
On 19-05-18, 23:04, Taniya Das wrote:
[v2]
* Address
Hello Evan,
Thanks for the review comments.
On 3/30/2018 3:19 AM, Evan Green wrote:
Hi Taniya,
On Wed, Mar 28, 2018 at 11:19 PM Taniya Das wrote:
From: Amit Nischal
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs
for at least 1us before being de-asserted.
Signed-off-by: Taniya Das
Signed-off-by: Amit Nischal
---
drivers/clk/qcom/gdsc.c | 22 --
drivers/clk/qcom/gdsc.h | 4 +++-
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom
From: Amit Nischal
For some gdscs, it might take longer time up to 500us for
updating their status. So add support for the same by
defining a new flag 'GDS_TIMEOUT' to mark such gdsc in
order to poll their status for longer timeout value.
Signed-off-by: Amit Nischal
Signed-off-by:
This series implements the below logic for the GDSCs
1. logic to reset the AON logic before or assert/deassert the block
control reset removing the clamp io for few GDSCs on SDM845 SoC.
2. It also introduces the requirement to poll for higher timeout values
for few of the GDSCs.
3. There is
,
especially in the disable sequence, where the status bit
will be cleared even before the core is completely power
collapsed. On targets with this issue, poll the power on/off
bits in the CFG_GDSCR register instead to correctly determine
the GDSC state.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya
Thanks Stephen for the review comments.
On 4/16/2018 11:08 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-04-13 19:36:41)
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: David Collins
Signed-off-by: Amit
RPMh driver [1] and command DB
driver [2] which are both still undergoing review.
Thanks,
Taniya
[1]: https://lkml.org/lkml/2018/3/9/979
[2]: https://lkml.org/lkml/2018/3/14/787
Taniya Das (2):
dt-bindings: clock: Introduce QCOM RPMh clock bindings
clk: qcom: clk-rpmh: Add QCOM RPMh clock dr
Add RPMh clock device bindings for Qualcomm Technology Inc's SoCs. These
devices would be used for communicating resource state requests to control
the clocks managed by RPMh.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
Reviewed-by: Rob Herring
---
.../devicetree/bindings/clock
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c | 364
Hello Stephen,
I have tested the below patch & didn't see any issues.
On 5/2/2018 12:27 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-04-30 22:03:33)
@@ -45,15 +50,28 @@
#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
-static int gdsc_is_enabled(struct
Hello Stephen,
Thanks for review.
On 5/2/2018 9:00 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-05-02 03:51:17)
+ ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
+ if (ret) {
+ dev_err(&pdev->dev, "fail
both still undergoing review.
Thanks,
Taniya
[1]: https://lkml.org/lkml/2018/3/9/979
[2]: https://lkml.org/lkml/2018/3/14/787
Taniya Das (1):
clk: qcom: clk-rpmh: Add QCOM RPMh clock driver
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c |
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c | 368
send requests for the RPMh managed clock resources.
The RPMh clock driver depends upon the RPMh driver [1] and command DB
driver [2] which are both still undergoing review.
Thanks,
Taniya
[1]: https://lkml.org/lkml/2018/3/9/979
[2]: https://lkml.org/lkml/2018/3/14/787
Taniya Das (1):
clk: qcom: clk-
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c | 334
Yeah sure Stephen.
On 5/5/2018 8:21 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-05-03 02:09:57)
Hello Stephen,
I have tested the below patch & didn't see any issues.
Alright. Thanks! Can I take that as a "Tested-by"?
--
QUALCOMM INDIA, on behalf of Qualcomm Inn
Hello Bjorn,
Thanks for your review comments.
On 4/10/2018 4:28 AM, Bjorn Andersson wrote:
On Sun 08 Apr 03:32 PDT 2018, Taniya Das wrote:
From: Amit Nischal
Add RPMh clock device bindings for Qualcomm Technology Inc's SoCs. These
devices would be used for communicating resource
Hello Rob,
Thank you for the review comments.
On 4/13/2018 10:07 PM, Rob Herring wrote:
On Sun, Apr 08, 2018 at 04:02:12PM +0530, Taniya Das wrote:
From: Amit Nischal
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs
Hello Bjorn,
Thank you for the review comments.
On 4/10/2018 11:09 PM, Bjorn Andersson wrote:
On Sun 08 Apr 03:32 PDT 2018, Taniya Das wrote:
From: Amit Nischal
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed
Add RPMh clock device bindings for Qualcomm Technology Inc's SoCs. These
devices would be used for communicating resource state requests to control
the clocks managed by RPMh.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,rpmh-clk.txt
are both still undergoing review.
Thanks,
Taniya
[1]: https://lkml.org/lkml/2018/3/9/979
[2]: https://lkml.org/lkml/2018/3/14/787
Taniya Das (2):
dt-bindings: clock: Introduce QCOM RPMh clock bindings
clk: qcom: clk-rpmh: Add QCOM RPMh clock driver
.../devicetree/bindings/clock/qcom,
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: David Collins
Signed-off-by: Amit Nischal
---
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c | 367 ++
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c | 333
[2] which are both still undergoing review.
Thanks,
Taniya
[1]: https://lkml.org/lkml/2018/3/9/979
[2]: https://lkml.org/lkml/2018/3/14/787
Taniya Das (1):
clk: qcom: clk-rpmh: Add QCOM RPMh clock driver
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/q
Hello Stephen,
Could you please let me know your comments on the below.
On 5/4/2018 10:21 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-05-04 03:02:38)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
new file mode 100644
index 000..944fe04
--- /dev/null
+++ b
Hello Stephen,
Thanks for your review comments, please check my comments below, so
that I could submit the next patch series.
On 5/8/2018 5:58 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-05-07 03:48:06)
Hello Stephen,
Could you please let me know your comments on the below.
On 5/4
Thanks for the review.
On 5/27/2020 8:41 AM, Stephen Boyd wrote:
+ clocks:
+items:
+ - description: gcc_lpass_sway clock from GCC
+
+ clock-names:
+items:
+ - const: gcc_lpass_sway
As said on patch #4, maybe "iface" instead?
Will take care in the next patch.
+
+ powe
Thanks for your review.
On 5/29/2020 1:55 AM, Rob Herring wrote:
On Sun, May 17, 2020 at 02:52:22PM +0530, Taniya Das wrote:
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
properties that are needed in a device tree. Also add clock ids for GCC
LPASS and LPASS Core
Thanks for your review.
On 5/27/2020 8:40 AM, Stephen Boyd wrote:
Quoting Taniya Das (2020-05-17 02:22:24)
diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c
b/drivers/clk/qcom/lpasscorecc-sc7180.c
new file mode 100644
index 000..86e3599
--- /dev/null
+++ b/drivers/clk/qcom/lpasscorecc
Add the GCC lpass clock which is required to access the LPASS core
clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sc7180.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index ca4383e..8d3b161 100644
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