@vger.kernel.org; Suthikulpanit, Suravee
Subject: [PATCH V3] iommu/amd: Add logic to decode AMD IOMMU event flag
From: Suravee Suthikulpanit
Add logic to decode AMD IOMMU event flag based on information from AMD IOMMU
specification.
This should simplify debugging IOMMU errors. Also, dump DTE
Hi All,
Are there any other concerns about this patch series?
Thanks,
Suravee
On 8/26/2015 8:54 PM, Suravee Suthikulpanit wrote:
This patch adds support to setup DMA coherency for PCI device using
the ACPI _CCA attribute. According to the ACPI spec, the _CCA attribute
is required for ARM64. Th
n the UEFI
FW will soon remove this property.
Acked-by: Suravee Suthikulpanit
Suravee
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From: Wei Wang
There is a race condition when accessing kvm->arch.apic_access_page_done.
Due to it, x86_set_memory_region will fail when creating the second vcpu
for a svm guest.
Add a mutex_lock to serialize the accesses to apic_access_page_done.
This lock is also used by vmx for the same purpo
Boris,
On 6/18/2018 12:20 PM, Borislav Petkov wrote:
On Wed, Jun 13, 2018 at 01:43:10PM -0500, Suravee Suthikulpanit wrote:
The current logic incorrectly calculates the LLC ID from the APIC ID.
Unless specified otherwise, the LLC ID should be calculated from
the count order of the number of thr
Boris,
On 6/18/2018 1:23 PM, Borislav Petkov wrote:
On Mon, Jun 18, 2018 at 01:14:11PM -0500, Suthikulpanit, Suravee wrote:
This enumeration is only for the family17h model 00-1Fh of hardware
revision. The patch is intended for the future revision of hardware.
I realized that but the same
On 1/4/15, 04:55, "Hanjun Guo" wrote:
>Using the information presented by GTDT to initialize the arch
>timer (not memory-mapped).
>
>Originally-by: Amit Daniel Kachhap
>Tested-by: Suravee Suthikulpanit
>Signed-off-by: Hanjun Guo
>---
> arch/arm64/kernel/time.c | 7 ++
> drivers/cl
Mika/Rafael,
If there are no other concerns about this patch series, do you think this
ready to be pushed to linux-next tree along with the rest of the ARM64
ACPI patch series from Linaro?
Thanks,
Suravee
On 4/6/15, 10:45, "Suravee Suthikulanit"
wrote:
>Ping.
>
>Are there any other concerns
On 4/24/15, 21:28, "Rafael J. Wysocki" wrote:
>On Friday, April 24, 2015 04:08:31 PM Suravee Suthikulpanit wrote:
>> On 4/16/15 20:45, Zheng, Lv wrote:
>> > Before back porting this to ACPICA, let me ask one simple question.
>> > According to the spec, the _CLS is optional and PCI specific.
>> >
On 4/29/15, 09:47, "Arnd Bergmann" wrote:
>On Wednesday 29 April 2015 09:45:43 Suravee Suthikulpanit wrote:
>> On 04/29/2015 09:03 AM, Arnd Bergmann wrote:
>> > On Wednesday 29 April 2015 08:44:09 Suravee Suthikulpanit wrote:
>> >> + device->flags.cca_seen = 1;
>> >> +
Oren,
On 3/11/19 6:38 PM, Suthikulpanit, Suravee wrote:
> However, looking a bit more closely, I notice the logic in
> svm_deliver_avic_intr()
> should also have been changed from kvm_vcpu_wake_up() to kvm_vcpu_kick()
> since the latter will result in clearing the IRR bit for th
Oren
On 3/13/19 8:05 PM, Oren Twaig wrote:
> Hi Suravee,
>
> Turns out, the _same_ bug was already discussed in the past by
> yourself, Paolo and Radim (both now 'cc'-ed)
>
> Please read it here:
> https://patchwork.kernel.org/patch/8292231/
>
>
> After reading that thread, I have couple of qu
Alex,
On 2/6/19 1:34 AM, Alex Williamson wrote:
> On Mon, 4 Feb 2019 14:42:32 +
> "Suthikulpanit, Suravee" wrote:
>
>> Once the IRQ ack notifier for in-kernel PIT is no longer required
>> and run-time AVIC activate/deactivate is supported, we can remove
&
Ping
On 3/20/19 3:12 PM, Suthikulpanit, Suravee wrote:
> This reverts commit bb218fbcfaaa3b115d4cd7a43c0ca164f3a96e57.
>
> As Oren Twaig pointed out the old discussion:
>
>https://patchwork.kernel.org/patch/8292231/
>
> that the change coud potentially cause an ex
Ping
On 3/26/19 10:57 AM, Suthikulpanit, Suravee wrote:
> Only clear the valid bit when invalidate logical APIC id entry.
> The current logic clear the valid bit, but also set the rest of
> the bits (including reserved bits) to 1.
>
> Fixes: 98d90582be2e ('svm: Fix AVIC
David,
On 4/14/2021 10:33 PM, David Coe wrote:
Hi Suravee!
I've re-run your revert+update patch on Ubuntu's latest kernel 5.11.0-14 partly
to check my mailer's 'mangling' hadn't also reached the code!
There are 3 sets of results in the attachment, all for the Ryzen 2400G. The
as-distributed
Shuah,
On 4/10/2021 12:06 AM, Shuah Khan wrote:
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 321f5906e6ed..648cdfd03074 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -1729,39 +1728,17 @@ static void __init init_iommu_perf_ctr(struct amd_io
On 4/10/2021 5:03 PM, David Coe wrote:
Results for AMD Ryzen 4700U running Ubuntu 21.04β kernel 5.11.0-13
$ sudo dmesg | grep IOMMU
[ 0.490352] pci :00:00.2: AMD-Vi: IOMMU performance counters supported
[ 0.491985] pci :00:00.2: AMD-Vi: Found IOMMU cap 0x40
[ 0.493732] perf/a
David / Joerg,
On 4/10/2021 5:03 PM, David Coe wrote:
The immediately obvious difference is the with the enormous count seen on
mem_dte_mis on the older Ryzen 2400G. Will do some RTFM but anyone with
comments and insight?
841,689,151,202,939 amd_iommu_0/mem_dte_mis/ (33.44
AM
To: Suthikulpanit, Suravee
Cc: Mark Rutland; ja...@lakedaemon.net; Pawel Moll; Catalin Marinas; Will
Deacon; t...@linutronix.de; Kasiviswanathan, Harish;
linux-arm-ker...@lists.infradead.org; linux-...@vger.kernel.org;
linux-kernel@vger.kernel.org; linux-...@vger.kernel.org;
devicet
Hi Bjorn,
On 8/25/2015 3:14 AM, Bjorn Helgaas wrote:
On Mon, Aug 24, 2015 at 12:09 PM, Suravee Suthikulpanit
wrote:
commit 84cfb2213cd400fef227ec0d7829ec4e12895da9
Author: Bjorn Helgaas
Date: Thu Aug 13 19:49:52 2015 -0500
ACPI / scan: Rename acpi_check_dma() to acpi_dma_is_coherent
Hi Rafael,
On 9/10/2015 3:38 AM, Rafael J. Wysocki wrote:
On Wednesday, September 09, 2015 07:16:49 PM Suthikulpanit, Suravee wrote:
>Hi All,
>
>Are there any other concerns about this patch series?
I have none, but then it sort of missed the merge window.
I can easily queue it u
On 11/13/14 18:29, Arnd Bergmann wrote:
> On Tuesday 28 October 2014 08:36:54 suravee.suthikulpa...@amd.com wrote:
>> From: Suravee Suthikulpanit
>>
>> Initial revision of device tree for AMD Seattle platform
>
> Sorry for not looking at this earlier in enough detail.
>
>> +dma0: dma@050 {
On 11/28/14, 22:13, "Arnd Bergmann" wrote:
>On Wednesday 26 November 2014, suravee.suthikulpa...@amd.com wrote:
>> From: Suravee Suthikulpanit
>>
>> Initial revision of device tree for AMD Seattle Development platform.
>>
>> Cc: Arnd Bergmann
>> Cc: Marc Zyngier
>> Cc: Mark Rutland
>> Cc:
On 11/21/14, 19:57, "Marc Zyngier" wrote:
>>+ gic: interrupt-controller@e1101000 {
>>+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
>>+ interrupt-controller;
>>+ #interrupt-cells = <3>;
>>+ #address-cells = <2>;
>>+ #size-cell
On 11/21/14, 21:48, "Marc Zyngier" wrote:
>On 21/11/14 14:40, Suthikulpanit, Suravee wrote:
>>
>>
>> On 11/21/14, 19:57, "Marc Zyngier" wrote:
>>
>>>> + gic: interrupt-controller@e1101000 {
>>>> + comp
Hi Olof,
On 11/25/14, 06:09, "Olof Johansson" wrote:
>Hi Suravee,
>
>Some comments below.
>
>
>On Mon, Nov 24, 2014 at 1:51 PM, wrote:
>> From: Suravee Suthikulpanit
>>
>>[...]
>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
>> index f8001a6..604af09 100644
>> ---
Hi Marc,
On 11/25/14, 17:23, "Marc Zyngier" wrote:
>Hi Suravee,
>
>Just spotted a small issue below (looks like a recurring mistake in a
>number of DTs I've seem lately):
>
>On 24/11/14 21:51, suravee.suthikulpa...@amd.com wrote:
>> From: Suravee Suthikulpanit
>>
>> Initial revision of device
On 11/25/14, 18:57, "Arnd Bergmann" wrote:
>On Monday 24 November 2014 15:51:17 suravee.suthikulpa...@amd.com wrote:
>>
>> +gic: interrupt-controller@e1101000 {
>> +compatible = "arm,gic-400", "arm,cortex-a15-gic";
>> +interrupt-controller;
>> +#interrup
Hi Arnd,
On 12/1/14, 20:33, "Arnd Bergmann" wrote:
>On Sunday 30 November 2014 21:46:39 suravee.suthikulpa...@amd.com wrote:
>> From: Suravee Suthikulpanit
>>
>> AMD Seattle should support 40-bit DMA.
>>
>> Signed-off-by: Suravee Suthikulpanit
>>
>
>The change looks good, but two things abo
Hi Rafael,
On 5/15/15, 18:59, "Rafael J. Wysocki" wrote:
>On Friday, May 15, 2015 04:23:11 PM Suravee Suthikulpanit wrote:
>> This patch refactors of_pci_dma_configure() into a more generic
>> pci_dma_configure(), which can be reused by non-OF code.
>> Then, it adds support for setting up PCI de
Hi Bjorn,
On 5/16/15, 07:41, "Bjorn Helgaas" wrote:
>On Fri, May 15, 2015 at 4:23 PM, Suravee Suthikulpanit
> wrote:
>> This patch refactors of_pci_dma_configure() into a more generic
>> pci_dma_configure(), which can be reused by non-OF code.
>> Then, it adds support for setting up PCI device D
On 3/12/15, 08:26, "Timur Tabi" wrote:
>Hanjun Guo wrote:
>> This patch set already tested on multi platforms:
>> - AMD Seattle board;
>> - Cavium Thunder board;
>> - Huawei D02 board;
>> - Qualcomm ARM64 platform
>>
>> This version 10 patch set address some minor comments and collect A
On 2/9/15, 19:15, "Mika Westerberg"
wrote:
>On Mon, Feb 09, 2015 at 12:02:43AM +0100, Rafael J. Wysocki wrote:
>> On Monday, February 09, 2015 12:20:03 AM Suravee Suthikulpanit wrote:
>> > Device drivers typically use ACPI _HIDs/_CIDs listed in struct
>>device_driver
>> > acpi_match_table to matc
On 2/10/15, 23:07, "Rafael J. Wysocki" wrote:
>On Tuesday, February 10, 2015 11:59:32 AM Mika Westerberg wrote:
>> On Mon, Feb 09, 2015 at 09:02:11PM +0000, Suthikulpanit, Suravee wrote:
>> > On 2/9/15, 19:15, "Mika Westerberg"
>> > wrote:
>&
On 3/2/15, 10:41, "Tejun Heo" wrote:
>On Mon, Mar 02, 2015 at 02:27:20AM -0600, Suravee Suthikulpanit wrote:
>> This patch adds ACPI supports for AHCI platform driver, which uses _CLS
>> method to match the device.
>>
>> The following is an example of ASL structure in DSDT for a SATA
>>control
This reverts commit bb218fbcfaaa3b115d4cd7a43c0ca164f3a96e57.
As Oren Twaig pointed out the old discussion:
https://patchwork.kernel.org/patch/8292231/
that the change coud potentially cause an extra IPI to be sent to
the destination vcpu because the AVIC hardware already set the IRR bit
befor
Alex,
On 8/19/19 6:00 AM, Alexander Graf wrote:
>
>
> On 15.08.19 18:25, Suthikulpanit, Suravee wrote:
>> In-kernel IOAPIC does not update RTC pending EOI info with AMD SVM /w
>> AVIC
>> when interrupt is delivered as edge-triggered since AMD processors
>
The 'commit 67034bb9dd5e ("KVM: SVM: Add irqchip_split() checks before
enabling AVIC")' was introduced to fix miscellaneous boot-hang issues
when enable AVIC. This is mainly due to AVIC hardware doest not #vmexit
on write to LAPIC EOI register resulting in-kernel PIC and IOAPIC to
wait and do not i
Generally, APICv for all vcpus in the VM are enable/disable in the same
manner. So, get_enable_apicv() should represent APICv status of the VM
instead of each VCPU.
Modify kvm_x86_ops.get_enable_apicv() to take struct kvm as parameter
instead of struct kvm_vcpu.
Signed-off-by: Suravee Suthikulpan
Introduce per-VM debugfs for providing per-VM debug information.
Signed-off-by: Suravee Suthikulpanit
---
arch/mips/kvm/mips.c | 5 +
arch/powerpc/kvm/powerpc.c | 5 +
arch/s390/kvm/kvm-s390.c | 5 +
arch/x86/kvm/debugfs.c | 5 +
include/linux/kvm_host.h | 1 +
virt
Introduce interface for activate/deactivate posted interrupts, and
implement SVM hooks to toggle AMD IOMMU guest virtual APIC mode.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/include/asm/kvm_host.h | 4
arch/x86/kvm/svm.c | 44 +
Currently, there is no way to tell whether APICv is active
on a particular VM. This often cause confusion since APICv
can be deactivated at runtime.
Introduce a debugfs entry to report APICv state of a VM.
This creates a read-only file:
/sys/kernel/debug/kvm/70860-14/apicv-state
Signed-off-by
ACK notifiers don't work with AMD SVM w/ AVIC when the PIT interrupt
is delivered as edge-triggered fixed interrupt since AMD processors
cannot exit on EOI for these interrupts.
Add code to check LAPIC pending EOI before injecting any pending PIT
interrupt on AMD SVM when AVIC is activated.
Signe
Certain runtime conditions require APICv to be temporary deactivated.
However, current implementation only support permanently deactivate
APICv at runtime (mainly used when running Hyper-V guest).
In addtion, for AMD, when activate / deactivate APICv during runtime,
all vcpus in the VM has to be o
Activate/deactivate AVIC requires setting/unsetting the memory region used
for virtual APIC backing page (APIC_ACCESS_PAGE_PRIVATE_MEMSLOT).
So, re-factor avic_init_access_page() to avic_setup_access_page()
and add srcu_read_lock/unlock, which are needed to allow this function
to be called during r
Re-factor code into a helper function for setting lapic parameters when
activate/deactivate APICv, and export the function for subsequent usage.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/lapic.c | 22 +-
arch/x86/kvm/lapic.h | 1 +
2 files changed, 18 insertions(
Since disabling APICv has to be done for all vcpus on AMD-based system,
adopt the newly introduced kvm_make_apicv_deactivate_request() intereface.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/hyperv.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch
AMD AVIC does not support ExtINT. Therefore, AVIC must be temporary
deactivated and fall back to using legacy interrupt injection via vINTR
and interrupt window.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/svm.c | 49 +
1 file changed, 45
Once run-time AVIC activate/deactivate, and PIC and IOAPIC EOI workaround
for AVIC is supported, we can remove the kernel irqchip split mode
requirement for AVIC.
Hence, remove the check for irqchip split mode when enabling AVIC.
Cc: Radim Krčmář
Cc: Paolo Bonzini
Signed-off-by: Suravee Suthiku
Move these duplicated predefined macros to the header file so that
it can be re-used in other places.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/lapic.c | 13 +
arch/x86/kvm/lapic.h | 1 +
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kvm/lapic.c
In-kernel IOAPIC does not update RTC pending EOI info with AMD SVM /w AVIC
when interrupt is delivered as edge-triggered since AMD processors
cannot exit on EOI for these interrupts.
Add code to also check LAPIC pending EOI before injecting any new RTC
interrupts on AMD SVM when AVIC is activated.
Add necessary logics for supporting activate/deactivate AVIC at runtime.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/svm.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 47f2439..cfa4b13 100
Currently, after a VM boots with APICv enabled, it could go into
the following states:
* activated = VM is running w/ APICv
* deactivated = VM deactivate APICv (temporary)
* disabled= VM deactivate APICv (permanent)
Introduce KVM APICv state enum to help keep track of the APICv states
Alex,
On 8/19/19 5:35 AM, Alexander Graf wrote:
>
>
> On 15.08.19 18:25, Suthikulpanit, Suravee wrote:
>> AMD AVIC does not support ExtINT. Therefore, AVIC must be temporary
>> deactivated and fall back to using legacy interrupt injection via vINTR
>> and interrupt
Alex,
On 8/27/19 3:20 AM, Alexander Graf wrote:
>
>
> On 26.08.19 21:41, Suthikulpanit, Suravee wrote:
>> Alex,
>>
>> On 8/19/2019 4:57 AM, Alexander Graf wrote:
>>>
>>>
>>> On 15.08.19 18:25, Suthikulpanit, Suravee wrote:
>>>>
Alex,
On 8/19/2019 4:49 AM, Alexander Graf wrote:
>
>
> On 15.08.19 18:25, Suthikulpanit, Suravee wrote:
>> Currently, after a VM boots with APICv enabled, it could go into
>> the following states:
>> * activated = VM is running w/ APICv
>> * deactivated
Alex,
On 8/19/2019 4:57 AM, Alexander Graf wrote:
>
>
> On 15.08.19 18:25, Suthikulpanit, Suravee wrote:
>> Currently, there is no way to tell whether APICv is active
>> on a particular VM. This often cause confusion since APICv
>> can be deactivated at runtime.
>
Alex,
On 8/19/2019 5:42 AM, Alexander Graf wrote:
>
>
> On 15.08.19 18:25, Suthikulpanit, Suravee wrote:
>> ACK notifiers don't work with AMD SVM w/ AVIC when the PIT interrupt
>> is delivered as edge-triggered fixed interrupt since AMD processors
>> cannot
Alex,
On 8/28/19 2:37 PM, Graf (AWS), Alexander wrote:
@@ -5522,9 +5558,6 @@ static void enable_irq_window(struct kvm_vcpu
*vcpu)
{
struct vcpu_svm *svm = to_svm(vcpu);
-if (kvm_vcpu_apicv_active(vcpu))
-return;
-
/*
Alex,
On 8/27/19 4:10 AM, Alexander Graf wrote:
>
> On 26.08.19 22:46, Suthikulpanit, Suravee wrote:
>> Alex,
>>
>> On 8/19/2019 5:42 AM, Alexander Graf wrote:
>>>
>>>
>>> On 15.08.19 18:25, Suthikulpanit, Suravee wrote:
>>>> ACK n
Generally, APICv for all vcpus in the VM are enable/disable in the same
manner. So, get_enable_apicv() should represent APICv status of the VM
instead of each VCPU.
Modify kvm_x86_ops.get_enable_apicv() to take struct kvm as parameter
instead of struct kvm_vcpu.
Reviewed-by: Vitaly Kuznetsov
Sig
Add trace points when sending request to activate/deactivate APICv.
Suggested-by: Alexander Graf
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/trace.h | 30 ++
arch/x86/kvm/x86.c | 7 +++
2 files changed, 37 insertions(+)
diff --git a/arch/x86/kvm/tra
The 'commit 67034bb9dd5e ("KVM: SVM: Add irqchip_split() checks before
enabling AVIC")' was introduced to fix miscellaneous boot-hang issues
when enable AVIC. This is mainly due to AVIC hardware doest not #vmexit
on write to LAPIC EOI register resulting in-kernel PIC and IOAPIC to
wait and do not i
Add necessary logics for supporting activate/deactivate AVIC at runtime.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/svm.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 2e06ee2..a01bc6a 100
Currently, after a VM boots with APICv enabled, it could go into
the following states:
* activated = VM is running w/ APICv
* suspended = VM deactivate APICv temporarily
* disabled = VM deactivate APICv permanently
Introduce KVM APICv state enum to help keep track of the APICv states
along
AMD SVM AVIC accelerates write access to APIC EOI register for edge-trigger
interrupts, and does not trap. This breaks in-kernel irqchip, which expects
the EOI trap to send notifier for acked irq.
Introduce struct kvm_x86_ops.apicv_eoi_accelerate to allow check
for such behavior.
Signed-off-by: S
Re-factor code into a helper function for setting lapic parameters when
activate/deactivate APICv, and export the function for subsequent usage.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/lapic.c | 22 +-
arch/x86/kvm/lapic.h | 1 +
2 files changed, 18 insertions(
Move these duplicated predefined macros to the header file so that
it can be re-used in other places.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/lapic.c | 13 +
arch/x86/kvm/lapic.h | 1 +
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kvm/lapic.c
Activate/deactivate AVIC requires setting/unsetting the memory region used
for virtual APIC backing page (APIC_ACCESS_PAGE_PRIVATE_MEMSLOT).
So, re-factor avic_init_access_page() to avic_setup_access_page()
and add srcu_read_lock/unlock, which are needed to allow this function
to be called during r
Refactor code for handling IOAPIC EOI for subsequent patch.
There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/ioapic.c | 110 +-
1 file changed, 56 insertions(+), 54 deletions(-)
diff --git a/arch/x86/kvm/ioapic.
Since disabling APICv has to be done for all vcpus on AMD-based system,
adopt the newly introduced kvm_make_apicv_deactivate_request() interface.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/hyperv.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/
In-kernel IOAPIC does not receive EOI with AMD SVM AVIC
since the processor accelerate write to APIC EOI register and
does not trap if the interrupt is edge-triggered.
Workaround this by lazy check for pending APIC EOI at the time when
setting new IOPIC irq, and update IOAPIC EOI if no pending API
Since AVIC does not currently work w/ nested virtualization, disable AVIC
for the guest if setting CPUID Fn8001_ECX[SVM] (i.e. indicate support
for SVM, which is needed for nested virtualization).
Suggested-by: Alexander Graf
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/svm.c | 10
AMD AVIC does not support ExtINT. Therefore, AVIC must be temporary
deactivated and fall back to using legacy interrupt injection via vINTR
and interrupt window.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/svm.c | 50 ++
1 file changed, 4
Certain runtime conditions require APICv to be temporary deactivated.
However, current implementation only support permanently deactivate
APICv at runtime (mainly used when running Hyper-V guest).
In addition, for AMD, when activate / deactivate APICv during runtime,
all vcpus in the VM has to be
Once run-time AVIC activate/deactivate is supported, and EOI workaround
for AVIC is implemented, we can remove the kernel irqchip split mode
requirement for AVIC.
Hence, remove the check for irqchip split mode when enabling AVIC.
Cc: Radim Krčmář
Cc: Paolo Bonzini
Signed-off-by: Suravee Suthiku
Introduce interface for activate/deactivate posted interrupts, and
implement SVM hooks to toggle AMD IOMMU guest virtual APIC mode.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/include/asm/kvm_host.h | 4
arch/x86/kvm/svm.c | 44 +
Ping:
Hi All,
Are there other concerns or suggestions for this series?
Thanks,
Suravee
On 9/13/19 2:00 PM, Suthikulpanit, Suravee wrote:
> The 'commit 67034bb9dd5e ("KVM: SVM: Add irqchip_split() checks before
> enabling AVIC")' was introduced to fix miscellaneo
Hi,
On 10/9/19 2:25 PM, Jiri Kosina wrote:
> On Fri, 27 Sep 2019, Shah, Nehal-bakulchandra wrote:
>
> Do you have BAR memory allocation failures in dmesg with IOMMU on?
>>>
>>> No. The device is *not* treated as PCI device and I still think that
>>> this is the source of the evil.
>>>
> A
Jan,
On 5/8/2019 5:27 PM, Jan H. Schönherr wrote:
> On 22/03/2019 12.57, Suthikulpanit, Suravee wrote:
>> Introduce a helper function for setting lapic parameters when
>> activate/deactivate apicv.
>>
>> Signed-off-by: Suravee Suthikulpanit
>> -
Paolo,
On 7/3/2019 4:16 PM, Paolo Bonzini wrote:
> On 22/03/19 12:57, Suthikulpanit, Suravee wrote:
>> Add hooks for handling the case when guest VM update APIC ID, DFR and LDR.
>> This is needed during AMD AVIC is temporary deactivated.
>>
>> Signed-off-by: Suravee
From: Suravee Suthikulpanit
Print warning message when IPI target ID is invalid due to one of
the following reasons:
* In logical mode: cluster > max_cluster (64)
* In physical mode: target > max_physical (512)
* Address is not present in the physical or logical ID tables
Signed-off-by: Su
From: Suravee Suthikulpanit
In case of incomplete IPI with invalid interrupt type, the current
SVM driver does not properly emulate the IPI, and fails to boot
FreeBSD guests with multiple vcpus when enabling AVIC.
Fix this by update APIC ICR high/low registers, which also
emulate sending the IPI
Joerg,
On 1/22/19 5:44 PM, j...@8bytes.org wrote:
> Hi Suravee,
>
> On Thu, Jan 17, 2019 at 08:44:36AM +, Suthikulpanit, Suravee wrote:
>> Then, in __domain_flush_pages, we issue command when the dev_iommu[] >= 0.
>> This should preserve previous behavior, and only a
Current SVM AVIC driver makes two incorrect assumptions:
1. APIC LDR register cannot be zero
2. APIC DFR for all vCPUs must be the same
LDR=0 means the local APIC does not support logical destination mode.
Therefore, the driver should mark any previously assigned logical APIC ID
table entry as
The function svm_refresh_apicv_exec_ctrl() always returning prematurely
as kvm_vcpu_apicv_active() always return false when calling from
the function arch/x86/kvm/x86.c:kvm_vcpu_deactivate_apicv().
This is because the apicv_active is set to false just before calling
refresh_apicv_exec_ctrl().
Also
From: Suravee Suthikulpanit
When a device switches domain, IOMMU driver detach device from the old
domain, and attach device to the new domain. During this period
the host table root pointer is not set, which means DMA translation
should be marked as invalid (clear TV bit).
So, clear the TV bit
From: Suravee Suthikulpanit
When a VM is terminated, the VFIO driver detaches all pass-through
devices from VFIO domain by clearing domain id and page table root
pointer from each device table entry (DTE), and then invalidates
the DTE. Then, the VFIO driver unmap pages and invalidate IOMMU pages.
Joerg,
On 1/16/19 8:26 PM, j...@8bytes.org wrote:
> On Wed, Jan 16, 2019 at 04:16:25AM +0000, Suthikulpanit, Suravee wrote:
>> diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
>> index 525659b88ade..ab31ba75da1b 100644
>> --- a/drivers/iommu/amd_iommu.c
&
Joerg,
On 1/16/19 8:03 PM, j...@8bytes.org wrote:
> Hi Suravee,
>
> On Wed, Jan 16, 2019 at 04:15:10AM +, Suthikulpanit, Suravee wrote:
>> From: Suravee Suthikulpanit
>>
>> When a device switches domain, IOMMU driver detach device from the old
>> domain, an
Joerg,
On 1/16/19 8:26 PM, j...@8bytes.org wrote:
> How about the attached diff? If
> I understand the problem correctly, it should fix the problem more
> reliably.
>
> Thanks,
>
> Joerg
>
> diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
> index 87ba23a75b38..dc1e2a8a1
Joerg,
On 1/17/19 12:08 AM, j...@8bytes.org wrote:
> On Wed, Jan 16, 2019 at 02:08:55PM +0000, Suthikulpanit, Suravee wrote:
>> Actually, I am not sure how we would be missing the flush on the last device.
>> In my test, I am seeing the flush command being issued c
From: Suravee Suthikulpanit
When a VM is terminated, the VFIO driver detaches all pass-through
devices from VFIO domain by clearing domain id and page table root
pointer from each device table entry (DTE), and then invalidates
the DTE. Then, the VFIO driver unmap pages and invalidate IOMMU pages.
Joerg,
On 1/17/19 3:44 PM, Suravee Suthikulpanit wrote:
> Joerg,
>
> On 1/17/19 12:08 AM, j...@8bytes.org wrote:
>> On Wed, Jan 16, 2019 at 02:08:55PM +, Suthikulpanit, Suravee wrote:
>>> Actually, I am not sure how we would be missing the flush on the last
>>
Paolo,
On 1/30/19 11:22 PM, Paolo Bonzini wrote:
> On 29/01/19 09:09, Suthikulpanit, Suravee wrote:
>> The function svm_refresh_apicv_exec_ctrl() always returning prematurely
>> as kvm_vcpu_apicv_active() always return false when calling from
>> the func
Currently, AMD AVIC can only be enabled when creating VM in irqchip
split mode, which is due to the following issues:
* AMD AVIC does not support ExtINT, which is required during booting
phase of Windows and FreeBSD VMs. This results in hanging in the
boot loaders.
* Untrap APIC E
During AVIC temporary deactivation, guest could update APIC ID,
DFR and LDR registers, which would not be trapped by
avic_unaccelerated_ccess_interception(). In this case, we need
to update the AVIC logical APIC ID table accordingly.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kvm/svm.c |
Activate/deactivate AVIC requires setting/unsetting the memory region used
for APIC_ACCESS_PAGE_PRIVATE_MEMSLOT. So, re-factor avic_init_access_page()
to avic_setup_access_page() and add srcu_read_lock/unlock, which are needed
to allow this function to be called during run-time.
Also, introduce av
The function svm_refresh_apicv_exec_ctrl() always returning prematurely
as kvm_vcpu_apicv_active() always return false when calling from
the function arch/x86/kvm/x86.c:kvm_vcpu_deactivate_apicv().
This is because the apicv_active is set to false just before calling
refresh_apicv_exec_ctrl().
Also
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