EL into
a generic header file. But the alternative would be to use a weak()
function in core.c which is not nicer, in my opinion.
Acked-by: Stephane Eranian
> ---
> include/linux/perf_event.h | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/include/linu
function should return false because obviously nothing can be written in
the buffer.
Signed-off-by: Stephane Eranian
---
diff --git a/kernel/events/ring_buffer.c b/kernel/events/ring_buffer.c
index 23cb34f..73147b9 100644
--- a/kernel/events/ring_buffer.c
+++ b/kernel/events/ring_buffer.c
@@ -18,1
On Mon, Mar 18, 2013 at 1:59 PM, Peter Zijlstra wrote:
> On Mon, 2013-03-18 at 13:48 +0100, Stephane Eranian wrote:
>> if (!rb->writable)
>> - return true;
>> + return false;
>
>
> writable means user writable (VM_WRITE); the
On Mon, Mar 18, 2013 at 2:11 PM, Peter Zijlstra wrote:
> On Mon, 2013-03-18 at 14:03 +0100, Stephane Eranian wrote:
>> On Mon, Mar 18, 2013 at 1:59 PM, Peter Zijlstra wrote:
>> > On Mon, 2013-03-18 at 13:48 +0100, Stephane Eranian wrote:
>> >
it to rb->overwrite because it tells whether or not the
buffer can overwrite its tail (suggested by PeterZ).
Signed-off-by: Stephane Eranian
---
diff --git a/kernel/events/internal.h b/kernel/events/internal.h
index d56a64c..eb675c4 100644
--- a/kernel/events/internal.h
+++ b/kernel/events/internal
on context-switch or when the associated
event is disabled. And there we do not have a pt_regs handy.
Setting pt_regs to all zeroes may not be the best option but it is
not clear what else to do given where the drain_bts_buffer() is called
from.
Signed-off-by: Stephane Eranian
---
diff --git a
On Mon, Mar 18, 2013 at 10:06 PM, Greg Kroah-Hartman
wrote:
> 3.8-stable review patch. If anyone has any objections, please let me know.
>
Greg, you also need to pick David Rientjes patch to fix compilation on
non X86 architectures.
Thanks.
> --
>
> From: S
On Mon, Mar 18, 2013 at 10:20 PM, Greg Kroah-Hartman
wrote:
> On Mon, Mar 18, 2013 at 10:11:28PM +0100, Stephane Eranian wrote:
>> On Mon, Mar 18, 2013 at 10:06 PM, Greg Kroah-Hartman
>> wrote:
>> > 3.8-stable review patch. If anyone has any objections, please let me
On Tue, Mar 19, 2013 at 1:43 PM, Peter Zijlstra wrote:
> On Mon, 2013-03-18 at 14:46 +0100, Stephane Eranian wrote:
>>
>> This patch fixes an uninitialized pt_regs struct in drain BTS
>> function. The pt_regs struct is propagated all the way to the
>> code_
On Tue, Mar 19, 2013 at 1:58 PM, Peter Zijlstra wrote:
> On Tue, 2013-03-19 at 13:50 +0100, Stephane Eranian wrote:
>> > Should we not replace:
>> >
>> > regs.ip = 0;
>> >
>> > with that memset? It avoids the memset work in a few cases a
avoid doing it when
we end up returning early without doing the actual BTS processing.
Also dropped the reg.val initialization because it is redundant with
the memset() as suggested by PeterZ.
Signed-off-by: Stephane Eranian
---
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c
b/arch/x86
On Tue, Jan 29, 2013 at 9:03 AM, Ingo Molnar wrote:
>
> * Stephane Eranian wrote:
>
>> On Mon, Jan 28, 2013 at 9:52 PM, Stephane Eranian wrote:
>> > Jiri,
>> >
>> > I don't see part 0/8 of this series. Did you send it to me too?
>> >
&g
On Fri, Jan 25, 2013 at 11:38 AM, Ingo Molnar wrote:
>
> * Stephane Eranian wrote:
>
>> This patch series had a new feature to the kernel perf_events
>> interface and corresponding user level tool, perf.
>
> Ok, so I have created a topic tree for this, tip:perf/x86.
&g
On Tue, Feb 5, 2013 at 2:49 AM, Andi Kleen wrote:
> From: Andi Kleen
>
> Recent Intel CPUs have a new alternative MSR range for perfctrs that allows
> writing the full counter width. Enable this range if the hardware reports it
> using a new capability bit. This lowers overhead of perf stat sligh
On Fri, Feb 1, 2013 at 3:18 PM, Pawel Moll wrote:
> Hello,
>
> I'd like to revive the topic...
>
> On Tue, 2012-10-16 at 18:23 +0100, Peter Zijlstra wrote:
>> On Tue, 2012-10-16 at 12:13 +0200, Stephane Eranian wrote:
>> > Hi,
>> >
>> > There
value. On Haswell it also avoids some
> problems with TSX aborting when the end of the counter range is reached.
>
> v2: Print the feature at boot
Tested okay for me.
Reviewed-by: Stephane Eranian
> Signed-off-by: Andi Kleen
>
> diff --git a/arch/x86/include/uapi/asm/msr-index.h
5,788,785 cycles
2.000379943 S04 27,361,546 cycles
2.001167808 S04818,275 cycles
Signed-off-by: Stephane Eranian
Stephane Eranian (2):
perf tools: add cpu_map processor socket level functions
perf stat: add per processor socket count aggregation
2.001167808 S04818,275 cycles
Signed-off-by: Stephane Eranian
---
tools/perf/builtin-stat.c | 126 +
1 file changed, 115 insertions(+), 11 deletions(-)
diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c
index
This patch adds:
- cpu_map__get_socket: get socked id from cpu
- cpu_map__build_socket_map: build socket map
- cpu_map__socket: gets acutal socket from logical socket
Those functions are used by uncore and processor socket-level
aggregation modes.
Signed-off-by: Stephane Eranian
---
tools/perf
On Wed, Feb 6, 2013 at 8:51 PM, Arnaldo Carvalho de Melo
wrote:
> Em Wed, Feb 06, 2013 at 03:46:02PM +0100, Stephane Eranian escreveu:
>> tools/perf/builtin-stat.c | 126
>> +
>
> Added the missing 'perf stat' man pa
On Thu, Feb 7, 2013 at 3:31 AM, Namhyung Kim wrote:
> Hi Stephane,
>
> On Wed, 6 Feb 2013 15:46:00 +0100, Stephane Eranian wrote:
>> This patch adds per-processor socket count aggregation
>> for system-wide mode measurements. This is a useful
>> mode to detect im
On Thu, Feb 7, 2013 at 6:57 PM, Jacob Shin wrote:
> On Wed, Feb 06, 2013 at 11:26:29AM -0600, Jacob Shin wrote:
>> On AMD family 15h processors, there are 4 new performance counters
>> (in addition to 6 core performance counters) that can be used for
>> counting northbridge events (i.e. DRAM acces
On Wed, Feb 6, 2013 at 6:31 PM, Jacob Shin wrote:
> On Wed, Feb 06, 2013 at 11:26:23AM -0600, Jacob Shin wrote:
>> The following patchset enables 4 additional performance counters in
>> AMD family 15h processors that count northbridge events -- such as
>> number of DRAM accesses.
>>
>
> Here is th
on. For instance, now if the core
PMU is overcommitted, but not the uncore, then uncore still goes
thru event rescheduling for nothing.
But what matters at this point, is that there is coverage
for uncore, so we can get some bandwidth measurements
out. So i recommend we merge this in. Thanks.
Ac
see that the load
is evenly balanced across all 4 physical core (HT is on).
Signed-off-by: Stephane Eranian
-
Stephane Eranian (2):
perf stat: refactor aggregation code
perf stat: add per-core aggregation
tools/perf/Documentation/perf-stat.txt |6 +
tools/perf/builtin-stat.c
in increasing order.
Signed-off-by: Stephane Eranian
---
tools/perf/builtin-stat.c | 208 ++---
tools/perf/util/cpumap.c | 40 ++---
2 files changed, 148 insertions(+), 100 deletions(-)
diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-sta
1.90030 S0-C3 1266,092 cycles
Signed-off-by: Stephane Eranian
---
tools/perf/Documentation/perf-stat.txt |6 +
tools/perf/builtin-stat.c | 37 -
tools/perf/util/cpumap.c | 46
On Tue, Feb 12, 2013 at 6:23 PM, Andi Kleen wrote:
> On Tue, Feb 12, 2013 at 03:09:26PM +0100, Stephane Eranian wrote:
>> This patch series contains improvement to the aggregation support
>> in perf stat.
>>
>> First, the aggregation code is refactored and a aggr_mode e
On Tue, Feb 12, 2013 at 6:29 PM, Andi Kleen wrote:
>>
>> > The idea itself is useful.
>> >
>> Yes, it is.
>
> BTW it would be even more useful if it could print some of the
> statistics turbostat does (in particular frequency and C0 residency)
> Often you only care about cycles not idle, and the f
On Tue, Apr 2, 2013 at 12:29 AM, David Ahern wrote:
> On 4/1/13 12:29 PM, John Stultz wrote:
>>>
>>> Any chance a decision can be reached in time for 3.10? Seems like the
>>> simplest option is the perf event based ioctl.
>>
>>
>> I'm still not sold on the CLOCK_PERF posix clock. The semantics are
rebased to
3.9.0-rc3.
In the 6th version, we integrated peterz' comments
and remove the irq masking/unmasking for the hrtimer
handler. It was redundant for core hrtimer code which
already block interrupts. We also rebased to 3.9.0-rc5.
Signed-off-by: Stephane Eranian
---
Stephane Eranian (2)
ion, we handle the reprogramming of the
hrtimer using hrtimer_forward_now(). That way, we sync
up to new timer value quickly (suggested by Jiri Olsa).
Signed-off-by: Stephane Eranian
---
include/linux/perf_event.h |1 +
kernel/events/core.c |
() such
that hrtimer_init() is run before perf_event_init().
The default interval in milliseconds is set to a
timer tick just like with the old code. We will
provide a sysctl to tune this in another patch.
Signed-off-by: Stephane Eranian
---
include/linux/perf_event.h |3 +-
init/main.c
On Wed, Apr 3, 2013 at 3:55 PM, David Ahern wrote:
> On 4/3/13 3:17 AM, Stephane Eranian wrote:
>>
>> I haven't done any specific testing with either approach yet. The goal is
>> to
>> use this perf timestamp to correlate user level events to hardware
>> eve
On Wed, Apr 3, 2013 at 4:14 PM, David Ahern wrote:
> On 4/3/13 8:00 AM, Stephane Eranian wrote:
>>>
>>> What's the advantage of changing apps -- like the JIT compiler -- to emit
>>> perf based timestamps versus having perf emit existing timestamps? ie.,
>&g
On Wed, Apr 3, 2013 at 7:57 PM, John Stultz wrote:
> On 04/03/2013 07:22 AM, Stephane Eranian wrote:
>>
>> On Wed, Apr 3, 2013 at 4:14 PM, David Ahern wrote:
>>>
>>> On 4/3/13 8:00 AM, Stephane Eranian wrote:
>>>>>
>>>>> Why not have
This small patch fixes a mistake in the comments
for the PERF_MEM_LVL_* events. The L2, L3 bits simply
represent cache levels, not hits or misses. That is
encoded in PERF_MEM_LVL_MISS/PERF_MEM_LVL_HIT.
Signed-off-by: Stephane Eranian
---
diff --git a/include/uapi/linux/perf_event.h b/include
On Mon, Jan 28, 2013 at 11:08 PM, Andi Kleen wrote:
>> > - if (lbr_format == LBR_FORMAT_EIP_FLAGS) {
>> > + if (lbr_format == LBR_FORMAT_EIP_FLAGS ||
>> > + lbr_format == LBR_FORMAT_EIP_FLAGS2) {
>> > mis = !!(from & LBR_FROM_FL
On Fri, Jan 25, 2013 at 11:00 PM, Andi Kleen wrote:
> From: Andi Kleen
>
> With checkpointed counters there can be a situation where the counter
> is overflowing, aborts the transaction, is set back to a non overflowing
> checkpoint, causes interupt. The interrupt doesn't see the overflow
> becau
On Mon, Jan 28, 2013 at 8:21 PM, Arnaldo Carvalho de Melo
wrote:
> Em Mon, Jan 28, 2013 at 07:26:17PM +0100, Stephane Eranian escreveu:
>> On Mon, Jan 28, 2013 at 6:59 PM, Arnaldo Carvalho de Melo
>> wrote:
>> > Em Fri, Jan 25, 2013 at 04:21:11PM +0100, Stephane Erania
On Tue, Jan 29, 2013 at 12:16 AM, Andi Kleen wrote:
>> I don't buy really this workaround. You are assuming you're always
>> measuring INTC_CHECKPOINTED
>> event by itself.
>
> There's no such assumption.
>
>> So what if you get into the handler because of an PMI
>> due to an overflow
>> of anothe
On Tue, Jan 29, 2013 at 12:46 AM, Fengguang Wu wrote:
> Signed-off-by: Fengguang Wu
Acked-by: Stephane Eranian
> ---
> arch/x86/kernel/cpu/perf_event_intel.c |4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> --- linux-next.orig/arch/x86/kernel/cpu/
, we added the column headings printed every 25 lines.
Cleaned up the code some more based on Namhyung's comments.
In v6, we simplify print_stat() by dropping the useless
check for interval as noted by Namhyung Kim. We also
rebase to 3.8.0-rc4.
In v7, we simply rebased to Arnaldo's perf/c
This field will be used by commands which print
counter deltas on regular timer intervals,
such as perf stat -I.
Signed-off-by: Stephane Eranian
---
tools/perf/util/evsel.c | 26 ++
tools/perf/util/evsel.h |1 +
2 files changed, 27 insertions(+)
diff --git a/tools
: Stephane Eranian
---
tools/perf/Documentation/perf-stat.txt |4 +
tools/perf/builtin-stat.c | 157 +---
2 files changed, 146 insertions(+), 15 deletions(-)
diff --git a/tools/perf/Documentation/perf-stat.txt
b/tools/perf/Documentation/perf-stat.txt
Arnaldo,
V7 posted. It's a rebase done against your perf/core, was no big deal.
Let me know if it works for you now.
On Tue, Jan 29, 2013 at 2:41 AM, Arnaldo Carvalho de Melo
wrote:
> Em Mon, Jan 28, 2013 at 11:45:56PM +0100, Stephane Eranian escreveu:
>> On Mon, Jan 28, 2
On Tue, Jan 29, 2013 at 2:00 AM, Andi Kleen wrote:
>
> On Tue, Jan 29, 2013 at 01:30:19AM +0100, Stephane Eranian wrote:
> > >> The counter is reinstated to its state before the critical section but
> > >> the PMI cannot be
> > >> cancelled and there
set.
Signed-off-by: Stephane Eranian
---
diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c
index dc8aee9..050d5bc 100644
--- a/tools/perf/util/evlist.c
+++ b/tools/perf/util/evlist.c
@@ -119,8 +119,7 @@ void __perf_evlist__set_leader(struct list_head *list)
leader = list_entry(l
tiple events.
Signed-off-by: Stephane Eranian
---
Stephane Eranian (2):
perf tools: add cpu_map__get_socket()
perf: add new perf uncore command
tools/perf/Documentation/perf-uncore.txt | 88
tools/perf/Makefile |1 +
tools/perf/arch/x86/Makefile |
To get the socket number associated with a CPU.
Useful for uncore output.
Signed-off-by: Stephane Eranian
---
tools/perf/util/cpumap.c | 26 ++
tools/perf/util/cpumap.h |1 +
2 files changed, 27 insertions(+)
diff --git a/tools/perf/util/cpumap.c b/tools/perf/util
hange for a given processor and
metric computation requires combining multiple events.
Signed-off-by: Stephane Eranian
---
tools/perf/Documentation/perf-uncore.txt | 88
tools/perf/Makefile |1 +
tools/perf/arch/x86/Makefile |1 +
tools/perf/arch/x86
On Thu, Jan 31, 2013 at 3:21 PM, Ingo Molnar wrote:
>
> * Stephane Eranian wrote:
>
>> This patchset adds a new command to perf: perf uncore.
>> It is used to measure processor socket-level metrics
>> on a system-wide basis and at all priv levels.
>>
>> The
pport which directly
> gives the instruction, not off-by-one instruction. So with precise == 2
> we use that directly and don't try to use LBRs and walking basic blocks.
> This lowers the overhead significantly.
>
> Some other features are added in later patches.
>
> Signe
Andi,
Are you going to post a new version based on my feedback or do you stay
with what you posted on 1/25?
On Fri, Jan 25, 2013 at 11:00 PM, Andi Kleen wrote:
> This is based on v7 of the full Haswell PMU support, but
> ported to the latest perf/core and stripped down to the "basic support"
>
Hi,
Looks like perf annotate in pipe mode is totally broken nowadays.
I tried this from tip.git:
$ perf record -o - noploop 5 >perf.data
$ perf annotate -i i < perf.data
Core dump
Callstack looks as follows:
0x0049f9e4 in add_hist_entry (hists=0x809708,
entry=0x7fffde60, al=0x7ff
On Fri, Feb 1, 2013 at 9:04 AM, Namhyung Kim wrote:
> Hi Stephane,
>
> On Fri, 1 Feb 2013 00:51:51 +0100, Stephane Eranian wrote:
>> Hi,
>>
>> Looks like perf annotate in pipe mode is totally broken nowadays.
>> I tried this from tip.git:
>>
>> $ pe
pport which directly
> gives the instruction, not off-by-one instruction. So with precise == 2
> we use that directly and don't try to use LBRs and walking basic blocks.
> This lowers the overhead significantly.
>
> Some other features are added in later patches.
>
> Sig
evented
> from being set on fixed counters.
>
> Contains fixes from Stephane Eranian
>
> v2: Folded TSX bits into standard FIXED_EVENT_CONSTRAINTS
> v3: Use SNB LBR init code. Comment fix (Stephane Eranian)
> Signed-off-by: Andi Kleen
Looks ok to me, just minor typo in comment
typo in PEBS event table (Stephane Eranian)
> Signed-off-by: Andi Kleen
Looks ok to me.
Reviewed-by: Stephane Eranian
> ---
> arch/x86/kernel/cpu/perf_event.h |2 ++
> arch/x86/kernel/cpu/perf_event_intel.c|6 --
> arch/x86/
On Thu, Jan 10, 2013 at 8:50 PM, Jacob Shin wrote:
> The following patchset enables 4 additional performance counters in
> AMD family 15h processors that count northbridge events -- such as
> number of DRAM accesses.
>
In order for me to test this patch set more thoroughly it would help if you
cou
On Thu, Jan 24, 2013 at 12:56 PM, Ingo Molnar wrote:
>
> * Stephane Eranian wrote:
>
>> This patch series had a new feature to the kernel perf_events
>> interface and corresponding user level tool, perf.
>
> Would be nice to merge this with the overlapping parts
From: Andi Kleen
Add a way for the CPU initialization code to register additional events,
and merge them into the events attribute directory. Used in the next
patch.
Signed-off-by: Andi Kleen
---
arch/x86/kernel/cpu/perf_event.c | 33 +
arch/x86/kernel/cpu/per
This patch extends Jiri's changes to make generic
events mapping visible via sysfs. The patch extends
the mechanism to non-generic events by allowing
the mappings to be hardcoded in strings.
This mechanism will be used by the PEBS-LL patch
later on.
Signed-off-by: Stephane Eranian
---
arc
hardware.
Signed-off-by: Stephane Eranian
---
include/linux/perf_event.h |2 ++
include/uapi/linux/perf_event.h | 68 +--
kernel/events/core.c|6
3 files changed, 74 insertions(+), 2 deletions(-)
diff --git a/include/linux
-loads. It export the right event
encoding based on the host CPU and can be used directly
by the perf tool.
Loosely based on Intel's Lin Ming patch posted on LKML
in July 2011.
Signed-off-by: Stephane Eranian
---
arch/x86/include/uapi/asm/msr-index.h |1 +
arch/x86/kernel/cpu/perf_ev
.
Signed-off-by: Stephane Eranian
---
arch/x86/kernel/cpu/perf_event.h |5 +++
arch/x86/kernel/cpu/perf_event_intel.c|2 ++
arch/x86/kernel/cpu/perf_event_intel_ds.c | 49 +++--
3 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/arch/x86
- mem : memory level of the access (L1, L2, L3, RAM, ...)
- snoop: access snoop mode
Signed-off-by: Stephane Eranian
---
tools/perf/util/event.h |1 +
tools/perf/util/evsel.c |6 +
tools/perf/util/hist.c| 77 +++-
tools/perf/util/hist.h| 13 ++
tools/perf/util
This patch adds the --mem-mode option to perf report.
This mode requires a perf.data file created with memory
access samples.
Signed-off-by: Stephane Eranian
---
tools/perf/builtin-report.c | 140 +--
1 file changed, 135 insertions(+), 5 deletions
not set, then
the mapping is executable.
Signed-off-by: Stephane Eranian
---
include/uapi/linux/perf_event.h |1 +
kernel/events/core.c|3 +++
2 files changed, 4 insertions(+)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 3e4844c..3907
Leverages the PERF_RECORD_MISC_MMAP_DATA bit in
the RECORD_MMAP record header. When the bit is set
then the mapping type is set to MAP__VARIABLE.
Signed-off-by: Stephane Eranian
---
tools/perf/util/machine.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/tools
)
Cc: Stephane Eranian
Signed-off-by: Namhyung Kim
---
tools/perf/util/symbol-elf.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c
index db0cc92..00cf128 100644
--- a/tools/perf/util/symbol-elf.c
+++ b/tools/perf/util/symbol-
From: Namhyung Kim
The symbol addresses in a dso have relative offsets from the start of
a mapping. So in order to ouput correct offset value from @ip, one of
them should be converted.
Cc: Stephane Eranian
Signed-off-by: Namhyung Kim
---
tools/perf/util/sort.c |2 +-
1 file changed, 1
This new command is a wrapper on top of perf record and
perf report to make it easier to configure for memory
access profiling.
To record loads:
$ perf mem -t load rec .
To record stores:
$ perf mem -t store rec .
To get the report:
$ perf mem -t load rep
Signed-off-by: Stephane
eigthened sample support completely.
Signed-off-by: Stephane Eranian
---
Andi Kleen (3):
perf, x86: Support CPU specific sysfs events
perf, core: Add a concept of a weightened sample v2
perf, tools: Add support for weight v7 (modified)
Namhyung Kim (2):
perf tools: Ignore ABS symbols
the
put_event_constraint() call.
This mechanism is going to be used by the PEBS-LL patches.
It avoids defining yet another table to hold event specific
information.
Signed-off-by: Stephane Eranian
---
arch/x86/kernel/cpu/perf_event.c |2 +-
arch/x86/kernel/cpu/perf_even
from Andi modified by Stephane Eranian
to include ONLY the weight supporting code and apply to pristine 3.8.0-rc4.
Signed-off-by: Andi Kleen
---
tools/perf/Documentation/perf-record.txt |6
tools/perf/Documentation/perf-report.txt |2 +-
tools/perf/Documentation/perf-top.txt
We use the -W option to obtain the cost of the
memory accesses.
Data address sampling is obtained via the -d option.
Signed-off-by: Stephane Eranian
---
tools/perf/util/evsel.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index
Make the PEBS Load Latency threshold register layout
and encoding visible to user level tools.
Signed-off-by: Stephane Eranian
---
arch/x86/kernel/cpu/perf_event_intel.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c
b/arch/x86/kernel/cpu
Was missing from current code yet PERF_SAMPLE_ADDR has
been present for a long time. Needed for PEBS-LL mode.
Signed-off-by: Stephane Eranian
---
tools/perf/util/session.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/session.c b/tools/perf/util
From: Andi Kleen
For some events it's useful to weight sample with a hardware
provided number. This expresses how expensive the action the
sample represent was. This allows the profiler to scale
the samples to be more informative to the programmer.
There is already the period which is used simi
Shin wrote:
> On Thu, Jan 24, 2013 at 02:31:59PM +0100, Stephane Eranian wrote:
>> On Thu, Jan 10, 2013 at 8:50 PM, Jacob Shin wrote:
>> > The following patchset enables 4 additional performance counters in
>> > AMD family 15h processors that count northbridge event
On Thu, Jan 10, 2013 at 8:50 PM, Jacob Shin wrote:
> From: Robert Richter
>
> Code simplification. No functional changes.
>
> Signed-off-by: Robert Richter
> Signed-off-by: Jacob Shin
Acked-by: Stephane Eranian
> ---
> arch/x86/kernel/cpu
On Thu, Jan 10, 2013 at 8:50 PM, Jacob Shin wrote:
> From: Robert Richter
>
> Generalize northbridge constraints code for family 10h so that later
> we can reuse the same code path with other AMD processor families that
> have the same northbridge event constraints.
>
> Signed-off-by: Robert Rich
On Thu, Jan 10, 2013 at 8:50 PM, Jacob Shin wrote:
> Update these AMD bit field names to be consistent with naming
> convention followed by the rest of the file.
>
> Signed-off-by: Jacob Shin
Acked-by: Stephane Eranian
> ---
> arch/x86/include/asm/perf_event.h|
On Thu, Jan 10, 2013 at 8:50 PM, Jacob Shin wrote:
> Move counter index to MSR address offset calculation to architecture
> specific files. This prepares the way for perf_event_amd to enable
> counter addresses that are not contiguous -- for example AMD Family
> 15h processors have 6 core performa
On Thu, Jan 10, 2013 at 8:50 PM, Jacob Shin wrote:
> Similar to config_base and event_base, allow architecture specific
> RDPMC ECX values.
>
> Signed-off-by: Jacob Shin
Acked-by: Stephane Eranian
> ---
> arch/x86/kernel/cpu/perf_event.c |2 +-
> arch/x86/ke
On Thu, Jan 10, 2013 at 8:50 PM, Jacob Shin wrote:
> On AMD family 15h processors, there are 4 new performance counters
> (in addition to 6 core performance counters) that can be used for
> counting northbridge events (i.e. DRAM accesses). Their bit fields are
> almost identical to the core perfor
On Fri, Jan 25, 2013 at 3:52 AM, Arnaldo Carvalho de Melo
wrote:
> Em Tue, Jan 22, 2013 at 02:18:52PM +0100, Stephane Eranian escreveu:
>> This patch adds a new printing mode for perf stat.
>> It allows internval printing. That means perf stat
>> can now print event d
On Fri, Jan 25, 2013 at 9:55 AM, Ingo Molnar wrote:
>
> * Stephane Eranian wrote:
>
>> This patch series had a new feature to the kernel perf_events
>> interface and corresponding user level tool, perf.
>
> Can I add your Signed-off-by tag to the patches you picked
On Fri, Jan 25, 2013 at 10:01 AM, Ingo Molnar wrote:
>
> * Stephane Eranian wrote:
>
>> This patch adds PERF_SAMPLE_DSRC.
>>
>> PERF_SAMPLE_DSRC collects the data source, i.e., where
>> did the data associated with the sampled instruction
>> come from. I
ed by default]
> arch/x86/kernel/cpu/perf_event.c:1510:31: warning: assignment from
> incompatible
> pointer type [enabled by default]
>
> Signed-off-by: Borislav Petkov
> Cc: Andi Kleen
> Cc: Stephane Eranian
Acked-by: Stephane Eranian
> ---
> arch/x86/kernel/cpu/pe
On Fri, Jan 25, 2013 at 11:00 PM, Andi Kleen wrote:
> From: Andi Kleen
>
> Add support for the v2 PEBS format. It has a superset of the v1 PEBS
> fields, but has a longer record so we need to adjust the code paths.
>
> The main advantage is the new "EventingRip" support which directly
> gives the
evented
> from being set on fixed counters.
>
> Contains fixes from Stephane Eranian
>
> v2: Folded TSX bits into standard FIXED_EVENT_CONSTRAINTS
> Signed-off-by: Andi Kleen
> ---
> arch/x86/include/asm/perf_event.h |3 +++
> arch/x86/kernel/cpu/per
On Fri, Jan 25, 2013 at 11:00 PM, Andi Kleen wrote:
> From: Andi Kleen
>
> Add basic PEBS support for Haswell.
> The constraints are similar to SandyBridge with a few new events.
>
> v2: Readd missing pebs_aliases
> v3: Readd missing hunk. Fix some constraints.
> Signed-off-by: Andi Kleen
> ---
On Fri, Jan 25, 2013 at 11:00 PM, Andi Kleen wrote:
> From: Andi Kleen
>
> Implement the TSX transaction and checkpointed transaction qualifiers for
> Haswell. This allows e.g. to profile the number of cycles in transactions.
>
> The checkpointed qualifier requires forcing the event to
> counter
gt; Cc: Arnaldo Carvalho de Melo
> Cc: Namhyung Kim
> Cc: Corey Ashford
> Cc: Frederic Weisbecker
> Cc: Ingo Molnar
> Cc: Namhyung Kim
> Cc: Paul Mackerras
> Cc: Peter Zijlstra
> Cc: Stephane Eranian
> ---
> arch/x86/kernel/cpu/perf_event_intel.c | 2 ++
> 1
On Mon, Jan 28, 2013 at 6:59 PM, Arnaldo Carvalho de Melo
wrote:
> Em Fri, Jan 25, 2013 at 04:21:11PM +0100, Stephane Eranian escreveu:
>> On Fri, Jan 25, 2013 at 3:52 AM, Arnaldo Carvalho de Melo
>> wrote:
>> > Em Tue, Jan 22, 2013 at 02:18:52PM +0100, Stephane Eran
gt; Signed-off-by: Jiri Olsa
> Cc: Corey Ashford
> Cc: Frederic Weisbecker
> Cc: Ingo Molnar
> Cc: Namhyung Kim
> Cc: Paul Mackerras
> Cc: Peter Zijlstra
> Cc: Arnaldo Carvalho de Melo
> Cc: Andi Kleen
> Cc: Stephane Eranian
> ---
> tools/perf/util/parse-events.l
On Mon, Jan 28, 2013 at 9:52 PM, Stephane Eranian wrote:
> Jiri,
>
> I don't see part 0/8 of this series. Did you send it to me too?
>
> I have some comments about it. I don't see why create something from scratch
> when I have been developing a library (libpfm4)
On Fri, Jan 25, 2013 at 11:00 PM, Andi Kleen wrote:
> From: Andi Kleen
>
> Haswell has two additional LBR from flags for TSX: intx and abort, implemented
> as a new v4 version of the LBR format.
>
> Handle those in and adjust the sign extension code to still correctly extend.
> The flags are expo
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