From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 46 ++
1 file changed, 46 i
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
inde
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' regi
Hi Viresh,
On 2/26/2018 3:34 PM, Viresh Kumar wrote:
> On 26-02-18, 15:23, Sricharan R wrote:
>> From: Stephen Boyd
>
> Is this email id still valid ?
>
Yes. codeaurora id should exist.
>> +static int __init qcom_cpufreq_populate_opps(stru
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (2):
clk: qcom: Add safe switch hook for krait mux clocks
dt-bindings: cpufreq: Document operating-points-v2-krait-cpu
Stephen Boyd (13):
ARM: Add Krait L2 register accessor functions
clk: mux: Spl
eady. Pull that logic out into reusable functions
that operate on an optional table and some flags so that other
drivers can use the same logic.
[Sricharan: Rebased for mainline]
Signed-off-by: Sricharan R
Signed-off-by: Stephen Boyd
---
drivers/clk/clk-mux.c
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' regi
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
drivers/clk/qcom/
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files changed
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
inde
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,krait-cc.txt| 22 ++
1
itching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-
From: Stephen Boyd
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Acked-by: Viresh Kumar
[Sricharan: updated to use dev_pm_opp_set_prop_name and
nvmem apis]
Signed-off-by: Sricharan R
Signed-off-by: St
-cpufreq driver
reads the efuse value from the SoC to provide the required information
that is used to determine the voltage and current value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.
Signed-off-by: Sricharan R
---
.../devicetree/bindings/cpufreq/krait
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
Signed-off
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 +
.../devic
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 46 ++
1 file changed, 46 i
x-arm-kernel/2015-March/332615.html
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (2):
clk: qcom: Add safe switch hook for krait mux clocks
dt-bindings: cpufreq: Document
eady. Pull that logic out into reusable functions
that operate on an optional table and some flags so that other
drivers can use the same logic.
[Sricharan: Rebased for mainline]
Signed-off-by: Sricharan R
Signed-off-by: Stephen Boyd
---
drivers/clk/clk-mux.c
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' regi
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 46 ++
1 file changed, 46 i
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
drivers/clk/qcom/
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files changed
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
inde
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig
itching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-
-cpufreq driver
reads the efuse value from the SoC to provide the required information
that is used to determine the voltage and current value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.
Signed-off-by: Sricharan R
---
.../devicetree/bindings/cpufreq/krait
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,krait-cc.txt| 22 ++
1
From: Stephen Boyd
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Cc:
[Sricharan: updated to use dev_pm_opp_set_prop_name, NVMEM apis,
new binding]
Signed-off-by: Sricharan R
Signed-off-by: Stephen Boyd
--
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
Signed-off
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 +
.../devic
Hi Viresh,
On 2/6/2018 9:56 AM, Viresh Kumar wrote:
> On 06-02-18, 09:38, Sricharan R wrote:
>> diff --git a/drivers/cpufreq/qcom-cpufreq.c b/drivers/cpufreq/qcom-cpufreq.c
>> new file mode 100644
>> index 000..5b988d4
>> --- /dev/null
>> +++ b/drivers/cpufreq
Hi Viresh,
On 2/6/2018 9:57 AM, Viresh Kumar wrote:
> On 06-02-18, 09:38, Sricharan R wrote:
>> In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
>> that has KRAIT processors the voltage/current value of each OPP
>> varies based on the silicon variant in use.
&
Hi Rob,
On 2/5/2018 11:37 AM, Rob Herring wrote:
> On Mon, Jan 29, 2018 at 10:41:15AM +0530, Sricharan R wrote:
>> Add the compatible for ipq4019.
>> This does not need clocks to do scm calls.
>>
>> Signed-off-by: Sricharan R
>> ---
>> Documentation/device
Hi Abhishek,
On 2/3/2018 4:25 PM, Abhishek Sahu wrote:
> On 2018-01-29 10:41, Sricharan R wrote:
>> The board has a spi-nand interface on spi0 bus chipselect1.
>>
>> Signed-off-by: Sricharan R
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
&
Hi Abhishek,
On 2/3/2018 4:47 PM, Abhishek Sahu wrote:
> On 2018-01-29 10:41, Sricharan R wrote:
>> Add the common parts for the dk04 boards.
>>
>> Signed-off-by: Sricharan R
>> ---
>> arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 147
>
>
&g
Hi Abhishek,
On 2/3/2018 5:00 PM, Abhishek Sahu wrote:
> On 2018-01-29 10:41, Sricharan R wrote:
>> Signed-off-by: Sricharan R
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 8
>&g
Hi Abhishek,
On 2/3/2018 5:07 PM, Abhishek Sahu wrote:
> On 2018-01-29 10:41, Sricharan R wrote:
>> Signed-off-by: Sricharan R
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 14 +++
Hi Abhishek,
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (c) 2017, The Linux Foundation. All rights reserved.
>> +
>> +#include "qcom-ipq4019-ap.dk07.1.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK07.1-C2";
>
> s/IPQ40xx/IPQ4019
>
ok
>> +
>> +
Hi Viresh,
On 12/20/2017 9:06 AM, Viresh Kumar wrote:
> On 19-12-17, 21:24, Sricharan R wrote:
>> From: Stephen Boyd
>>
>> Register a cpufreq-generic device whenever we detect that a
>> "qcom,krait" compatible CPU is present in DT.
>
Hi Viresh,
On 12/20/2017 8:56 AM, Viresh Kumar wrote:
> On 19-12-17, 21:25, Sricharan R wrote:
>> +cpu@0 {
>> +compatible = "qcom,krait";
>> +enable-method = "qcom,kpss-acc-v1";
>> +device_type = "cpu&q
Hi Viresh,
On 12/20/2017 11:57 AM, Viresh Kumar wrote:
> On 20-12-17, 11:55, Sricharan R wrote:
>>>> + opp-14 {
>>>> + opp-hz = /bits/ 64 <14>;
>>>> + opp-microvolt-speed0-pvs0-v0 = <1250
Hi Rob,
On 12/21/2017 2:41 AM, Rob Herring wrote:
> On Tue, Dec 19, 2017 at 09:24:50PM +0530, Sricharan R wrote:
>> From: Stephen Boyd
>>
>> Adds bindings document for qcom,hfpll instantiated within
>> the Krait processor subsystem as separate register region.
>&g
On 12/21/2017 2:43 AM, Rob Herring wrote:
> On Tue, Dec 19, 2017 at 09:24:55PM +0530, Sricharan R wrote:
>> From: Stephen Boyd
>>
>> The ACC and GCC regions present in KPSSv1 contain registers to
>> control clocks and power to each Krait CPU and L2. Docum
On 12/21/2017 2:44 AM, Rob Herring wrote:
> On Tue, Dec 19, 2017 at 09:24:57PM +0530, Sricharan R wrote:
>> From: Stephen Boyd
>>
>> The Krait clock controller controls the krait CPU and the L2 clocks
>> consisting a primary mux and secondary mux. Add document fo
Hi Rob,
On 12/21/2017 2:48 AM, Rob Herring wrote:
> On Wed, Dec 20, 2017 at 11:55:33AM +0530, Sricharan R wrote:
>> Hi Viresh,
>>
>> On 12/20/2017 8:56 AM, Viresh Kumar wrote:
>>> On 19-12-17, 21:25, Sricharan R wrote:
>>>> + cpu@0
Hi Bjorn,
On 11/14/2017 4:23 PM, Sricharan R wrote:
> IPQ8074 has an integrated Hexagon dsp core Q6v5 and a wireless lan
> (Lithium) IP. This series adds the remoteproc driver to reset, load
> and boot Q6 firmware.
>
> The first patch is to make the mdt_loader authenticate
> th
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' regi
eady. Pull that logic out into reusable functions
that operate on an optional table and some flags so that other
drivers can use the same logic.
[Sricharan: Rebased for mainline]
Signed-off-by: Sricharan R
Signed-off-by: Stephen Boyd
---
drivers/clk/clk-mux.c
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332607.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332615.html
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
[4] https://lwn.net/Articles/740994/
Sricharan R (1):
clk:
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
drivers/clk/qcom/
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files changed
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig
itching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-
From: Stephen Boyd
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/arm/msm/qcom,pvs.txt | 91 ++
1 file changed, 91 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/
From: Stephen Boyd
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Cc:
[Sricharan: updated to use dev_pm_opp_set_prop_name]
Signed-off-by: Sricharan R
Signed-off-by: Stephen Boyd
---
drivers/cpufreq/Kconfig.arm
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,krait-cc.txt| 22 ++
1 file changed, 22 insertion
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
Signed-off
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 +
.../devicetree/bindings/arm/msm/qco
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 46 ++
1 file changed, 46 insertions(+)
create mode
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
inde
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/
Hi Rob,
On 12/26/2017 11:06 PM, Rob Herring wrote:
> On Thu, Dec 21, 2017 at 5:53 AM, Sricharan R wrote:
>> Hi Rob,
>>
>> On 12/21/2017 2:48 AM, Rob Herring wrote:
>>> On Wed, Dec 20, 2017 at 11:55:33AM +0530, Sricharan R wrote:
>>>> Hi Viresh,
>>&
Hi Rob,
Thanks for the review.
On 12/13/2017 2:05 AM, Rob Herring wrote:
> On Fri, Dec 08, 2017 at 03:12:22PM +0530, Sricharan R wrote:
>> From: Stephen Boyd
>>
>> On some devices (MSM8974 for example), the HFPLLs are
>> instantiated within the Krait processor subsys
Hi Rob,
On 12/13/2017 2:06 AM, Rob Herring wrote:
> On Fri, Dec 08, 2017 at 03:12:23PM +0530, Sricharan R wrote:
>> From: Stephen Boyd
>>
>> Describe the HFPLLs present on MSM8960 and APQ8064 devices.
>>
>> Signed-off-by: Stephen Boyd
>>
Hi Rob,
On 12/13/2017 2:21 AM, Rob Herring wrote:
> On Fri, Dec 08, 2017 at 03:12:27PM +0530, Sricharan R wrote:
>> From: Stephen Boyd
>>
>> The Krait CPU clocks are made up of a primary mux and secondary
>> mux for each CPU and the L2, controlled via cp15 accessors.
Hi Rob,
On 12/13/2017 2:08 AM, Rob Herring wrote:
> On Fri, Dec 08, 2017 at 03:12:26PM +0530, Sricharan R wrote:
>> From: Stephen Boyd
>>
>> The ACC and GCC regions present in KPSSv1 contain registers to
>> control clocks and power to each Krait CPU and L2. For CPUf
Hi Rob,
On 9/12/2017 7:51 PM, Rob Herring wrote:
> On Thu, Aug 31, 2017 at 10:15:33AM +0530, Sricharan R wrote:
>> IPQ8074 has an integrated Hexagon dsp core q6v5 and a wireless lan
>> (Lithium) IP. An mdt type single image format is used for the
>> firmware. So the mdt
Hi Chris,
On 8/29/2017 3:21 AM, Chris Lew wrote:
> Hi Sricharan,
>
> Minor bug in this patch.
>
> On 8/24/2017 12:21 AM, Sricharan R wrote:
> [..]
>> @@ -829,11 +839,14 @@ static int qcom_glink_rx_open(struct qcom_glink
>> *glink, unsigned int rcid,
>
is is done on top of Avaneesh's msm8996 rproc support [1]
[1] https://lkml.org/lkml/2017/7/21/217
V2:
Last time introduced this a new rproc driver, but there is lot
of code that can be shared if it is added to the q6v5-mpss pil
driver.
Sricharan R (6):
remoteproc: qcom: mdt_lo
qcom_mdt_load function loads the mdt type firmware and
initialises the secure memory as well. Make the initialisation only
when requested by the caller, so that the function can be used
by self-authenticating remoteproc as well.
Signed-off-by: Sricharan R
---
drivers/soc/qcom/mdt_loader.c
Instead of directly assigning reset, fw and rproc ops, put them
in to of_match data and get from that. Currently same ops
are used for all compatibles, but that will change when we add
q6v5-wcss support.
Signed-off-by: Sricharan R
---
drivers/remoteproc/qcom_q6v5_pil.c | 38
q6v5-wcss core's start function is mostly common
with the q6v5 of msm8996. So reuse that and add
the stop function.
Signed-off-by: Sricharan R
---
drivers/remoteproc/qcom_q6v5_pil.c | 212 +
1 file changed, 212 insertions(+)
diff --git a/drivers/remot
IPQ8074 has an integrated Hexagon dsp core q6v5 and a wireless lan
(Lithium) IP. An mdt type single image format is used for the
firmware. So the mdt_load function can be directly used to load
the firmware. Also add the relevant resets required for this core.
Signed-off-by: Sricharan R
Most of the q6v5-pil start function is same for the q6v5-wcss rproc
that will be added later. So split and move out the common pieces
so that the same code can be reused.
Signed-off-by: Sricharan R
---
drivers/remoteproc/qcom_q6v5_pil.c | 165 +
1 file
Export rproc_elf_get_boot_addr so that it can be
used by any remoteproc to get the bootaddr of the
elf type firmware images. This is used in the
subsequent patch by the q6v5 based remoteproc
while loading its elf based mdt type image.
Signed-off-by: Sricharan R
---
drivers/remoteproc
Export rproc_elf_get_boot_addr so that it can be
used by any remoteproc to get the bootaddr of the
elf type firmware images. This is used in the
subsequent patch by the q6v5 based remoteproc
while loading its elf based mdt type image.
Signed-off-by: Sricharan R
---
drivers/remoteproc
Instead of directly assigning reset, fw and rproc ops, put them
in to of_match data and get from that. Currently same ops
are used for all compatibles, but that will change when we add
q6v5-wcss support.
Signed-off-by: Sricharan R
---
drivers/remoteproc/qcom_q6v5_pil.c | 38
driver.
Sricharan R (6):
remoteproc: qcom: mdt_loader: Make the firmware authentication
optional
remoteproc: Export rproc_elf_get_boot_addr
remoteproc: qcom: Push reset ops, fw ops, rproc ops in to of_match
data
remoteproc: qcom: Split the head and tail of the q6v5-pil rproc
Most of the q6v5-pil start function is same for the q6v5-wcss rproc
that will be added later. So split and move out the common pieces
so that the same code can be reused.
Signed-off-by: Sricharan R
---
drivers/remoteproc/qcom_q6v5_pil.c | 166 -
1 file
q6v5-wcss core's start function is mostly common
with the q6v5 of msm8996. So reuse that and add
the stop function.
Signed-off-by: Sricharan R
---
drivers/remoteproc/qcom_q6v5_pil.c | 212 +
1 file changed, 212 insertions(+)
diff --git a/drivers/remot
qcom_mdt_load function loads the mdt type firmware and
initialises the secure memory as well. Make the initialisation only
when requested by the caller, so that the function can be used
by self-authenticating remoteproc as well.
Signed-off-by: Sricharan R
---
drivers/soc/qcom/mdt_loader.c
IPQ8074 has an integrated Hexagon dsp core q6v5 and a wireless lan
(Lithium) IP. An mdt type single image format is used for the
firmware. So the mdt_load function can be directly used to load
the firmware. Also add the relevant resets required for this core.
Signed-off-by: Sricharan R
Hi Arun,
Thanks for the review.
On 8/22/2017 11:28 AM, Arun Kumar Neelakantam wrote:
>
>
> On 8/16/2017 10:48 PM, Sricharan R wrote:
>> +
>> +struct glink_msg {
>> + __le16 cmd;
>> + __le16 param1;
>> + __le32 param2;
>> + u8 data[];
&
Hi,
>
> spinlock intent_lock initialization is missed ?
right, should add that.
>> kref_init(&channel->refcount);
>> return channel;
>> @@ -187,6 +215,7 @@ static void qcom_glink_channel_release(struct kref *ref)
>> struct glink_channel *channel = container_of(ref, struct
Hi,
>> - /* Might have an ongoing, fragmented, message to append */
>> - if (!channel->buf) {
>> - channel->buf = kmalloc(chunk_size + left_size, GFP_ATOMIC);
>> - if (!channel->buf)
>> - return -ENOMEM;
>> + if (glink->intentless) {
>> + /* Might have
Hi,
>> + /* Take it off the tree of receive intents */
>> + if (!intent->reuse) {
>> + spin_lock(&channel->intent_lock);
>> + idr_remove(&channel->liids, intent->id);
>> + spin_unlock(&channel->intent_lock);
>> + }
>> +
>> + /* Schedule the sending of a rx_done indi
MTD_SPEEDTEST READ PAGE: 3860 KiB/s
>> MTD_SPEEDTEST WRITE PAGE: 2837 KiB/s
>> IOZONE READ: 2677 KB/s
>> IOZONE WRITE: 1308 KB/s
>>
>> bam dma interrupts (after tests): 58806
>>
>> Signed-off-by
From: Bjorn Andersson
Renaming the glink_rpm_xx functions and structs to qcom_glink_xx
equivalents helps to reuse the core glink protocol while adding
support for smem based glink transport in the later patches.
Signed-off-by: Bjorn Andersson
Signed-off-by: Sricharan R
---
drivers/rpmsg
glink: Make RX FIFO peak accessor to take an offset
Sricharan R (13):
rpmsg: glink: Return -EAGAIN when there is no FIFO space
rpmsg: glink: Do a mbox_free_channel in remove
rpmsg: glink: Fix default case while handling received commands
rpmsg: glink: Add support for transport version nego
Currently if we receive a command that we still do not
support, then its simply discarded. While doing so, the
RX FIFO pointer also needs to be incremented. Fixing this.
Signed-off-by: Sricharan R
---
drivers/rpmsg/qcom_glink_native.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers
introduce this.
Signed-off-by: Bjorn Andersson
Signed-off-by: Sricharan R
---
drivers/rpmsg/qcom_glink_native.c | 15 +++
drivers/rpmsg/qcom_glink_native.h | 2 +-
drivers/rpmsg/qcom_glink_rpm.c| 5 -
drivers/rpmsg/qcom_glink_smem.c | 5 -
4 files changed, 16 insertions
Once the remote side sends a rx done ack, check
for the intent reuse information from it and
suitably discard or reuse the remote passed
intent buffers.
Signed-off-by: Sricharan R
Signed-off-by: Bjorn Andersson
---
drivers/rpmsg/qcom_glink_native.c | 42
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