Thanks Arnd.
Regards,
Shiju
> -Original Message-
> From: arndbergm...@gmail.com [mailto:arndbergm...@gmail.com] On Behalf
> Of Arnd Bergmann
> Sent: 19 January 2018 15:07
> To: Timur Tabi
> Cc: Shiju Jose; Linux ARM; Linux Kernel Mailing List; Catalin Marinas;
>
Enable ACPI APEI SEA option for arm64, to handle
ARMv8 SEA(Synchronous External Abort).
Signed-off-by: Shiju Jose
Cc: Tyler Baicar
Cc: James Morse
Cc: Dongjiu Geng
Cc: Xie XiuQi
Cc: Qiang Zheng
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64
Hi Gengdongjiu,
Ok got it. Please ignore this patch.
Thanks,
Shiju
> -Original Message-
> From: gengdongjiu
> Sent: 21 March 2018 01:49
> To: Shiju Jose; xuwei (O)
> Cc: a...@arndb.de; james.mo...@arm.com; tbai...@codeaurora.org;
> Xiexiuqi; Zhengqiang (turing); Linu
ocessor context information and vendor
>specific error information with raw hex format.
>
>Signed-off-by: Jason Tian
>---
> drivers/ras/ras.c | 22 +-
> include/ras/ras_event.h | 41 +++---
>---
> 2 files changed, 56 insertions
shared CPU list of that shared cache.
For the firmware-first error reporting, add an interface in the
ghes_edac allow to report a CPU corrected error count.
Suggested-by: James Morse
Signed-off-by: Shiju Jose
---
Documentation/ABI/testing/sysfs-devices-edac | 15 ++
drivers/acpi/a
Hi James,
>-Original Message-
>From: linux-acpi-ow...@vger.kernel.org [mailto:linux-acpi-
>ow...@vger.kernel.org] On Behalf Of James Morse
>Sent: 31 July 2020 14:48
>To: Shiju Jose
>Cc: Andy Shevchenko ; linux-
>a...@vger.kernel.org; linux-...@vger.ke
PCIe controller does not use DWC IP.
Signed-off-by: Yicong Yang
Signed-off-by: Shiju Jose
Acked-by: Bjorn Helgaas
--
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-hisi-error.c | 336 +++
3
the device.
V1:
1. Fix comments from James Morse.
2. add driver to handle HiSilicon hip08 PCIe controller's errors,
which is an application of the above interface.
Shiju Jose (1):
ACPI / APEI: Add a notifier chain for unknown (vendor) CPER records
Yicong Yang (1):
PCI: hip: A
er has run.
Co-developed-by: James Morse
Signed-off-by: James Morse
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 63
include/acpi/ghes.h | 18
2 files changed, 81 insertions(+)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/a
application could monitor the recorded corrected error
count for the predictive failure analysis.
More information in the patch headers.
Shiju Jose (2):
EDAC/ghes: Add EDAC device for the CPU caches
ACPI / APEI: Add reporting ARM64 CPU cache corrected error count
Documentation/ABI/testing
d the solution 2.1
For the firmware-first error handling, add an interface in the
ghes_edac for reporting the CPU corrected error count for
a CPU core to the user-space through the CPU EDAC device.
Suggested-by: James Morse
Signed-off-by: Shiju Jose
---
Documentation/ABI/testing/sysfs-devices-edac
uot;
would be merged on the mainline.
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 68 ++--
include/linux/cper.h | 4 +++
2 files changed, 69 insertions(+), 3 deletions(-)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/gh
Hi Boris,
>-Original Message-
>From: Borislav Petkov [mailto:b...@alien8.de]
>Sent: 18 January 2021 18:37
>To: Shiju Jose
>Cc: linux-e...@vger.kernel.org; linux-a...@vger.kernel.org; linux-
>ker...@vger.kernel.org; james.mo...@arm.com;
>mchehab+hua...@kernel.org; t
Hi Boris,
Thanks for the feedback.
Apologies for the delay.
>-Original Message-
>From: Borislav Petkov [mailto:b...@alien8.de]
>Sent: 31 December 2020 16:44
>To: Shiju Jose
>Cc: linux-e...@vger.kernel.org; linux-a...@vger.kernel.org; linux-
>ker...@vger.kernel.org; j
Hi James,
Can you review and help to merge this patch?
Thanks,
Shiju
>-Original Message-
>From: Rafael J. Wysocki [mailto:raf...@kernel.org]
>Sent: 05 February 2021 12:54
>To: Shiju Jose ; Borislav Petkov ;
>James Morse
>Cc: open list:EDAC-CORE ; ACPI Devel Maling
&g
Hi James,
Thanks for the feedback.
>-Original Message-
>From: linux-acpi-ow...@vger.kernel.org [mailto:linux-acpi-
>ow...@vger.kernel.org] On Behalf Of James Morse
>Sent: 21 August 2019 18:23
>To: Shiju Jose
>Cc: linux-a...@vger.kernel.org; linux-e...@vger.kerne
Hi James,
>-Original Message-
>From: James Morse [mailto:james.mo...@arm.com]
>Sent: 21 August 2019 18:23
>To: Shiju Jose
>Cc: linux-a...@vger.kernel.org; linux-e...@vger.kernel.org; linux-
>ker...@vger.kernel.org; r...@rjwysocki.net; l...@kernel.org;
>tony.l...@inte
Hi James,
>-Original Message-
>From: James Morse [mailto:james.mo...@arm.com]
>Sent: 21 August 2019 18:24
>To: Shiju Jose
>Cc: linux-a...@vger.kernel.org; linux-e...@vger.kernel.org; linux-
>ker...@vger.kernel.org; r...@rjwysocki.net; l...@kernel.org;
>tony.l...@inte
This patch adds log_arm_hw_error to the new error notification
method.
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 47 ++-
drivers/ras/ras.c| 5 -
include/linux/ras.h | 7 +--
3 files changed, 31 insertions(+), 28
could be move to the proposed callback method.
https://www.spinics.net/lists/linux-edac/msg10508.html
https://patchwork.kernel.org/patch/10979491/
Shiju Jose (4):
ACPI: APEI: Add support to notify the vendor specific HW errors
ACPI: APEI: Add ghes_handle_memory_failure to the new notification
This patch adds ghes_handle_memory_failure to the new error
notification method.
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 51 ++--
1 file changed, 36 insertions(+), 15 deletions(-)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi
This patch adds ghes_handle_aer to the new error notification method.
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
index 4400d56..ffc309c 100644
--- a
Presently the vendor specific HW errors, in the non-standard format,
are not reported to the vendor drivers for the recovery.
This patch adds support to notify the vendor specific HW errors to the
registered kernel drivers.
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 118
Hi Tyler,
>-Original Message-
>From: linux-acpi-ow...@vger.kernel.org [mailto:linux-acpi-
>ow...@vger.kernel.org] On Behalf Of Tyler Baicar OS
>Sent: 02 July 2019 17:52
>To: Open Source Submission ; linux-arm-
>ker...@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
>a...@vger.ker
> Tony Luck; Mauro Carvalho Chehab; Robert Moore; Erik Schmauss; Tyler
> Baicar; Will Deacon; James Morse; Shiju Jose; Jonathan (Zhixiong) Zhang;
> gengdongjiu; linux-a...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-e...@vger.kernel.org; de...@acpica.org
> Subject: [RFC
Hi James,
> -Original Message-
> From: linux-acpi-ow...@vger.kernel.org [mailto:linux-acpi-
> ow...@vger.kernel.org] On Behalf Of James Morse
> Sent: 16 March 2017 14:26
> To: Shiju Jose
> Cc: r...@rjwysocki.net; l...@kernel.org; b...@suse.de; mi...@kernel.org;
> pr
handler for
notification types SCI, GSIV and GPIO.
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 28 +---
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
index b192b42..fd39929 100644
--- a
Hi Peter,
Thanks for the comments.
> -Original Message-
> From: James Morse [mailto:james.mo...@arm.com]
> Sent: 10 March 2017 17:16
> To: Shiju Jose
> Cc: catalin.mari...@arm.com; will.dea...@arm.com;
> tbai...@codeaurora.org; zjzh...@codeaurora.org; marc.zyng...@a
this is no longer just SCI, but anything from the
Hardware Error Device.
Signed-off-by: Shiju Jose
[james.mo...@arm.com: rewrote commit log]
Signed-off-by: James Morse
CC: James Morse
CC: Hanjun Guo
---
drivers/acpi/apei/ghes.c | 28 +---
1 file changed, 17 insertions(+), 11
work queue for queuing each vendor-specific error record and uses
blocking notifier chain, in the work function, to report the error to
the registered drivers.
The drivers should match the section type of the error record before
processing the error data.
Signed-off-by: Shiju Jose
Reviewed-by: Bjorn
PCIe controller's errors,
which is an application of the above interface.
Shiju Jose (1):
ACPI / APEI: Add support to notify the vendor specific HW errors
Yicong Yang (1):
PCI: hip: Add handling of HiSilicon HIP PCIe controller errors
drivers/acpi/apei/ghes.c | 12
PCIe controller does not use DWC ip.
Signed-off-by: Yicong Yang
Signed-off-by: Shiju Jose
Reviewed-by: Bjorn Helgaas
Reviewed-by: Andy Shevchenko
--
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-hisi-error.c
Hi Andy,
>-Original Message-
>From: Andy Shevchenko [mailto:andriy.shevche...@linux.intel.com]
>Sent: 18 June 2020 16:56
>To: Shiju Jose
>Cc: linux-a...@vger.kernel.org; linux-...@vger.kernel.org; linux-
>ker...@vger.kernel.org; r...@rjwysocki.net; helg...@kernel.or
Hi James,
Thanks for reviewing the patch and the modifications.
>-Original Message-
>From: James Morse [mailto:james.mo...@arm.com]
>Sent: 18 June 2020 19:20
>To: Shiju Jose
>Cc: linux-a...@vger.kernel.org; linux-...@vger.kernel.org; linux-
>ker...@vger.kernel.org;
as run.
Signed-off-by: Shiju Jose
[ Removed kfifo and ghes_gdata_pool. Expanded commit message ]
Signed-off-by: James Morse
---
drivers/acpi/apei/ghes.c | 63
include/acpi/ghes.h | 27 +
2 files changed, 90 insertions(+)
diff --git
rror
for module with multiple devices, but use the same section type.
In the error handler will use socket id/sub module id etc to distinguish
the device.
V1:
1. Fix comments from James Morse.
2. add driver to handle HiSilicon hip08 PCIe controller's errors,
which is an applicat
PCIe controller does not use DWC ip.
Signed-off-by: Yicong Yang
Signed-off-by: Shiju Jose
--
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-hisi-error.c | 336 +++
3 files changed, 345 inser
Add support to notify the vendor specific non-fatal HW errors
to the drivers for the error recovery.
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 130 ++-
include/acpi/ghes.h | 28 +
2 files changed, 157 insertions(+), 1 deletion
to distinguish
the device.
V1:
1. Fix comments from James Morse.
2. add driver to handle HiSilicon hip08 PCIe controller's errors,
which is an application of the above interface.
Shiju Jose (1):
ACPI / APEI: Add support to notify the vendor specific HW errors
Yicong Yang (1):
P
to distinguish
the device.
V1:
1. Fix comments from James Morse.
2. add driver to handle HiSilicon hip08 PCIe controller's errors,
which is an application of the above interface.
Shiju Jose (1):
ACPI / APEI: Add support to notify the vendor specific HW errors
Yicong Yang (1):
P
PCIe controller does not use DWC ip.
Signed-off-by: Yicong Yang
Signed-off-by: Shiju Jose
--
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-hisi-error.c | 336 +++
3 files changed, 345 inser
Hi Rafael,
>-Original Message-
>From: Rafael J. Wysocki [mailto:raf...@kernel.org]
>Sent: 13 July 2020 12:18
>To: Shiju Jose
>Cc: linux-a...@vger.kernel.org; linux-...@vger.kernel.org; linux-
>ker...@vger.kernel.org; r...@rjwysocki.net; helg...@kernel.org;
>b..
Hi Rafael,
>-Original Message-
>From: linux-pci-ow...@vger.kernel.org [mailto:linux-pci-
>ow...@vger.kernel.org] On Behalf Of Rafael J. Wysocki
>Sent: 13 July 2020 14:38
>To: Shiju Jose
>Cc: Rafael J. Wysocki ; linux-a...@vger.kernel.org; linux-
>p...@vger.ker
uish
the device.
V1:
1. Fix comments from James Morse.
2. add driver to handle HiSilicon hip08 PCIe controller's errors,
which is an application of the above interface.
Shiju Jose (1):
ACPI / APEI: Add a notifier chain for unknown (vendor) CPER records
Yicong Yang (1):
PCI: hip:
er has run.
Co-developed-by: James Morse
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 63
include/acpi/ghes.h | 27 +
2 files changed, 90 insertions(+)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
ind
PCIe controller does not use DWC ip.
Signed-off-by: Yicong Yang
Signed-off-by: Shiju Jose
--
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-hisi-error.c | 336 +++
3 files changed, 345 inser
Hi James,
Thanks for the reply and the information shared.
>-Original Message-
>From: James Morse [mailto:james.mo...@arm.com]
>Sent: 02 October 2020 18:33
>To: Shiju Jose
>Cc: Borislav Petkov ; linux-e...@vger.kernel.org; linux-
>a...@vger.kernel.org; linux-kern
Hi Boris, Hi James,
>-Original Message-
>From: Borislav Petkov [mailto:b...@alien8.de]
>Sent: 01 October 2020 18:31
>To: James Morse
>Cc: Shiju Jose ; linux-e...@vger.kernel.org; linux-
>a...@vger.kernel.org; linux-kernel@vger.kernel.org; tony.l...@intel.com;
>
error collection and CPU core isolation?
2.If disabling entire CPU core is not acceptable,
please suggest method to disable L1 and L2 cache on ARM64 core?
Shiju Jose (7):
RAS/CEC: Replace the macro PFN with ELEM_NO
RAS/CEC: Replace pfns_poisoned with elems_poisoned
RAS/CEC: Move X86 MCE
Replace the macro PFN with ELEM_NO for common use.
Signed-off-by: Shiju Jose
---
drivers/ras/cec.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/ras/cec.c b/drivers/ras/cec.c
index 569d9ad2c594..22d11c66c266 100644
--- a/drivers/ras/cec.c
+++ b
Replace the variable pfns_poisoned with elems_poisoned
for the common use.
Signed-off-by: Shiju Jose
---
drivers/ras/cec.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/ras/cec.c b/drivers/ras/cec.c
index 22d11c66c266..f20da1103f27 100644
--- a/drivers/ras
CEC may need to support other architectures such as ARM64.
Move X86 MCE specific code under CONFIG_X86_MCE to support
building for other architectures.
Signed-off-by: Shiju Jose
---
drivers/ras/cec.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/ras/cec.c b/drivers/ras
Modify the function cec_mod_work() for the common use
with the other error sources.
Signed-off-by: Shiju Jose
---
drivers/ras/cec.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/ras/cec.c b/drivers/ras/cec.c
index 803e641d8e5c..f869e7a270b8 100644
--- a
. Implementation details is added in the file.
Signed-off-by: Shiju Jose
---
drivers/ras/cec.c | 125 --
1 file changed, 109 insertions(+), 16 deletions(-)
diff --git a/drivers/ras/cec.c b/drivers/ras/cec.c
index f869e7a270b8..ca52917d514c 100644
--- a
period, it will try to isolate the CPU core.
If disabling entire CPU core is not acceptable, Please suggest
method to disable L1 and L2 cache on ARM64 core?
Signed-off-by: Shiju Jose
---
arch/arm64/ras/Kconfig | 17 +++
drivers/ras/Kconfig| 1 +
drivers/ras/cec.c | 231
Add reporting ARM64 CPU correctable errors to the RAS correctable
errors collector(CEC).
ARM processor error types are cache/TLB/bus errors.
Any of the above error types should not be consider for the
error collection and CPU core isolation?
Signed-off-by: Shiju Jose
---
drivers/acpi/apei
Hi Boris, Hi James,
>-Original Message-
>From: Borislav Petkov [mailto:b...@alien8.de]
>Sent: 02 October 2020 13:44
>To: Shiju Jose
>Cc: linux-e...@vger.kernel.org; linux-a...@vger.kernel.org; linux-
>ker...@vger.kernel.org; tony.l...@intel.com; r...@rjwysocki.net;
&g
d Kernel panic - not syncing: Attempted to kill init!
exitcode=0x000b ]---
Signed-off-by: Shiju Jose
---
drivers/edac/ghes_edac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c
index da60c29468a7..7930643c6811 10064
;hisi_qm_set_vft'
drivers/crypto/hisilicon/qm.c:2420: warning: Function parameter or member
'number' not described in 'hisi_qm_set_vft'
drivers/crypto/hisilicon/qm.c:2620: warning: Function parameter or member 'qm'
not described in 'qm_clear_queues'
Si
ion type.
In the error handler will use socket id/sub module id etc to distinguish
the device.
V1:
1. Fix comments from James Morse.
2. add driver to handle HiSilicon hip08 PCIe controller's errors,
which is an application of the above interface.
Shiju Jose (1):
ACPI /
Add support to report the vendor specific non-fatal HW errors
to the drivers for the error recovery.
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 126 ++-
include/acpi/ghes.h | 28 +
2 files changed, 153 insertions(+), 1 deletion
e
HIP PCIe controller does not use DWC ip.
Signed-off-by: Yicong Yang
Signed-off-by: Shiju Jose
--
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-hisi-error.c | 336 +++
3 files changed
Please ignore this patch set. Resending soon.
Thanks,
Shiju
>-Original Message-
>From: Shiju Jose
>Sent: 29 May 2020 18:39
>To: linux-a...@vger.kernel.org; linux-...@vger.kernel.org; linux-
>ker...@vger.kernel.org; r...@rjwysocki.net; b...@alien8.de;
>james.m
ame section type.
In the error handler will use socket id/sub module id etc to distinguish
the device.
V1:
1. Fix comments from James Morse.
2. add driver to handle HiSilicon hip08 PCIe controller's errors,
which is an application of the above interface.
Shiju Jose (1):
e
HIP PCIe controller does not use DWC ip.
Signed-off-by: Yicong Yang
Signed-off-by: Shiju Jose
--
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-hisi-error.c | 336 +++
3 files changed
Add support to report the vendor specific non-fatal HW errors
to the drivers for the error recovery.
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 130 ++-
include/acpi/ghes.h | 28 +
2 files changed, 157 insertions(+), 1 deletion
Hi Boris, Hi James,
>-Original Message-
>From: linux-pci-ow...@vger.kernel.org [mailto:linux-pci-
>ow...@vger.kernel.org] On Behalf Of James Morse
>Sent: 08 April 2020 11:03
>To: Borislav Petkov ; Shiju Jose
>Cc: linux-a...@vger.kernel.org; linux-...@vger.kerne
Add error recovery for the PCIe local errors
2.Removed code for the other OEM errors from HIP08 edac driver
because there is no current requirement for the recovery.
Shiju Jose (2):
EDAC: Add support for reporting the non-standard errors to the vendor
drivers
EDAC: Add handling for
merate_dimms() again.
Suggested-by: Borislav Petkov
Signed-off-by: Shiju Jose
---
drivers/edac/ghes_edac.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c
index da60c29468a7..54ebc8afc6b1 100644
--- a/drivers/ed
Sorry. Please ignore this.
>-Original Message-
>From: linux-edac-ow...@vger.kernel.org [mailto:linux-edac-
>ow...@vger.kernel.org] On Behalf Of Shiju Jose
>Sent: 27 August 2020 15:01
>To: linux-e...@vger.kernel.org; linux-kernel@vger.kernel.org; b...@alien8.de;
>mche...@
Hello Boris,
Thanks for reviewing.
>-Original Message-
>From: linux-edac-ow...@vger.kernel.org [mailto:linux-edac-
>ow...@vger.kernel.org] On Behalf Of Borislav Petkov
>Sent: 26 August 2020 09:52
>To: Shiju Jose
>Cc: linux-e...@vger.kernel.org; linux-kernel@vger
Hi Andy,
>-Original Message-
>From: Andy Shevchenko [mailto:andriy.shevche...@linux.intel.com]
>Sent: 01 September 2020 09:26
>To: Shiju Jose
>Cc: linux-a...@vger.kernel.org; linux-...@vger.kernel.org; linux-
>ker...@vger.kernel.org; r...@rjwysocki.net; helg...@kernel
PCIe controller does not use DWC IP.
Signed-off-by: Yicong Yang
Signed-off-by: Shiju Jose
Acked-by: Bjorn Helgaas
--
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-hisi-error.c | 336 +++
3
face to support reporting the vendor error
for module with multiple devices, but use the same section type.
In the error handler will use socket id/sub module id etc to distinguish
the device.
V1:
1. Fix comments from James Morse.
2. add driver to handle HiSilicon hip08 PCIe controller&#
er has run.
Co-developed-by: James Morse
Signed-off-by: James Morse
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 63
include/acpi/ghes.h | 18
2 files changed, 81 insertions(+)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/a
the CPU core.
The threshold value, time period etc are configurable.
Implementation details is added in the file.
Signed-off-by: Shiju Jose
---
Documentation/ABI/testing/debugfs-cpu-cec | 22 ++
arch/arm64/ras/Kconfig| 8 +
drivers/acpi/apei/ghes.c | 30
Hi Boris,
>-Original Message-
>From: Borislav Petkov [mailto:b...@alien8.de]
>Sent: 01 September 2020 15:36
>To: Shiju Jose
>Cc: linux-e...@vger.kernel.org; linux-a...@vger.kernel.org; linux-
>ker...@vger.kernel.org; tony.l...@intel.com; r...@rjwysocki.net;
>j
le id etc to distinguish
the device.
V1:
1. Fix comments from James Morse.
2. add driver to handle HiSilicon hip08 PCIe controller's errors,
which is an application of the above interface.
Shiju Jose (1):
ACPI / APEI: Add a notifier chain for unknown (vendor) CPER records
Yic
er has run.
Co-developed-by: James Morse
Signed-off-by: James Morse
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 63
include/acpi/ghes.h | 18
2 files changed, 81 insertions(+)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/a
PCIe controller does not use DWC IP.
Signed-off-by: Yicong Yang
Signed-off-by: Shiju Jose
Acked-by: Bjorn Helgaas
--
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-hisi-error.c | 336 +++
3
ma_setup'
drivers/acpi/arm64/iort.c:1142: warning: Excess function parameter 'size'
description in 'iort_dma_setup'
drivers/acpi/arm64/iort.c:1534: warning: Function parameter or member 'ops' not
described in 'iort_add_platform_device'
Signed-off-by: Shiju
Add reporting ARM64 CPU cache corrected error count to the ghes_edac.
The error count would be updated in the EDAC CPU cache sysfs
interface.
Signed-off-by: Jonathan Cameron
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 79 ++--
include/linux
.
User-space application could monitor the recorded corrected error
count for the early fault detection.
Jonathan Cameron (1):
ACPI: PPTT: Fix for a high level cache node detected in the low level
Shiju Jose (3):
ACPI: PPTT: Add function acpi_find_cache_info
EDAC/ghes: Add EDAC device for
-by: James Morse
Signed-off-by: Jonathan Cameron
Signed-off-by: Shiju Jose
---
drivers/edac/Kconfig | 10 +++
drivers/edac/ghes_edac.c | 135 +++
include/acpi/ghes.h | 27
3 files changed, 172 insertions(+)
diff --git a/drivers/edac/Kconfig
n check in the acpi_find_cache_level(),
for a cache node found in the private resource of a CPU node
with all the next level of caches present in the other cache nodes.
Signed-off-by: Jonathan Cameron
Co-developed-by: Shiju Jose
Signed-off-by: Shiju Jose
---
drivers/acpi/p
Add function acpi_find_cache_info() to find the
information of the caches found in a CPU hierarchy
represented in the PPTT.
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
Signed-off-by: Shiju Jose
---
drivers/acpi/pptt.c | 62
Hi James,
Thanks for the feedback.
>-Original Message-
>From: James Morse [mailto:james.mo...@arm.com]
>Sent: 06 November 2020 19:34
>To: Shiju Jose ; linux-kernel@vger.kernel.org;
>b...@alien8.de; tony.l...@intel.com; r...@rjwysocki.net; l...@kernel.org;
>rrich...@marv
Adding Lorenzo.
Thanks,
Shiju
>-Original Message-
>From: linux-acpi-ow...@vger.kernel.org [mailto:linux-acpi-
>ow...@vger.kernel.org] On Behalf Of Shiju Jose
>Sent: 22 July 2020 11:43
>To: linux-a...@vger.kernel.org; linux-...@vger.kernel.org; linux-
>ker...@
Hi Bjorn,
Thanks for reviewing.
>-Original Message-
>From: Bjorn Helgaas [mailto:helg...@kernel.org]
>Sent: 24 July 2020 00:21
>To: Shiju Jose
>Cc: linux-a...@vger.kernel.org; linux-...@vger.kernel.org; linux-
>ker...@vger.kernel.org; r...@rjwysocki.net; b...@al
Hi Bjorn,
>-Original Message-
>From: Bjorn Helgaas [mailto:helg...@kernel.org]
>Sent: 24 July 2020 00:23
>To: Shiju Jose
>Cc: linux-a...@vger.kernel.org; linux-...@vger.kernel.org; linux-
>ker...@vger.kernel.org; r...@rjwysocki.net; b...@alien8.de;
>james.mo...@arm
>-Original Message-
>From: Bjorn Helgaas [mailto:helg...@kernel.org]
>Sent: 24 July 2020 13:54
>To: Shiju Jose
>Cc: linux-a...@vger.kernel.org; linux-...@vger.kernel.org; linux-
>ker...@vger.kernel.org; r...@rjwysocki.net; b...@alien8.de;
>james.mo...@arm.com; l.
er has run.
Co-developed-by: James Morse
Signed-off-by: Shiju Jose
---
drivers/acpi/apei/ghes.c | 63
include/acpi/ghes.h | 27 +
2 files changed, 90 insertions(+)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
ind
section type.
In the error handler will use socket id/sub module id etc to distinguish
the device.
V1:
1. Fix comments from James Morse.
2. add driver to handle HiSilicon hip08 PCIe controller's errors,
which is an application of the above interface.
Shiju Jose (1):
ACPI / APE
section type.
In the error handler will use socket id/sub module id etc to distinguish
the device.
V1:
1. Fix comments from James Morse.
2. add driver to handle HiSilicon hip08 PCIe controller's errors,
which is an application of the above interface.
Shiju Jose (1):
ACPI / APE
PCIe controller does not use DWC IP.
Signed-off-by: Yicong Yang
Signed-off-by: Shiju Jose
Acked-by: Bjorn Helgaas
--
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-hisi-error.c | 336 +++
3
Hi Andy,
>-Original Message-
>From: Andy Shevchenko [mailto:andriy.shevche...@linux.intel.com]
>Sent: 22 July 2020 12:02
>To: Shiju Jose
>Cc: linux-a...@vger.kernel.org; linux-...@vger.kernel.org; linux-
>ker...@vger.kernel.org; r...@rjwysocki.net; helg...@kernel.or
Hi Rafael, Hi James,
Can you help to merge this patch because I added and tested all the suggestions
from James.
Thanks,
Shiju
>-Original Message-
>From: linux-pci-ow...@vger.kernel.org [mailto:linux-pci-
>ow...@vger.kernel.org] On Behalf Of Shiju Jose
>Sent: 22 June 20
Hello Boris,
>-Original Message-
>From: Borislav Petkov [mailto:b...@alien8.de]
>Sent: 09 September 2020 13:02
>To: Shiju Jose
>Cc: linux-e...@vger.kernel.org; linux-a...@vger.kernel.org; linux-
>ker...@vger.kernel.org; tony.l...@intel.com; r...@rjwysocki.net;
>j
Hello,
Can you help to merge this series?
Thanks,
Shiju
>-Original Message-
>From: Linuxarm [mailto:linuxarm-boun...@huawei.com] On Behalf Of Shiju
>Jose
>Sent: 03 September 2020 13:35
>To: linux-a...@vger.kernel.org; linux-...@vger.kernel.org; linux-
>ker...@
Hi Boris,
Sorry for the delay.
>-Original Message-
>From: Borislav Petkov [mailto:b...@alien8.de]
>Sent: 11 September 2020 17:48
>To: Shiju Jose
>Cc: linux-e...@vger.kernel.org; linux-kernel@vger.kernel.org;
>mche...@kernel.org; tony.l...@intel.com; james.mo...@
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